Hello mturney mturney,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to review the following change.
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/include/soc/symbols.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 16 files changed, 319 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/1
diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index 5cd7981..d177c0e 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -5,3 +5,4 @@ ## Platforms
- [SC7180 series](sc7180/index.md) +- [SC7280 series](sc7280/index.md) diff --git a/Documentation/soc/qualcomm/sc7280/index.md b/Documentation/soc/qualcomm/sc7280/index.md new file mode 100644 index 0000000..9dad39c --- /dev/null +++ b/Documentation/soc/qualcomm/sc7280/index.md @@ -0,0 +1,19 @@ +# Qualcomm SC7280 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. + + diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig new file mode 100644 index 0000000..fc2f34b --- /dev/null +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -0,0 +1,27 @@ + +config SOC_QUALCOMM_SC7280 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + +if SOC_QUALCOMM_SC7280 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7280/memlayout.ld" + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000..2bed326 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,36 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += spi.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +endif diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c new file mode 100644 index 0000000..807bb25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7280_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c new file mode 100644 index 0000000..4b9eb37 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h new file mode 100644 index 0000000..70d17be --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h new file mode 100644 index 0000000..82a0c39 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_GPIO_H_ +#define _SOC_QUALCOMM_SC7280_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + +#endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/mmu.h b/src/soc/qualcomm/sc7280/include/soc/mmu.h new file mode 100644 index 0000000..5a2984f --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_MMU_H_ +#define _SOC_QUALCOMM_SC7280_MMU_H_ + +void sc7280_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7280_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/symbols.h b/src/soc/qualcomm/sc7280/include/soc/symbols.h new file mode 100644 index 0000000..e930638 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/symbols.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7280_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_aop) +DECLARE_REGION(dram_soc) +DECLARE_REGION(dcb) +DECLARE_REGION(pmic) +DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop) + +#endif /* _SOC_QUALCOMM_SC7280_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld new file mode 100644 index 0000000..94300e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + FMAP_CACHE(0x14853400, 2K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 44K, 4K) + REGION(limits_cfg, 0x1486a000, 4K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c new file mode 100644 index 0000000..9905c29 --- /dev/null +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7280_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7280/qclib.c b/src/soc/qualcomm/sc7280/qclib.c new file mode 100644 index 0000000..6affc63 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qclib.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c new file mode 100644 index 0000000..7233d38 --- /dev/null +++ b/src/soc/qualcomm/sc7280/soc.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7280_ops = { + CHIP_NAME("SOC Qualcomm SC7280") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c new file mode 100644 index 0000000..50aa395 --- /dev/null +++ b/src/soc/qualcomm/sc7280/spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7280/timer.c b/src/soc/qualcomm/sc7280/timer.c new file mode 100644 index 0000000..19e466a --- /dev/null +++ b/src/soc/qualcomm/sc7280/timer.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +}
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45205/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/2//COMMIT_MSG@7 PS2, Line 7: sc7280 Please start to put the vendor in the prefix too.
qualcomm/sc7280: …
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45205/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/2//COMMIT_MSG@7 PS2, Line 7: sc7280
Please start to put the vendor in the prefix too. […]
Is there a rule about that? Considering that patch subject space is often too short to really convey a good summary of a patch anyway, I don't think we should force people to waste too much of it on prefix. SoC names don't really clash between vendors.
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/inc... File src/soc/qualcomm/sc7280/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/inc... PS6, Line 15: DECLARE_REGION(aop) Should probably just dump these into <soc/symbols_common.h> rather than duplicate between chips. Extra symbols don't hurt even if a chip isn't using them.
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/qcl... File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/qcl... PS6, Line 9: int qclib_soc_blob_load(void) Please factor this out in qualcomm/common if it's needed by more than one SoC. Since all the SoC's we're using for now need it anyway, I'd just throw it into qclib_load_and_run(). If you really want to keep it separate you could guard it with a Kconfig, or make a separate qclib_add_pmic_stuff() and call that from here or something.
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/tim... File src/soc/qualcomm/sc7280/timer.c:
https://review.coreboot.org/c/coreboot/+/45205/6/src/soc/qualcomm/sc7280/tim... PS6, Line 7: void init_timer(void) Should consider putting this in qualcomm/common and just using SRC_XO_HZ from <soc/clock.h> for the frequency (or define a separate ARCH_TIMER_HZ in each <soc/clock.h> that can then be defined to SRC_XO_HZ or whatever else it might be for each individual SoC).
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#7).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M 3rdparty/qc_blobs M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/include/soc/symbols.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 17 files changed, 331 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#12).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M 3rdparty/qc_blobs M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/include/soc/symbols.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 17 files changed, 331 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/12
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45205/14/3rdparty/qc_blobs File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/14/3rdparty/qc_blobs@1 PS14, Line 1: 355fff30cbb98882664743ef62a65cbaa958e715 that commit isn't on gerrit, so this CL can't be checked out by the builder.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 15: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45205/15/3rdparty/qc_blobs File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/15/3rdparty/qc_blobs@1 PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715 This commit doesn't exist. The builds will keep failing until this is removed, or the qc_blobs tree is updated to contain this commit (which won't actually happen, because the commit ID will be changed when it merges due to updated commit messages.)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45205/15//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/15//COMMIT_MSG@8 PS15, Line 8: Please elaborate, what the SoC is, if the code was copied or written from scratch, and what datasheets (name and revision) were used.
Attention is currently required from: Ravi kumar. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 22:
(1 comment)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/64523918_687877c2 PS22, Line 28: /* Attempt to load Limits Config Blob */ : ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, : REGION_SIZE(limits_cfg)); : if (ssize < 0) : return -1; : qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, : _limits_cfg, ssize, 0); This is not in the sc7180 soc code. From talking to Juilus, it seemed like it was removed in the previous generation. Can you briefly explain what this blob does and why we need it in the sc7280 soc?
Attention is currently required from: Ravi kumar. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#24).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M 3rdparty/qc_blobs M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 17 files changed, 322 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/24
Attention is currently required from: Ravi kumar, Paul Menzel, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 24:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/63955619_d41e6f3b PS2, Line 7: sc7280
Is there a rule about that? Considering that patch subject space is often too short to really convey […]
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/fc7cc450_2a0a45e4 PS2, Line 7: sc7280
Is there a rule about that? Considering that patch subject space is often too short to really convey […]
Done
File src/soc/qualcomm/sc7280/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/45205/comment/606c8741_85be1015 PS6, Line 15: DECLARE_REGION(aop)
Should probably just dump these into <soc/symbols_common.h> rather than duplicate between chips. […]
Done
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/da37c8af_3db27737 PS6, Line 9: int qclib_soc_blob_load(void)
Please factor this out in qualcomm/common if it's needed by more than one SoC. […]
Sure julius, We will make this change once discuss with internal team
File src/soc/qualcomm/sc7280/timer.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/390c9348_02c710f1 PS6, Line 7: void init_timer(void)
Should consider putting this in qualcomm/common and just using SRC_XO_HZ from <soc/clock. […]
Sure julius, we will make this change once discuss with internal team
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 24:
(1 comment)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/dbd9920e_12bf2bcb PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
This commit doesn't exist. […]
Ravi, you need to resolve this before any of your patches can land in coreboot.org.
Attention is currently required from: Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 24:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/363345c5_c48bf4e3 PS2, Line 7: sc7280
Done
I do not know of any documented rule. Looking through the summaries with `git log --oneline`, it is nice to have the vendor in the prefix, as not everybody knows every model name, and cannot map it.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Ravi Kumar Bokka. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 24:
(6 comments)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/93d28be6_b0737b41 PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
Ravi, you need to resolve this before any of your patches can land in coreboot.org.
So just to make things easier, the way you fix this is:
1. Go into your coreboot Git checkout 2. Make sure you have this patch on top (e.g. via rebase --interactive or something) 3. `cd 3rdparty/qc_blobs` 4. `git checkout 6b7fe498eb782b` 5. `cd ../..` 6. `git add 3rdparty/qc_blobs` 7. `git commit --amend`
That should bring you back to the old qc_blobs version. Submodule checkouts are basically tracked like normal files in git. If you need a submodule checkout to some internal unreleased qc_blobs version to test this, put that in a separate HACK patch at the end of this patch train for now.
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45205/comment/43e5c281_a6d7a27a PS24, Line 12: verstage-y += spi.c nit: btw, our build system now supports `all-y += ...` as a shorthand for adding files like this to every stage
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/5ddc3a58_d15e2ea3 PS24, Line 8: #define SSRAM_END(addr) SYMBOL(essram, addr) This was recently changed, please use REGION_START() and REGION_END() for these. See https://review.coreboot.org/c/coreboot/+/49332/13/src/soc/qualcomm/sc7180/me...
https://review.coreboot.org/c/coreboot/+/45205/comment/72e24b5e_1710e4ff PS24, Line 42: FMAP_CACHE(0x1485B400, 2K) Please fit a CBFS_MCACHE() area of at least 8K in here somewhere, that was also a recent addition. See https://review.coreboot.org/c/coreboot/+/38424/24/src/soc/qualcomm/sc7180/me...
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/61133651_ebc691a7 PS24, Line 12: ssize_t ssize; We've had typo errors with stuff like this before... please just use a single ssize_t variable for all of these (the cbfs_boot_load_file() results will not overflow 63 bits).
https://review.coreboot.org/c/coreboot/+/45205/comment/d4615677_2607a6ce PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", This API was recently renamed and is now called cbfs_load() with slightly simplified signature (see https://review.coreboot.org/c/coreboot/+/39304/18/src/soc/qualcomm/sc7180/qc...).
Please rebase this patch train onto the newest master and see if you have more issues like that.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Ravi Kumar Bokka. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#25).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M 3rdparty/qc_blobs M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 17 files changed, 315 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/25
Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 25:
(4 comments)
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/8968501f_ee8adc9a PS24, Line 8: #define SSRAM_END(addr) SYMBOL(essram, addr)
This was recently changed, please use REGION_START() and REGION_END() for these. See https://review. […]
i will update
https://review.coreboot.org/c/coreboot/+/45205/comment/d976dad2_b8c6e64f PS24, Line 42: FMAP_CACHE(0x1485B400, 2K)
Please fit a CBFS_MCACHE() area of at least 8K in here somewhere, that was also a recent addition. […]
sure i will update
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/e0e33921_64542080 PS24, Line 12: ssize_t ssize;
We've had typo errors with stuff like this before... […]
addressed in below patch https://review.coreboot.org/c/coreboot/+/49013/5/src/soc/qualcomm/sc7280/qcl...
i will update this soc patch individually
https://review.coreboot.org/c/coreboot/+/45205/comment/0d909e90_a8b6c6d8 PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
This API was recently renamed and is now called cbfs_load() with slightly simplified signature (see […]
addressed in below patch https://review.coreboot.org/c/coreboot/+/49013/5/src/soc/qualcomm/sc7280/qcl...
i will update this soc patch individually
Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 25:
(2 comments)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/32614ca4_30a46f68 PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
So just to make things easier, the way you fix this is: […]
if i checkout with below command: git checkout 6b7fe498eb782b
its pointing to previous stage. In that case, suspecing, we may loose additional functionality from qc_blobs.
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45205/comment/68465c9b_3d68a54e PS24, Line 12: verstage-y += spi.c
nit: btw, our build system now supports `all-y += ... […]
sure i will update
Attention is currently required from: Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 25:
(1 comment)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/9fc42bf8_db6e3a4f PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
if i checkout with below command: […]
What dependency do you have with qc_blobs for this CL (or other following CLs)?
Are you unable to test with the qc_blobs update in a HACK patch at the end of the patch train per Julius' recommendation? That would at least unblock the Jenkins issue preventing this CL from getting landed.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 25:
(1 comment)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/7206486e_a32f53f3 PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
What dependency do you have with qc_blobs for this CL (or other following CLs)? […]
This patch should now pass the build-bot. The reference to blobs in Makefile.inc is to sc7180 blobs which should be present in upstream repository. It is noted this is incorrect and will be corrected when initial sc7280 blobs are available. We fix this, temporarily, with a later hack patch that restores the blob reference to sc7280.
Attention is currently required from: Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 25:
(3 comments)
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/6a4dd354_9cfb8d97 PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
This patch should now pass the build-bot. […]
Hi Mike, do you mean this patch should be passing as is? It's still verified -1 so I'm assuming another patch will be uploaded soon?
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/89bc69c8_3351e203 PS24, Line 12: ssize_t ssize;
addressed in below patch […]
I don't see this change in the other CL yet. But also, is there any reason why the changes in https://review.coreboot.org/c/coreboot/+/49013/ should not be merged into this CL as well instead of being fixed in a future CL?
https://review.coreboot.org/c/coreboot/+/45205/comment/3a9002b3_92c7f06d PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
addressed in below patch […]
Same comment as above. I think that these changes should be merged into this patch.
Attention is currently required from: Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner, mturney mturney. mturney mturney has uploaded a new patch set (#26) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 16 files changed, 314 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/26
Attention is currently required from: Ravi kumar, Martin Roth, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 26:
(3 comments)
Patchset:
PS26: Thanks, Mike, for resolving the build issue!
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/27f40a22_fd4e1ce0 PS14, Line 1: 355fff30cbb98882664743ef62a65cbaa958e715
that commit isn't on gerrit, so this CL can't be checked out by the builder.
Done
File 3rdparty/qc_blobs:
https://review.coreboot.org/c/coreboot/+/45205/comment/98cdc3e5_0a2257cc PS15, Line 1: Subproject commit 355fff30cbb98882664743ef62a65cbaa958e715
Hi Mike, do you mean this patch should be passing as is? It's still verified -1 so I'm assuming ano […]
Done
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 26:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/84bb00fe_5644e426 PS15, Line 8:
Please elaborate, what the SoC is, if the code was copied or written from scratch, and what datashee […]
Agreed. Please write a brief description and also please include:
BUG=b:182963902 TEST= (how you tested that this code was correct)
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#27).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M 3rdparty/qc_blobs M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 17 files changed, 315 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/27
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. mturney mturney has uploaded a new patch set (#29) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 16 files changed, 314 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/29
Attention is currently required from: Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. mturney mturney has uploaded a new patch set (#30) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 305 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/30
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#31).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 306 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/31
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. mturney mturney has uploaded a new patch set (#32) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 305 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/32
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#33).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 306 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/33
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Julius Werner, mturney mturney. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 33:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/617effab_8e8cecdd PS15, Line 8:
Agreed. Please write a brief description and also please include: […]
Ack
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/fff877f2_eebcbf92 PS24, Line 8: #define SSRAM_END(addr) SYMBOL(essram, addr)
i will update
addressed
https://review.coreboot.org/c/coreboot/+/45205/comment/c3fc56e8_74961cff PS24, Line 42: FMAP_CACHE(0x1485B400, 2K)
sure i will update
Ack
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/94839421_76a5acbc PS6, Line 9: int qclib_soc_blob_load(void)
Sure julius, […]
Ack
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/d623adea_30a2ee61 PS24, Line 12: ssize_t ssize;
I don't see this change in the other CL yet. […]
Ack
https://review.coreboot.org/c/coreboot/+/45205/comment/1c408e01_e12efc6e PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
Same comment as above. I think that these changes should be merged into this patch.
addressed
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 33:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/c5f114a2_9677118b PS15, Line 8:
Ack
Hey Ravi, I don't see the commit message updated in this latest patchset. Can you please update it as requested?
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/7169a932_76de0841 PS24, Line 42: FMAP_CACHE(0x1485B400, 2K)
Ack
I don't see CBFS_MCACHE in the latest patchset.
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/9f2839f5_d30b36f0 PS6, Line 9: int qclib_soc_blob_load(void)
Ack
Ravi, did you end up refactoring this out as Julius suggested?
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/2171ff83_2ab53733 PS24, Line 12: ssize_t ssize;
Ack
I still don't see this correction?
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#34).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST= validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 307 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/34
Attention is currently required from: Shelley Chen, Martin Roth, Paul Menzel, Julius Werner, mturney mturney. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 33:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/e778b91e_7c2bf827 PS15, Line 8:
Hey Ravi, I don't see the commit message updated in this latest patchset. […]
Done
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/569824d5_b2b9653e PS24, Line 8: #define SSRAM_END(addr) SYMBOL(essram, addr)
addressed
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/08886646_8b331670 PS24, Line 42: FMAP_CACHE(0x1485B400, 2K)
I don't see CBFS_MCACHE in the latest patchset.
Done
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/24f07dc6_0834b7e9 PS6, Line 9: int qclib_soc_blob_load(void)
Ravi, did you end up refactoring this out as Julius suggested?
sorry for late response, i will acknowledge, the difference is limits config changes i need to remove from sc7280. once confirm with internal team i will move to common code.
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/0f63751a_fe0791bb PS24, Line 12: ssize_t ssize;
I still don't see this correction?
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/48d8f287_11414258 PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
addressed
Done
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 34:
(1 comment)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/ba554ffe_26fcd691 PS24, Line 12: ssize_t ssize;
Done
I thought that Julius was asking to only have one size variable (for example ssize_t size) and use it throughout the code rather than defining both size and ssize due to how error prone it is? Julius can correct me if I misunderstood.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 34:
(1 comment)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/05ee6ac8_c9f6e666 PS6, Line 9: int qclib_soc_blob_load(void)
sorry for late response, i will acknowledge, the difference is limits config changes i need to remov […]
common code between trogdor and herobrine has been factored into common/. trogdor qclib.c file will disappear and herobrine will only load limits. Separately a response as to what limits is being used for will be provided.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 34:
(1 comment)
File src/soc/qualcomm/sc7280/timer.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/ccb1c747_ef1bbb31 PS6, Line 7: void init_timer(void)
Sure julius, […]
sc7280 doesn't have include/soc/clock.h file at this point in the patch-train. I suggest we defer this change until the header file is introduced to herobrine and then update the common function.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 34:
(1 comment)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/fb982f92_011a9592 PS22, Line 28: /* Attempt to load Limits Config Blob */ : ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, : REGION_SIZE(limits_cfg)); : if (ssize < 0) : return -1; : qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, : _limits_cfg, ssize, 0);
This is not in the sc7180 soc code. […]
We are working on providing a short description of this qclib dependency in the commit message. Note that this isn't a blob per-se as it isn't read from cbfs container, similar to pmiccfg. It is more akin to the ddr training data that is stored once it is generated at runtime.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has uploaded a new patch set (#35) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 17 files changed, 312 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/35
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 35:
(4 comments)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/ec38ff14_d461e311 PS6, Line 9: int qclib_soc_blob_load(void)
common code between trogdor and herobrine has been factored into common/. […]
Done
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/cbcb4a85_9e229837 PS22, Line 28: /* Attempt to load Limits Config Blob */ : ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, : REGION_SIZE(limits_cfg)); : if (ssize < 0) : return -1; : qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, : _limits_cfg, ssize, 0);
We are working on providing a short description of this qclib dependency in the commit message. […]
Ack. Ravi will respond when he gets this information.
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/555dd9be_57546313 PS24, Line 12: ssize_t ssize;
I thought that Julius was asking to only have one size variable (for example ssize_t size) and use i […]
Done
File src/soc/qualcomm/sc7280/timer.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/9cc36be5_9b4fb239 PS6, Line 7: void init_timer(void)
sc7280 doesn't have include/soc/clock.h file at this point in the patch-train. […]
Ack. This file is not available yet. Will modify when the macro is available later on the in patch train.
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 35: Code-Review+2
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. mturney mturney has uploaded a new patch set (#36) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 17 files changed, 314 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/36
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 36: Code-Review+2
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 36:
(2 comments)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/31136ae6_a1596b1e PS36, Line 159: Something isn't right here... you're adding this to common/qclib.c but I don't see you removing it from sc7180/qclib.c. You still need to keep sc7180 working when you add sc7280 stuff or factor code out into common.
Please do the "factoring out into common" stuff in a separate patch preceding this one, and then the "add sc7280 support" patch should really only contain sc7280 stuff.
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/5feb9019_690fc431 PS36, Line 14: QCLIB_FR_LIMITS_CFG_DATA Just to double-check, we are sure that the limits_cfg data will never need to be updated throughout the lifetime of the device after it was initially written in the factory, right? Because right now this is defined as an RO flash section. For the DDR training data on Trogdor we also originally started with the assumption that it would never need to be updated and then changed our mind later, so I want to make sure we think about this from the start for this one.
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, mturney mturney. Shelley Chen has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Removed Code-Review+2 by Shelley Chen shchen@google.com
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#37).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 18 files changed, 290 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/37
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Julius Werner, mturney mturney. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 37:
(2 comments)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/86b4c1d6_ac35fc9b PS36, Line 159:
Something isn't right here... you're adding this to common/qclib. […]
Ack
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/75e735e2_39bee1b8 PS36, Line 14: QCLIB_FR_LIMITS_CFG_DATA
Just to double-check, we are sure that the limits_cfg data will never need to be updated throughout […]
Done
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Julius Werner, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#38).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 19 files changed, 314 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/38
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 38:
(1 comment)
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/d92e7e30_062ffcb0 PS36, Line 14: QCLIB_FR_LIMITS_CFG_DATA
Done
As communicated to Shelley, sc7280 does not require limits after all and all support for it will be removed.
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 38:
(1 comment)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/6cb9e01f_a00e8f03 PS36, Line 159:
Ack
The intent was to do this as separate patches and we may have messed up the order, until the first couple of patches are landed it is really difficult to simulate the build-bot activity by stopping at each patch and compiling individually. Once the soc/ and mainboard/ patches land upstream I expect these types of issues will be caught before they get to upstream community to review.
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#39).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 18 files changed, 290 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/39
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 39:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/70568201_a9627eb2 PS15, Line 8:
Done
Still no commit message body with that information.
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 39:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/f9ebda4f_b6f9f6b9 PS15, Line 8:
Still no commit message body with that information.
[Paul]: Please elaborate, what the SoC is, if the code was copied or written from scratch, and what datasheets (name and revision) were used.
[Ravi]: The SOC name is mentioned as sc7280 in the commit message. and the code has been referenced from sc7180(trogdor) with few memory region related changes in memlayout.ld to support sc7280. Is this the information you are looking for? please let me know.
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 39:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/555e23ba_a04e2b96 PS15, Line 8:
as per internal discussion, The SoC data sheet is available only for internally today, we cannot share out side of the QC.
Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, Paul Menzel, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#40).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c A src/soc/qualcomm/common/timer.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 18 files changed, 291 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/40
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 40:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/aa63a6b1_8ac92129 PS15, Line 8:
as per internal discussion, The SoC data sheet is available only for internally today, we cannot sha […]
Yes, please add the name and revision nevertheless, in case it gets public in the future, or interested parties can *try to* request it from Qualcomm.
Attention is currently required from: Shelley Chen, Martin Roth, Ravi Kumar Bokka, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#41).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 13 files changed, 261 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/41
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 41:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/2820a8fa_fd10d234 PS41, Line 8: The main question, that needs to be answered from my point of view is, what the difference to SC7180 is, and why the difference is big enough, that it’s a new directory.
https://review.coreboot.org/c/coreboot/+/45205/comment/7c0cd685_01f60547 PS41, Line 10: qualcomm sc7280 developement board herobrine?
https://review.coreboot.org/c/coreboot/+/45205/comment/8ba4351f_c30c0171 PS41, Line 10: TEST=Validated on qualcomm sc7280 developement board What worked? Judging from the code not much, so maybe write, it’s just build tested?
File Documentation/soc/qualcomm/sc7280/index.md:
https://review.coreboot.org/c/coreboot/+/45205/comment/9ce1bf12_01612fe5 PS41, Line 18: Please remove the blank lines at the end of the file.
File src/soc/qualcomm/sc7280/Kconfig:
https://review.coreboot.org/c/coreboot/+/45205/comment/e9869468_49dfb812 PS41, Line 1: Please remove this blank line.
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45205/comment/c9c97802_8b83a6e5 PS41, Line 1: Please remove the blank line.
File src/soc/qualcomm/sc7280/bootblock.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/c0717515_e8f132ff PS41, Line 8: sc7280_mmu_init(); For the SC7180 this is done in decompressor.
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/b9882b8d_972472c1 PS41, Line 30: 84K Why not 83K as in SC7180?
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 41:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/cc55553b_71dfd750 PS41, Line 8:
The main question, that needs to be answered from my point of view is, what the difference to SC7180 […]
This is a completely new/different SoC. Do completely new/different SoCs not generally get a new folder/directory? Specific features and differences are unlikely to be published by QC in a public forum like this, and certainly not before any official public announcement of the chip.
https://review.coreboot.org/c/coreboot/+/45205/comment/557a479c_00d3c124 PS41, Line 10: qualcomm sc7280 developement board
herobrine?
herobrine is the Google designation for this board, which has not been spun yet. QC is in the process of doing initial hardware bring-up, so current testing is mainly done on QC hardware, typically called a CDP board.
https://review.coreboot.org/c/coreboot/+/45205/comment/75cf3003_f79dd616 PS41, Line 10: TEST=Validated on qualcomm sc7280 developement board
What worked? Judging from the code not much, so maybe write, it’s just build tested?
You are correct, for this first patch, only build-tested is valid. The whole patch-train has been tested on QC hardware and does boot to linux kernel login on console.
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 41:
(1 comment)
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/646d2331_5dccde79 PS41, Line 30: 84K
Why not 83K as in SC7180?
We are expecting to add a 1K watchdog tombstone region here, which will come later, so for time being we are using the 1K in pbl_timestamps so there isn't a memory hole. The watchdog tombstone region got added later in Trogdor, so this is just future planning for what we know is required.
Attention is currently required from: Shelley Chen, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#42).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 13 files changed, 257 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/42
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 42:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/f8d0c83d_5fa791e6 PS15, Line 8:
Yes, please add the name and revision nevertheless, in case it gets public in the future, or interes […]
as per qcom policy, we are not permitted to share any document/ revision number externally. Internal SoC datasheets are accessible to customer through Qualcomm portal. we can’t share more to general public without involving PDM/Legal et al.
File Documentation/soc/qualcomm/sc7280/index.md:
https://review.coreboot.org/c/coreboot/+/45205/comment/7e56e08d_21c8f63a PS41, Line 18:
Please remove the blank lines at the end of the file.
Ack
File src/soc/qualcomm/sc7280/Kconfig:
https://review.coreboot.org/c/coreboot/+/45205/comment/0533bc19_688aacdf PS41, Line 1:
Please remove this blank line.
Done
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45205/comment/48fa5873_3a4f818d PS41, Line 1:
Please remove the blank line.
Ack
https://review.coreboot.org/c/coreboot/+/45205/comment/44db7f92_1b1571c8 PS41, Line 1:
Please remove the blank line.
Done
File src/soc/qualcomm/sc7280/bootblock.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/9c221311_c576e2bc PS41, Line 8: sc7280_mmu_init();
For the SC7180 this is done in decompressor.
Ack
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 42:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/f93778a1_f68ebabd PS15, Line 8:
as per qcom policy, we are not permitted to share any document/ revision number externally. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/5bed6f20_52c33496 PS41, Line 8:
This is a completely new/different SoC. […]
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/57f43f7a_c6088b6c PS41, Line 10: TEST=Validated on qualcomm sc7280 developement board
You are correct, for this first patch, only build-tested is valid. […]
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/96820cae_25255a32 PS41, Line 10: qualcomm sc7280 developement board
herobrine is the Google designation for this board, which has not been spun yet. […]
Done
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/5040b278_405200c6 PS41, Line 30: 84K
We are expecting to add a 1K watchdog tombstone region here, which will come later, so for time bein […]
Done
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Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 42: Code-Review+2
(1 comment)
File src/soc/qualcomm/sc7280/include/soc/addressmap.h:
https://review.coreboot.org/c/coreboot/+/45205/comment/5f0a1568_55b6d361 PS42, Line 6: #include <stdint.h> Nit: Let's remove this until we need it later. It'll make the later code review cleaner.
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Ravi Kumar Bokka, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Martin Roth, Patrick Georgi, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45205
to look at the new patch set (#43).
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 12 files changed, 249 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/43
Attention is currently required from: Martin Roth, Paul Menzel, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 42:
(1 comment)
File src/soc/qualcomm/sc7280/include/soc/addressmap.h:
https://review.coreboot.org/c/coreboot/+/45205/comment/573241a9_86dcaaa0 PS42, Line 6: #include <stdint.h>
Nit: Let's remove this until we need it later. It'll make the later code review cleaner.
Done
Attention is currently required from: Ravi kumar, Martin Roth, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 43: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Shelley Chen shchen@google.com --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 12 files changed, 249 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved
diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index 5cd7981..d177c0e 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -5,3 +5,4 @@ ## Platforms
- [SC7180 series](sc7180/index.md) +- [SC7280 series](sc7280/index.md) diff --git a/Documentation/soc/qualcomm/sc7280/index.md b/Documentation/soc/qualcomm/sc7280/index.md new file mode 100644 index 0000000..4920805 --- /dev/null +++ b/Documentation/soc/qualcomm/sc7280/index.md @@ -0,0 +1,17 @@ +# Qualcomm SC7280 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig new file mode 100644 index 0000000..1bba460 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -0,0 +1,29 @@ +config SOC_QUALCOMM_SC7280 + bool + default n + depends on USE_QC_BLOBS + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select CACHE_MRC_SETTINGS + select HAS_RECOVERY_MRC_CACHE + +if SOC_QUALCOMM_SC7280 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7280/memlayout.ld" + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000..15bc039 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,38 @@ +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +all-y += ../common/timer.c +all-y += spi.c + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +SC7280_BLOB := $(top)/3rdparty/qc_blobs/sc7180 + +################################################################################ + +QC_SEC_FILE := $(SC7280_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c new file mode 100644 index 0000000..807bb25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7280_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c new file mode 100644 index 0000000..4b9eb37 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h new file mode 100644 index 0000000..82a0c39 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_GPIO_H_ +#define _SOC_QUALCOMM_SC7280_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + +#endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/mmu.h b/src/soc/qualcomm/sc7280/include/soc/mmu.h new file mode 100644 index 0000000..5a2984f --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_MMU_H_ +#define _SOC_QUALCOMM_SC7280_MMU_H_ + +void sc7280_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7280_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld new file mode 100644 index 0000000..24b79f9 --- /dev/null +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */ +#define SSRAM_START(addr) REGION_START(ssram, addr) +#define SSRAM_END(addr) REGION_END(ssram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) REGION_START(bsram, addr) +#define BSRAM_END(addr) REGION_END(bsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) REGION_START(aopsram, addr) +#define AOPSRAM_END(addr) REGION_END(aopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AB000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14819000, 40K) + PRERAM_CBFS_CACHE(0x14823000, 70K) + PRERAM_CBMEM_CONSOLE(0x14834800, 32K) + TIMESTAMP(0x1483C800, 1K) + TTB(0x1483D000, 56K) + STACK(0x1484B000, 16K) + VBOOT2_WORK(0x1484F000, 12K) + DMA_COHERENT(0x14853000, 8K) + REGION(ddr_training, 0x14855000, 8K, 4K) + REGION(qclib_serial_log, 0x14857000, 4K, 4K) + REGION(ddr_information, 0x1485B000, 1K, 1K) + FMAP_CACHE(0x1485B400, 2K) + CBFS_MCACHE(0x1485BC00,8K) + REGION(dcb, 0x14875000, 32K, 4K) + REGION(pmic, 0x1487D000, 96K, 4K) + REGION(qclib, 0x14895000, 748K, 4K) + BSRAM_END(0x14950000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c new file mode 100644 index 0000000..9a28578 --- /dev/null +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols_common.h> + +void sc7280_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c new file mode 100644 index 0000000..33d4a69 --- /dev/null +++ b/src/soc/qualcomm/sc7280/soc.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols_common.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7280_ops = { + CHIP_NAME("SOC Qualcomm SC7280") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c new file mode 100644 index 0000000..50aa395 --- /dev/null +++ b/src/soc/qualcomm/sc7280/spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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