Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45206 )
Change subject: herobrine : Provide initial mainboard support ......................................................................
herobrine : Provide initial mainboard support
Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka rbokka@codeaurora.org --- M payloads/libpayload/Kconfig A payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/sc7280.c A src/mainboard/google/herobrine/Kconfig A src/mainboard/google/herobrine/Kconfig.name A src/mainboard/google/herobrine/Makefile.inc A src/mainboard/google/herobrine/board.h A src/mainboard/google/herobrine/board_info.txt A src/mainboard/google/herobrine/boardid.c A src/mainboard/google/herobrine/bootblock.c A src/mainboard/google/herobrine/chromeos.c A src/mainboard/google/herobrine/chromeos.fmd A src/mainboard/google/herobrine/devicetree.cb A src/mainboard/google/herobrine/mainboard.c A src/mainboard/google/herobrine/reset.c A src/mainboard/google/herobrine/romstage.c 17 files changed, 319 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45206/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index b5dc9a3..43ba6ab 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -256,6 +256,11 @@ depends on SERIAL_CONSOLE default n
+config SC7280_SERIAL_CONSOLE + bool "SC7280 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config QUALCOMM_QUPV3_SERIAL_CONSOLE bool "Qualcomm QUPV3 serial port driver" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine new file mode 100644 index 0000000..a9d576a --- /dev/null +++ b/payloads/libpayload/configs/config.herobrine @@ -0,0 +1,5 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_SC7280_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index c4f7bf6..6c54c49 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -42,6 +42,8 @@ libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c
+libc-$(CONFIG_LP_SC7280_SERIAL_CONSOLE) += serial/sc7280.c serial/serial.c + libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c
libc-$(CONFIG_LP_MOUSE_CURSOR) += mouse_cursor.c diff --git a/payloads/libpayload/drivers/serial/sc7280.c b/payloads/libpayload/drivers/serial/sc7280.c new file mode 100644 index 0000000..0d7f5cf --- /dev/null +++ b/payloads/libpayload/drivers/serial/sc7280.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <libpayload.h> + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + +} diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig new file mode 100644 index 0000000..92f77db --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig @@ -0,0 +1,55 @@ + +config BOARD_GOOGLE_HEROBRINE_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_HEROBRINE_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7280 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default "google/herobrine" + +config MAINBOARD_VENDOR + string + default "Google" + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Herobrine" if BOARD_GOOGLE_HEROBRINE + +config GBB_HWID + string + depends on CHROMEOS + default "HEROBRINE TEST 1859" if BOARD_GOOGLE_HEROBRINE + +endif # BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name new file mode 100644 index 0000000..13dc56a --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_HEROBRINE + bool "Herobrine" + select BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Makefile.inc b/src/mainboard/google/herobrine/Makefile.inc new file mode 100644 index 0000000..949d775 --- /dev/null +++ b/src/mainboard/google/herobrine/Makefile.inc @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += bootblock.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h new file mode 100644 index 0000000..c69d5d2 --- /dev/null +++ b/src/mainboard/google/herobrine/board.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ + +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +#define GPIO_EC_IN_RW GPIO(118) +#define GPIO_AP_EC_INT GPIO(94) +#define GPIO_AP_SUSPEND GPIO(20) +#define GPIO_WP_STATE GPIO(42) +#define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) +#define GPIO_SD_CD_L GPIO(69) +#define GPIO_AMP_ENABLE GPIO(23) + +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30)) + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/herobrine/board_info.txt b/src/mainboard/google/herobrine/board_info.txt new file mode 100644 index 0000000..a670d6e --- /dev/null +++ b/src/mainboard/google/herobrine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Herobrine Qualcomm sc7280 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c new file mode 100644 index 0000000..7ff648e --- /dev/null +++ b/src/mainboard/google/herobrine/boardid.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(31), [1] = GPIO(93), [0] = GPIO(33)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c new file mode 100644 index 0000000..05e53a6 --- /dev/null +++ b/src/mainboard/google/herobrine/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c new file mode 100644 index 0000000..dba1c09 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include "board.h" + +int get_write_protect_state(void) +{ +#if 0 + return !gpio_get(GPIO_WP_STATE); +#else + return 0; +#endif +} + +void setup_chromeos_gpios(void) +{ +#if 0 + /* Example of what needs to be done here */ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +#if 0 + /* Example of what needs to be done here */ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +#endif +} diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd new file mode 100644 index 0000000..a44a638 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# TODO: update for Herobrine +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x3c4000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x3c0000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 228K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb new file mode 100644 index 0000000..e23782f --- /dev/null +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/sc7280 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c new file mode 100644 index 0000000..31deb77 --- /dev/null +++ b/src/mainboard/google/herobrine/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <arch/mmio.h> +#include <gpio.h> +#include <timestamp.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/herobrine/reset.c b/src/mainboard/google/herobrine/reset.c new file mode 100644 index 0000000..9b5810f --- /dev/null +++ b/src/mainboard/google/herobrine/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c new file mode 100644 index 0000000..8844f18 --- /dev/null +++ b/src/mainboard/google/herobrine/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/qclib_common.h> + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +}
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