Change in coreboot[master]: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset...
Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 44 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/1
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6d88cbc..db0cdbd 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -11,12 +11,28 @@
config SA_PCIEX_LENGTH_MIB hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 0x1000 if (PCIEX_LENGTH_4096MB) + default 0x800 if (PCIEX_LENGTH_2048MB) + default 0x400 if (PCIEX_LENGTH_1024MB) + default 0x200 if (PCIEX_LENGTH_512MB) + default 0x100 if (PCIEX_LENGTH_256MB) + default 0x80 if (PCIEX_LENGTH_128MB) + default 0x40 if (PCIEX_LENGTH_64MB) + default 0x100 help - This option allows you to select length of PCIEX region. + This option allows you to select length of PCIEX region in MiB. + +config PCIEX_LENGTH_4096MB + bool + +config PCIEX_LENGTH_2048MB + bool + +config PCIEX_LENGTH_1024MB + bool + +config PCIEX_LENGTH_512MB + bool
config PCIEX_LENGTH_256MB bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..91595c2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0
+#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 #define PCIEXBAR_LENGTH_256MB 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 79a6628..ff806ac 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -28,13 +28,29 @@
/* Get PCI Express Region Length */ switch (CONFIG_SA_PCIEX_LENGTH_MIB) { - case 256 * MiB: + /* + * Length of PCIEXBAR region would be more than 256MB if + * PCIEXBAR.LENGTH width is 3. + */ + case 4096: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; + break; + case 2048: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 1024: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 512: + pciexbar_length = PCIEXBAR_LENGTH_512MB; + break; + case 256: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: + case 128: pciexbar_length = PCIEXBAR_LENGTH_128MB; break; - case 64 * MiB: + case 64: pciexbar_length = PCIEXBAR_LENGTH_64MB; break; default:
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/Kconfig:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 18: default 0x100 if (PCIEX_LENGTH_256MB) : default 0x80 if (PCIEX_LENGTH_128MB) : default 0x40 if (PCIEX_LENGTH_64MB) : default 0x100 this changes should have gone into CB:40235 itself
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 47: case 256: : pciexbar_length = PCIEXBAR_LENGTH_256MB; : break; : case 128: : pciexbar_length = PCIEXBAR_LENGTH_128MB; : break; : case 64: : pciexbar_length = PCIEXBAR_LENGTH_64MB; : break; this changes should have gone into CB:40235 itself
Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40363
to look at the new patch set (#2).
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 46 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/2
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/Kconfig:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 18: default 0x100 if (PCIEX_LENGTH_256MB) : default 0x80 if (PCIEX_LENGTH_128MB) : default 0x40 if (PCIEX_LENGTH_64MB) : default 0x100
this changes should have gone into CB:40235 itself
Done
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/1/src/soc/intel/common/block/... PS1, Line 47: case 256: : pciexbar_length = PCIEXBAR_LENGTH_256MB; : break; : case 128: : pciexbar_length = PCIEXBAR_LENGTH_128MB; : break; : case 64: : pciexbar_length = PCIEXBAR_LENGTH_64MB; : break;
this changes should have gone into CB:40235 itself
Done
Subrata Banik has uploaded a new patch set (#3) to the change originally created by Usha P. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 37 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/3
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Subrata Banik, Pratikkumar V Prajapati, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40363
to look at the new patch set (#4).
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 41 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/4
Subrata Banik has uploaded a new patch set (#5) to the change originally created by Usha P. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 7: Code-Review+1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 7:
(1 comment)
I don't see how we're correctly reporti
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... PS7, Line 45: break; But only certain chipsets support these length values. Shouldn't we be protecting against a misconfiguration?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... PS7, Line 45: break;
But only certain chipsets support these length values. […]
yes valid point, i had some CL like this https://review.coreboot.org/c/coreboot/+/40337 will restore this.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/... PS7, Line 45: break;
yes valid point, i had some CL like this https://review.coreboot.org/c/coreboot/+/40337 […]
Well, we need something to indicate support in the chipset. Can we have a MMCONF_MAX_SIZE or something like that?
Usha P has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
Abandoned
-
Aaron Durbin (Code Review) -
Pratikkumar V Prajapati (Code Review)
-
Subrata Banik (Code Review)
-
Usha P (Code Review)
-
Wonkyu Kim (Code Review)