coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by 9elements QA (Code Review) 21 Oct '20

21 Oct '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46278 ) Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... Patch Set 15: Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/24008 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/24007 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/24006 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/24005 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/24003 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/24002 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 21 Oct 2020 15:08:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/46274/22/src/cpu/intel/common/comm… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46274/22/src/cpu/intel/common/comm… PS22, Line 317: int > uint32_t have you read the commit message? ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 14:58:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Hello Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46014 to review the following change. Change subject: mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off ...................................................................... mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off The 0x30 register is eventually controlled by coreboot's pnp_enable_resources() based on the on/off setting. Other register settings were grouped with their respective "virtual" LDN, where possible. Note, this temporarily breaks LDN 8 settings, as coreboot will ignore configuration for disabled devices. Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46014/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index c05857f..3f9135c 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -61,8 +61,7 @@ irq 0xf7 = 0x00 irq 0xf8 = 0x00 end - device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - irq 0x30 = 0x00 + device pnp 2e.8 off # WDT1, GPIO0, GPIO1 io 0x60 = 0x00 irq 0xe0 = 0xff irq 0xe1 = 0xff @@ -78,29 +77,42 @@ irq 0xf6 = 0x00 irq 0xf7 = 0xff end - device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - irq 0x30 = 0xfe + device pnp 2e.009 off # GPIO8 + end + device pnp 2e.109 on # GPIO1 + end + device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff irq 0xe1 = 0x90 irq 0xe2 = 0x00 irq 0xe3 = 0x00 + irq 0xe9 = 0x00 + end + device pnp 2e.309 on # GPIO3 irq 0xe4 = 0x7f irq 0xe5 = 0x76 irq 0xe6 = 0x00 irq 0xe7 = 0x00 - irq 0xe8 = 0x00 - irq 0xe9 = 0x00 irq 0xea = 0x00 - irq 0xeb = 0x00 - irq 0xee = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.409 on # GPIO4 + irq 0xe8 = 0x00 irq 0xf0 = 0xff irq 0xf1 = 0x7b irq 0xf2 = 0x00 + irq 0xee = 0x00 + end + device pnp 2e.509 on # GPIO5 + irq 0xeb = 0x00 irq 0xf4 = 0xff irq 0xf5 = 0xef irq 0xf6 = 0x00 irq 0xf7 = 0x00 - irq 0xfe = 0x00 + end + device pnp 2e.609 on # GPIO6 + end + device pnp 2e.709 on # GPIO7 end device pnp 2e.a on # ACPI irq 0xe6 = 0x4c @@ -108,7 +120,6 @@ irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - irq 0x30 = 0x01 io 0x60 = 0x0290 irq 0xe2 = 0x7f irq 0xe4 = 0xf1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8 Gerrit-Change-Number: 46014 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update telemetry settings for morphius
by Kevin Chiu (Code Review) 21 Oct '20

21 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46472 ) Change subject: mb/google/zork: update telemetry settings for morphius ...................................................................... mb/google/zork: update telemetry settings for morphius update telemetry to improve the performance. BUG=b:168265881 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46472/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 43a9439..ecadb07 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -16,9 +16,9 @@ register "sustained_power_limit" = "12000" #mw register "thermctl_limit" = "100" #degrees C - register "telemetry_vddcr_vdd_slope" = "78709" #mA + register "telemetry_vddcr_vdd_slope" = "62852" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29035" #mA + register "telemetry_vddcr_soc_slope" = "28022" #mA register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode -- To view, visit https://review.coreboot.org/c/coreboot/+/46472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018 Gerrit-Change-Number: 46472 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Arthur Heymans (Code Review) 21 Oct '20

21 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 22: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46274/22/src/cpu/intel/common/comm… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46274/22/src/cpu/intel/common/comm… PS22, Line 317: int uint32_t -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 14:27:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware
by Paul Menzel (Code Review) 21 Oct '20

21 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39371 ) Change subject: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware ...................................................................... mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware Here is the relevant output of `superiotool` for the global control registers: Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM The serial console still does not work. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/bootblock.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39371/1 diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index 3d980a6..cbd6e3a 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -15,6 +15,7 @@ */ #include <bootblock_common.h> +#include <device/pnp_ops.h> #include <device/pnp_type.h> #include <amdblocks/acpimmio.h> #include <stdint.h> @@ -47,8 +48,21 @@ static void superio_init_m_pro(void) { + pnp_devfn_t global_dev = PNP_DEV(0x2e, 0); pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); + pnp_write_config(global_dev, 0x13, 0xff); + pnp_write_config(global_dev, 0x14, 0xff); + pnp_write_config(global_dev, 0x1a, 0x0a); + pnp_write_config(global_dev, 0x1b, 0x28); + pnp_write_config(global_dev, 0x1c, 0x00); + pnp_write_config(global_dev, 0x1d, 0x10); + pnp_write_config(global_dev, 0x22, 0xdf); + pnp_write_config(global_dev, 0x2a, 0x48); + pnp_write_config(global_dev, 0x2b, 0x20); + pnp_write_config(global_dev, 0x2c, 0x00); + pnp_write_config(global_dev, 0x2f, 0x01); + nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 21 Oct '20

21 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 13: (3 comments) https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… PS13, Line 271: pmc_clear_tco_status > is there a need for preprocessor directives? I don't think so. https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… File src/soc/intel/xeon_sp/include/soc/nvs.h: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… PS13, Line 14: u8 uior; > you need to sync the ACPI GNVS against this struct I think this change is not needed... https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… PS13, Line 293: uintptr_t tseg_base = pci_s_read_config32(PCI_DEV(0, > use get_tseg_base_lim instead Ok. It's also broken btw... -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 13 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 21 Oct 2020 13:09:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45952 to look at the new patch set (#22). Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... soc/intel/common: add Kconfig to enable/disable the ACPI PM timer Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Also, make the TCO SMI option select ACPI PM timer, since TCO won't work without it. The Kconfig option depends on CTC (Common Timer Copy), which a SoC has to support to do PM ACPI timer emulation. This new Kconfig gets used in the follow-up commits of this series. Note: On Apollolake USE_PM_ACPI_TIMER gets selected statically to avoid confusing the user in menuconfig, where the option is shown due to use of the common code for PM Timer emulation. On APL there is not hardware PM ACPI Timer, so emulation needs to be always enabled. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/smm/Kconfig 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#20). Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... soc/intel: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. TODO: test this patch on APL hardware to prove this assumption ^ Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 13 files changed, 36 insertions(+), 167 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46460 to look at the new patch set (#6). Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... soc/intel: drop unneeded ISST configuration code The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* (de)activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capbability, since one can configure the OS to not enable HWP if that is desired. To reduce complexity and duplicated code without actual benefit, this code, as well as the devicetree option get dropped in this change. This change has one side effect: all boards explicitly disabling or not explicitly enabling ISST now gain ISST support. If the OS is configured to enable HWP if supported, it will do so. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 7 files changed, 0 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46460/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020