coreboot-gerrit October 2020

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > just having one LPIT entry isn't enough; to make linux use both sysfs interfaces, there need to be t […] hmm, maybe I was wrong and we don't even need soc-specific LPIT tables but just set the addresses and MSRs via macros/defines? That way we can avoid ugly call-backs. That's more or less what platform sample code for KBL and TGL does. Tim, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 12:55:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: drop obsolete ISST workaround
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46459 ) Change subject: mb/google/dedede: drop obsolete ISST workaround ...................................................................... mb/google/dedede: drop obsolete ISST workaround Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/waddledee/Makefile.inc D src/mainboard/google/dedede/variants/waddledee/variant.c M src/mainboard/google/dedede/variants/waddledoo/Makefile.inc D src/mainboard/google/dedede/variants/waddledoo/variant.c 6 files changed, 0 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 45b2580..23b1596 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -29,19 +29,6 @@ } } -__weak void variant_isst_override(void) -{ - /* - * Implement the override only if the board uses very early/initial revisions of - * Silicon. Otherwise nothing to override. - */ -} - -static void mainboard_config_isst(void *unused) -{ - variant_isst_override(); -} - static void mainboard_init(void *chip_info) { const struct pad_config *base_pads; @@ -79,6 +66,3 @@ .init = mainboard_init, .enable_dev = mainboard_enable, }; - -/* Configure ISST before CPU initialization */ -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL); diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bd94ef4..dc855c6 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,7 +36,4 @@ */ bool variant_mem_is_half_populated(void); -/* Variant Intel Speed Shift Technology override */ -void variant_isst_override(void); - #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index 93f34f8..e835c69 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -3,4 +3,3 @@ romstage-y += memory.c ramstage-y += gpio.c -ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/variant.c b/src/mainboard/google/dedede/variants/waddledee/variant.c deleted file mode 100644 index ac3cf58..0000000 --- a/src/mainboard/google/dedede/variants/waddledee/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index eda535c..566f5cc 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,5 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later romstage-y += memory.c - -ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/variant.c b/src/mainboard/google/dedede/variants/waddledoo/variant.c deleted file mode 100644 index ac3cf58..0000000 --- a/src/mainboard/google/dedede/variants/waddledoo/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Gerrit-Change-Number: 46459 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46274 to look at the new patch set (#22). Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... {cpu,soc}/intel: deduplicate cpu code Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 15 files changed, 57 insertions(+), 413 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46274/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: rework code previously moved to common cpu code
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46588 ) Change subject: cpu/intel/common: rework code previously moved to common cpu code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/46588/4/src/include/cpu/x86/msr.h File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/46588/4/src/include/cpu/x86/msr.h@… PS4, Line 48: #define CPUID_6_ECX_EPB (1 << 3) > It's not a bit in IA32_ENERGY_PERF_BIOS, is it? `msr.h` is the wrong file […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Gerrit-Change-Number: 46588 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 12:35:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46278 ) Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... {cpu,soc}/intel: replace AES-NI locking by common implemenation call Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/skylake/cpu.c 9 files changed, 12 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index b4a91ea..65b28c0 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -216,11 +216,7 @@ /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); - if (!intel_ht_sibling()) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - } + set_aesni_lock(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d23772a..5af5ff9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -470,11 +470,7 @@ /* Thermal throttle activation offset */ configure_thermal_target(); - if (!intel_ht_sibling()) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - } + set_aesni_lock(); /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 0d11b5e..51b7395 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -6,6 +6,7 @@ */ #define MSR_FEATURE_CONFIG 0x13c +#define AESNI_DISABLE (1 << 1) #define AESNI_LOCK (1 << 0) #endif /* CPU_INTEL_MSR_H */ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 72f983f..0ae170b 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -9,6 +9,7 @@ #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -43,12 +44,6 @@ #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), - /* - * Enable and Lock the Advanced Encryption Standard (AES-NI) - * feature register - */ - REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, - FEATURE_CONFIG_LOCK), REG_SCRIPT_END }; @@ -62,6 +57,9 @@ /* Set core MSRs */ reg_script_run(core_msr_script); + + set_aesni_lock(); + /* * Enable ACPI PM timer emulation, which also lets microcode know * location of ACPI_BASE_ADDRESS. This also enables other features diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9092df1..854da2e 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <console/console.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> #include <arch/cpu.h> #include <intelblocks/cpulib.h> diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 2ef4561..2e12bf0 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -24,9 +24,6 @@ #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_VALUE 0x13 -#define MSR_FEATURE_CONFIG 0x13c -#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL -#define FEATURE_CONFIG_LOCK (1 << 0) #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 798d473..89bbbb0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -34,6 +34,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b1eda9b..7cee5be 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -9,6 +9,7 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/em64t100_save_state.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/common/common.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -59,12 +60,7 @@ msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) { - msr = rdmsr(MSR_FEATURE_CONFIG); - msr.lo |= FEATURE_CONFIG_LOCK; /* Lock AES-NI */ - wrmsr(MSR_FEATURE_CONFIG, msr); - } + set_aesni_lock(); /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5ec0023..e716c66 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -186,25 +186,6 @@ wrmsr(MSR_EMULATE_PM_TIMER, msr); } -/* - * Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling - * as suggested in Intel document 325384-070US. - */ -static void cpu_lock_aesni(void) -{ - msr_t msr; - - /* Only run once per core as specified in the MSR datasheet */ - if (intel_ht_sibling()) - return; - - msr = rdmsr(MSR_FEATURE_CONFIG); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; - wrmsr(MSR_FEATURE_CONFIG, msr); - } -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -227,8 +208,7 @@ /* Configure Intel Speed Shift */ configure_isst(); - /* Lock AES-NI MSR */ - cpu_lock_aesni(); + set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/common: rework code previously moved to common cpu code
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46588 ) Change subject: cpu/intel/common: rework code previously moved to common cpu code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/46588/3/src/include/cpu/x86/msr.h File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/46588/3/src/include/cpu/x86/msr.h@… PS3, Line 24: #define CPUID_EPP (1 << 3) > Should be named after it's location, e.g. CPUID_6_ECX_SOMETHING. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Gerrit-Change-Number: 46588 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 12:34:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#23). Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/block/acpi: add code for CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. This way all SoCs using the common code get the CPPC entries added. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 23 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46465 to look at the new patch set (#12). Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/soc/intel/skylake/acpi.c 2 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46465/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46461 to look at the new patch set (#8). Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... soc/intel/skl: replace conditional on dt option reading CPUID for CPPC Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46461/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor
by Paul Menzel (Code Review) 21 Oct '20

21 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42201 ) Change subject: soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor ...................................................................... soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor This unifies the file with `src/soc/intel/cannonlake/acpi.c`. Change-Id: Ia6601bfd6e7a11eca6bbc32f6757c165ba5a4cff Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42201/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index bdfacd3..5d48184 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,3 +1,4 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> @@ -170,15 +171,20 @@ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG(CHROMEOS) - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif + /* Update the mem console pointer. */ + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/42201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6601bfd6e7a11eca6bbc32f6757c165ba5a4cff Gerrit-Change-Number: 42201 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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