coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree
by Paul Menzel (Code Review) 22 Oct '20

22 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45998 ) Change subject: mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree ...................................................................... mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree The mainboard has a PS/2 port, so enable the keyboard controller in the devicetree. The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux, probably as ACPI code still needs to be added. Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45998/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 2aa2d89..c9de54c 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -37,7 +37,12 @@ irq 0x70 = 4 end device pnp 2e.3 off end # COM2/IR - device pnp 2e.5 off end # Keyboard + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 + irq 0x72 = 12 + end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 io 0xe0 = 0x7f -- To view, visit https://review.coreboot.org/c/coreboot/+/45998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804 Gerrit-Change-Number: 45998 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 ) Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 18:39:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Increase vbt_data size
by Srinidhi N Kaushik (Code Review) 21 Oct '20

21 Oct '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46374 ) Change subject: drivers/intel/gma: Increase vbt_data size ...................................................................... drivers/intel/gma: Increase vbt_data size With TGL FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Due to which cbfsf_decompression_info check failed when trying to load vbt binary from cbfs because vbt decompressed_size was greater than vbt_data size. This caused Graphics Init and fw creen issues. Increase the vbt_data to 9KiB to accommodate new vbt binary. BUG=b:170656067 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e --- M src/drivers/intel/gma/opregion.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46374/1 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 7682af1..8f1d2e6 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -19,7 +19,7 @@ return "vbt.bin"; } -static char vbt_data[8 * KiB]; +static char vbt_data[9 * KiB]; static size_t vbt_data_sz; void *locate_vbt(size_t *vbt_size) -- To view, visit https://review.coreboot.org/c/coreboot/+/46374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e Gerrit-Change-Number: 46374 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46463 ) Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/46463/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46463/6//COMMIT_MSG@14 PS6, Line 14: Test: > Linux doesn't use it, yet, thus I just checked, that the entries are correct in a dumped SSDT Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 18:29:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46463 ) Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 18:28:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: Fix regression
by Patrick Rudolph (Code Review) 21 Oct '20

21 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46634 ) Change subject: cpu/intel/common: Fix regression ...................................................................... cpu/intel/common: Fix regression Fix the logic introduced in CB:46276 "cpu/intel/common: only lock AES-NI when supported" which needs to be negated. Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/common/common_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46634/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 4568014..a54e891 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -273,7 +273,7 @@ if (!CONFIG(SET_MSR_AESNI_LOCK_BIT)) return; - if (cpu_get_feature_flags_ecx() & CPUID_AES) + if (!(cpu_get_feature_flags_ecx() & CPUID_AES)) return; /* Only run once per core as specified in the MSR datasheet */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Gerrit-Change-Number: 46634 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/22/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/22/src/soc/intel/common/bloc… PS22, Line 39: CPU_SUPPORTS_PM_TIMER_EMULATION Will this be used for anything else? Otherwise you could rename/move it to PM_ACPI_TIMER_OPTIONAL and wouldn't have any problem with the APL case. -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 17:49:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Hello Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46013 to review the following change. Change subject: mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers ...................................................................... mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers The `io` statement will prepare a 16-bit write, hence use `irq` for miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge 0x61 writes into 0x60). Note, using `irq` is still just a hack as these are neither I/O nor IRQs, but it's common practice in coreboot. Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 61 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46013/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index c9de54c..c05857f 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,83 +45,81 @@ end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - io 0xe0 = 0x7f - io 0xe1 = 0x10 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0xff - io 0xe5 = 0xff - io 0xe6 = 0xff - io 0xe7 = 0xff - io 0xec = 0x00 - io 0xed = 0xff - io 0xf4 = 0xff - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xf8 = 0x00 + irq 0xe0 = 0x7f + irq 0xe1 = 0x10 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0xff + irq 0xe5 = 0xff + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xec = 0x00 + irq 0xed = 0xff + irq 0xf4 = 0xff + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x00 end device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - io 0x30 = 0x00 - io 0x60 = 0x00 - io 0x61 = 0x00 - io 0xe0 = 0xff - io 0xe1 = 0xff - io 0xe2 = 0xff - io 0xe3 = 0xff - io 0xe4 = 0xff - io 0xf0 = 0xff - io 0xf1 = 0x28 - io 0xf2 = 0x00 - io 0xf3 = 0x00 - io 0xf4 = 0x08 - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0xff + irq 0x30 = 0x00 + io 0x60 = 0x00 + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe4 = 0xff + irq 0xf0 = 0xff + irq 0xf1 = 0x28 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x08 + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0xff end device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - io 0x30 = 0xfe - io 0xe0 = 0xff - io 0xe1 = 0x90 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0x7f - io 0xe5 = 0x76 - io 0xe6 = 0x00 - io 0xe7 = 0x00 - io 0xe8 = 0x00 - io 0xe9 = 0x00 - io 0xea = 0x00 - io 0xeb = 0x00 - io 0xee = 0x00 - io 0xf0 = 0xff - io 0xf1 = 0x7b - io 0xf2 = 0x00 - io 0xf4 = 0xff - io 0xf5 = 0xef - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xfe = 0x00 + irq 0x30 = 0xfe + irq 0xe0 = 0xff + irq 0xe1 = 0x90 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0x7f + irq 0xe5 = 0x76 + irq 0xe6 = 0x00 + irq 0xe7 = 0x00 + irq 0xe8 = 0x00 + irq 0xe9 = 0x00 + irq 0xea = 0x00 + irq 0xeb = 0x00 + irq 0xee = 0x00 + irq 0xf0 = 0xff + irq 0xf1 = 0x7b + irq 0xf2 = 0x00 + irq 0xf4 = 0xff + irq 0xf5 = 0xef + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xfe = 0x00 end device pnp 2e.a on # ACPI - io 0xe6 = 0x4c - io 0xe7 = 0x11 - io 0xf2 = 0x5d + irq 0xe6 = 0x4c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x30 = 0x01 - io 0x60 = 0x02 - io 0x61 = 0x90 - io 0xe2 = 0x7f - io 0xe4 = 0xf1 + irq 0x30 = 0x01 + io 0x60 = 0x0290 + irq 0xe2 = 0x7f + irq 0xe4 = 0xf1 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f off # GPIO Push-pull/Open-drain selection - io 0xe6 = 7f + irq 0xe6 = 7f end device pnp 2e.14 off # PORT80 UART - io 0xe0 = 0x00 + irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep end -- To view, visit https://review.coreboot.org/c/coreboot/+/46013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f Gerrit-Change-Number: 46013 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 17:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: rework code previously moved to common cpu code
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46588 ) Change subject: cpu/intel/common: rework code previously moved to common cpu code ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46588/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46588/6//COMMIT_MSG@9 PS6, Line 9: CB:46274 Could be replaced with commit hash after merge of the other. -- To view, visit https://review.coreboot.org/c/coreboot/+/46588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Gerrit-Change-Number: 46588 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 17:24:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020