coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46461 to look at the new patch set (#10). Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... soc/intel/skl: replace conditional on dt option reading CPUID for CPPC Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46461/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@16 PS6, Line 16: OS to not enable HWP if that is desired. > Please also mention the other bits that were set by the dropped […] I confirmed this on CML-U (Clevo L141CU), KBL-H (Smc X11SSM-F) and SKL-U (Acer ES1-572) by printing the MSR in bootblock. In all three cases MSR 0x1aah is 0x1cc0 Cold boot from fresh flash without AC attached ofc. where in all cases the bits were set after a cold boot (fresh flash without AC attached) https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@19 PS6, Line 19: , as well as the devicetree option > I don't see that. Done https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@21 PS6, Line 21: explicitly disabling > Are there any? neither the one or the other. I checked this but forgot to remove that paragraph -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 22:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46460 to look at the new patch set (#7). Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... soc/intel: drop unneeded ISST configuration code The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 7 files changed, 0 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46460/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Tim Wawrzynczak (Code Review) 22 Oct '20

22 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > hmm, maybe I was wrong and we don't even need soc-specific LPIT tables but just set the addresses an […] Yeah, for constant information like this, I think I'd rather just use #defines, but I like the tables idea -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 22:42:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: acpigen: Make acpigen_write_opregion() argument const
by Duncan Laurie (Code Review) 22 Oct '20

22 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46258 ) Change subject: acpigen: Make acpigen_write_opregion() argument const ...................................................................... acpigen: Make acpigen_write_opregion() argument const This structure is not modified so it can be made const and allow the calling function to also declare it as a const structure. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46258/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index e2fe2cf..7b72584 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -408,7 +408,7 @@ * len is region length. * OperationRegion(regionname, regionspace, regionoffset, regionlength) */ -void acpigen_write_opregion(struct opregion *opreg) +void acpigen_write_opregion(const struct opregion *opreg) { /* OpregionOp */ acpigen_emit_ext_op(OPREGION_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index e0d95cd..d06d20c 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -429,7 +429,7 @@ * This function takes input region name, region space, region offset & region * length. */ -void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_opregion(const struct opregion *opreg); /* * Generate ACPI AML code for Mutex * This function takes mutex name and initial value. -- To view, visit https://review.coreboot.org/c/coreboot/+/46258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269 Gerrit-Change-Number: 46258 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpigen: Make gpio set/get arguments const
by Duncan Laurie (Code Review) 22 Oct '20

22 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46257 ) Change subject: acpigen: Make gpio set/get arguments const ...................................................................... acpigen: Make gpio set/get arguments const The 'struct acpi_gpio' arguments passed to acpigen functions are not modified so they can be made const, which allows drivers to also use a const pointer. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46257/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 0ed3708..e2fe2cf 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1865,7 +1865,7 @@ * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); @@ -1873,7 +1873,7 @@ return acpigen_soc_set_tx_gpio(gpio->pins[0]); } -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_set_tx_gpio(gpio->pins[0]); @@ -1881,7 +1881,7 @@ return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } -void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_read_rx_gpio(gpio->pins[0]); @@ -1889,7 +1889,7 @@ acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } -void acpigen_get_tx_gpio(struct acpi_gpio *gpio) +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_get_tx_gpio(gpio->pins[0]); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index cb9e9c9..e0d95cd 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -499,8 +499,8 @@ * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio); +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a RX GPIO value based on the GPIO polarity. @@ -508,7 +508,7 @@ * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_rx_gpio(struct acpi_gpio *gpio); +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a TX GPIO value based on the GPIO polarity. @@ -516,7 +516,7 @@ * This function ends up calling acpigen_soc_get_tx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_tx_gpio(struct acpi_gpio *gpio); +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio); /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, -- To view, visit https://review.coreboot.org/c/coreboot/+/46257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db Gerrit-Change-Number: 46257 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpigen: Add ShiftLeft function helper
by Duncan Laurie (Code Review) 22 Oct '20

22 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46256 ) Change subject: acpigen: Add ShiftLeft function helper ...................................................................... acpigen: Add ShiftLeft function helper Provide a helper function for the ACPI shift left operator that uses the same operator for the source and result. ShiftLeft (OP, count, OP) Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46256/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index ee7c90c..0ed3708 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1381,6 +1381,14 @@ acpigen_write_len_f(); } +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count) +{ + acpigen_emit_byte(SHIFT_LEFT_OP); + acpigen_emit_byte(src_result); + acpigen_write_integer(count); + acpigen_emit_byte(ZERO_OP); +} + void acpigen_write_to_buffer(uint8_t src, uint8_t dst) { acpigen_emit_byte(TO_BUFFER_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index e443267..cb9e9c9 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -378,6 +378,7 @@ void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); void acpigen_write_to_integer(uint8_t src, uint8_t dst); void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op); -- To view, visit https://review.coreboot.org/c/coreboot/+/46256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a Gerrit-Change-Number: 46256 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpigen: Add helpers for common Store operations
by Duncan Laurie (Code Review) 22 Oct '20

22 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46255 ) Change subject: acpigen: Add helpers for common Store operations ...................................................................... acpigen: Add helpers for common Store operations Add helpers for some store operations: Store(INTEGER, NAME) ex: Store (100, SAVE) Store(INTEGER, OP) ex: Store (100, Local0) Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46255/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index a3beb10..ee7c90c 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1243,6 +1243,22 @@ acpigen_emit_namestring(dst); } +/* Store (src, "namestr") */ +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_namestring(dst); +} + +/* Store (src, dst) */ +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(dst); +} + /* Or (arg1, arg2, res) */ void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) { diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 10e328b..e443267 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -361,6 +361,8 @@ const char * const dev_states[], size_t dev_states_count); void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst); +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); -- To view, visit https://review.coreboot.org/c/coreboot/+/46255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946 Gerrit-Change-Number: 46255 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpigen: Add option for reserved bits in Field
by Duncan Laurie (Code Review) 22 Oct '20

22 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46254 ) Change subject: acpigen: Add option for reserved bits in Field ...................................................................... acpigen: Add option for reserved bits in Field Add an option for unused/reserved bits in a Field definition, allowing for declarations that do not start at bit 0: Field (UART, AnyAcc, NoLock, Preserve) { , 7, /* RESERVED */ BITF, /* Used bit */ } These just use byte 0 instead of a name. Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46254/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 5b45ebd..a3beb10 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -505,6 +505,12 @@ acpigen_write_field_length(size); } +static void acpigen_write_field_reserved(uint32_t size) +{ + acpigen_emit_byte(0); + acpigen_write_field_length(size); +} + /* * Generate ACPI AML code for Field * Arg0: region name @@ -515,6 +521,7 @@ * struct fieldlist l[] = { * FIELDLIST_OFFSET(0x84), * FIELDLIST_NAMESTR("PMCS", 2), + * FIELDLIST_RESERVED(6), * }; * acpigen_write_field("UART", l, ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK | * FIELD_PRESERVE); @@ -522,7 +529,8 @@ * Field (UART, AnyAcc, NoLock, Preserve) * { * Offset (0x84), - * PMCS, 2 + * PMCS, 2, + * , 6, * } */ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, @@ -546,6 +554,10 @@ acpigen_write_field_name(l[i].name, l[i].bits); current_bit_pos += l[i].bits; break; + case RESERVED: + acpigen_write_field_reserved(l[i].bits); + current_bit_pos += l[i].bits; + break; case OFFSET: acpigen_write_field_offset(l[i].bits, current_bit_pos); current_bit_pos = l[i].bits; diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index c30f844..10e328b 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -158,6 +158,10 @@ .name = X, \ .bits = Y, \ } +#define FIELDLIST_RESERVED(X) { .type = RESERVED, \ + .name = "", \ + .bits = X, \ + } #define FIELD_ANYACC 0 #define FIELD_BYTEACC 1 @@ -174,6 +178,7 @@ enum field_type { OFFSET, NAME_STRING, + RESERVED, FIELD_TYPE_MAX, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46 Gerrit-Change-Number: 46254 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: hw-gfx-gma: Use Broxton panel registers for CFL+
by Nico Huber (Code Review) 22 Oct '20

22 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/46625 ) Change subject: hw-gfx-gma: Use Broxton panel registers for CFL+ ...................................................................... Patch Set 4: (1 comment) We just learned that Coffee Lake can be paired with a 200 series PCH. In this case, the current code would match, but this change would break it. So this asks for a more comprehensive solution. I'm afraid, we'll have to add `PCH` type. Or maybe let's call it `Chipset`? That would better apply to all generations (also G45, and the small core SoCs). We could have the chipset in Kconfig and derive the generation from that internally. https://review.coreboot.org/c/libgfxinit/+/46625/4/common/hw-gfx-gma.ads File common/hw-gfx-gma.ads: https://review.coreboot.org/c/libgfxinit/+/46625/4/common/hw-gfx-gma.ads@49 PS4, Line 49: Coffeelake); Technically, the CPU works exactly the same as Kaby Lake. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Gerrit-Change-Number: 46625 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 21 Oct 2020 22:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020