coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/c/coreboot/+/46460/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46460/4//COMMIT_MSG@10 PS4, Line 10: (de) Just `activate` would be more accurate as the system is always supposed to start with HWP disabled. https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@16 PS6, Line 16: OS to not enable HWP if that is desired. Please also mention the other bits that were set by the dropped code. AFAIR, you confirmed that they are set by default on one unit. We should test that on some more (as datasheets pretend they are 0 by default). Make sure to always test a cold boot, the bits may be sticky. https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@19 PS6, Line 19: , as well as the devicetree option I don't see that. https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@21 PS6, Line 21: explicitly disabling Are there any? -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 17:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: update USB 2.0 controller Lane Parameter for morphius
by Kevin Chiu (Code Review) 21 Oct '20

21 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46537 ) Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for morphius ...................................................................... mb/google/zork: update USB 2.0 controller Lane Parameter for morphius Enhance USB 2.0 HS DC Voltage Level BUG=b:162614573 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46537/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ecadb07..62b08fb 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -35,6 +35,19 @@ .ports.xhci0_port2 = 1, /* Left USB3A port 2 */ }" + #USB 2.0 strength + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/46537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 Gerrit-Change-Number: 46537 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: hw-gfx-gma: Use Broxton panel registers for CFL+
by Angel Pons (Code Review) 21 Oct '20

21 Oct '20

Hello Nico Huber, Matt DeVillier, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/46625 to look at the new patch set (#4). Change subject: hw-gfx-gma: Use Broxton panel registers for CFL+ ...................................................................... hw-gfx-gma: Use Broxton panel registers for CFL+ Looks like the panel controls for Broxton made their way into the big cores, beginning with Coffee Lake. Account for it with a new CPU type. Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads 2 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/25/46625/4 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Gerrit-Change-Number: 46625 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in libgfxinit[master]: hw-gfx-gma: Use Broxton panel power for CFL+
by Angel Pons (Code Review) 21 Oct '20

21 Oct '20

Hello Nico Huber, Matt DeVillier, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/46625 to look at the new patch set (#3). Change subject: hw-gfx-gma: Use Broxton panel power for CFL+ ...................................................................... hw-gfx-gma: Use Broxton panel power for CFL+ Looks like the panel controls for Broxton made their way into the big cores, beginning with Coffee Lake. Account for it with a new CPU type. Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads 2 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/25/46625/3 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Gerrit-Change-Number: 46625 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h
by Jason Glenesk (Code Review) 21 Oct '20

21 Oct '20

Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46334 ) Change subject: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h ...................................................................... Patch Set 4: Please help to review this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/46334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Gerrit-Change-Number: 46334 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 15:49:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: drop obsolete ISST workaround
by 9elements QA (Code Review) 21 Oct '20

21 Oct '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46459 ) Change subject: mb/google/dedede: drop obsolete ISST workaround ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/24016 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/24015 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/24014 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/24013 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/24011 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/24010 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/46459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Gerrit-Change-Number: 46459 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 21 Oct 2020 15:46:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Fix/cleanup USB4 PCIe virtual/generic driver
by Duncan Laurie (Code Review) 21 Oct '20

21 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46544 ) Change subject: soc/intel/common: Fix/cleanup USB4 PCIe virtual/generic driver ...................................................................... soc/intel/common: Fix/cleanup USB4 PCIe virtual/generic driver This driver is for the root port device and needs to reference the parent device for its ACPI scope. Similarly for the debug output it needs to use the parent device, and fall back to the chip name if config->desc is not provided in the devicetree. The UID property is removed. This value is not the same as the port number; according to some docs it should be unique but it is not fully clear what it should be tied to. Regardless, it is not used by the Thunderbolt driver in the kernel. I also renamed some functions/structures to be clear that this is just an ACPI driver for the PCIe root port and not a driver for the root port itself. As part of this I removed the PCI based resource operations and the scan bus function since this device does not have children itself. Finally I added a detaled comment with an example describing what the driver is for and what properties it generates. TEST=boot on volteer and ensure the USB4 root port device and properties are added to the SSDT as described by the comment in chip.h. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18 --- M src/soc/intel/common/block/usb4/chip.h M src/soc/intel/common/block/usb4/pcie.c 2 files changed, 67 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46544/1 diff --git a/src/soc/intel/common/block/usb4/chip.h b/src/soc/intel/common/block/usb4/chip.h index f2eee4d..41f4ed6 100644 --- a/src/soc/intel/common/block/usb4/chip.h +++ b/src/soc/intel/common/block/usb4/chip.h @@ -3,10 +3,62 @@ #ifndef __DRIVERS_INTEL_USB4_PCIE_H__ #define __DRIVERS_INTEL_USB4_PCIE_H__ +/* + * This virtual generic driver provides the ACPI properties for an + * Intel USB4/TBT PCIe Root Port which is already declared in the DSDT, + * + * The associated USB4 port number is obtained from the generic ID and + * the related host interface (DMA) device is provided by the devicetree. + * + * The "ExternalFacingPort", and "HotPlugSupportInD3" properties are defined at + * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… + * + * Example: PCIe Root Port 2 via USB4 host interface 1 port 0: + * + * device pci 0d.3 alias tbt_dma1 on end # \_SB.PCI0.TDM1 + * device pci 07.2 alias tbt_pcie_rp2 on # \_SB.PCI0.TRP2 + * chip soc/intel/common/block/usb4 + * use tbt_dma1 as usb4_port # USB4 host interface for this root port + * device generic 0 on end # USB4 port number on this host interface + * end + * end + * + * The host interface and PCIe Root Port are declared in the DSDT: + * + * Scope (\_SB.PCI0) { + * Device (TDM1) { + * Name (_ADR, 0x000d0003) + * } + * Device (TRP2) { + * Name (_ADR, 0x00070002) + * } + * } + * + * This driver will provide the following properties in the SSDT: + * + * Scope (\_SB.PCI0.TRP2) { + * Name (_DSD, Package () { + * ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + * Package () { + * Package () { "usb4-host-interface", \_SB.PCI0.TDM1 }, + * Package () { "usb4-port-number", 0 }, + * }, + * ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), + * Package () { + * Package () { "HotPlugSupportInD3", 1 }, + * }, + * ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), + * Package () { + * Package () { "ExternalFacingPort", 1 }, + * }, + * } + * } + */ + struct soc_intel_common_block_usb4_config { const char *desc; - /* Pointer to USB4 device that this PCIe root port is routed to. */ + /* USB4 host interface (DMA device) that this PCIe root port is routed to. */ DEVTREE_CONST struct device *usb4_port; }; diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index e37d5f4..eae9027 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -4,19 +4,14 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdlib.h> #include <string.h> -#include <types.h> #include "chip.h" #define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" #define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" #if CONFIG(HAVE_ACPI_TABLES) -static void usb4_pcie_fill_ssdt(const struct device *dev) +static void usb4_pcie_acpi_fill_ssdt(const struct device *dev) { const struct soc_intel_common_block_usb4_config *config; const struct device *parent; @@ -43,14 +38,15 @@ /* Get ACPI path to USB4 device. */ usb4_path = acpi_device_path(config->usb4_port); if (!usb4_path) { - printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port\n", __func__); + printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port %s\n", + __func__, dev_path(config->usb4_port)); return; } usb4_path = strdup(usb4_path); port_id = dev->path.generic.id; - acpigen_write_scope(acpi_device_path(dev)); + acpigen_write_scope(acpi_device_path(parent)); /* Add pointer to USB4 port controller. */ dsd = acpi_dp_new_table("_DSD"); @@ -65,33 +61,31 @@ /* Indicate that port is external. */ pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); - acpi_dp_add_integer(pkg, "UID", port_id); acpi_dp_add_package(dsd, pkg); acpi_dp_write(dsd); acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(parent), + config->desc ? : dev->chip_ops->name, dev_path(parent)); } #endif -static struct device_operations usb4_dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, +static struct device_operations usb4_pcie_acpi_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = usb4_pcie_fill_ssdt, + .acpi_fill_ssdt = usb4_pcie_acpi_fill_ssdt, #endif }; -static void pcie_enable(struct device *dev) +static void usb4_pcie_acpi_enable(struct device *dev) { - dev->ops = &usb4_dev_ops; + dev->ops = &usb4_pcie_acpi_dev_ops; } struct chip_operations soc_intel_common_block_usb4_ops = { - CHIP_NAME("Intel USB4 Root Port") - .enable_dev = pcie_enable + CHIP_NAME("Intel USB4 PCIe Root Port") + .enable_dev = usb4_pcie_acpi_enable }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18 Gerrit-Change-Number: 46544 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Fix ACPI device name for USB4 DMA device
by Duncan Laurie (Code Review) 21 Oct '20

21 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46543 ) Change subject: soc/intel/common: Fix ACPI device name for USB4 DMA device ...................................................................... soc/intel/common: Fix ACPI device name for USB4 DMA device The USB4 host interface (DMA) devices need to use SA_DEVFN_* instead of SA_DEV_* when determining the ACPI name. The matching names are removed from the SOC-level ACPI name handler since they are provided by this driver now. TEST=boot on volteer and ensure TDM0 device is in the SSDT. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: If778bda82b80593452a590962dbffef6eff6484a --- M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/tigerlake/chip.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/46543/1 diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index 7c545f6..df2dfdd 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -15,9 +15,9 @@ static const char *tbt_dma_acpi_name(const struct device *dev) { switch (dev->path.pci.devfn) { - case SA_DEV_TCSS_DMA0: + case SA_DEVFN_TCSS_DMA0: return "TDM0"; - case SA_DEV_TCSS_DMA1: + case SA_DEVFN_TCSS_DMA1: return "TDM1"; default: return NULL; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 98ed55c..46c043f 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -68,8 +68,6 @@ case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; - case SA_DEVFN_TCSS_DMA0: return "TDM0"; - case SA_DEVFN_TCSS_DMA1: return "TDM1"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; case SA_DEVFN_TBT2: return "TRP2"; -- To view, visit https://review.coreboot.org/c/coreboot/+/46543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If778bda82b80593452a590962dbffef6eff6484a Gerrit-Change-Number: 46543 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Allow virtual/generic devices under PCI in devicetree
by Duncan Laurie (Code Review) 21 Oct '20

21 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46542 ) Change subject: device: Allow virtual/generic devices under PCI in devicetree ...................................................................... device: Allow virtual/generic devices under PCI in devicetree This change allows a generic device to be described in the devicetree under a PCI device, such as a root port. Previously any device under a PCI device was expected to also be a PCI device and that does not allow for a virtual/generic device to be present, for example to provide ACPI properties for a root port. The changes are: - Ignore non-PCI devices found under a PCI device when scanning and do not print an error for each devfn scanned. - Don't treat non-PCI devices as leftover and remove them, instead enable them as a static device. - Don't attempt to configure a static device in the tree that is not a PCIe device type. With these changes it is now possible to have a generic device under a PCI device, for example in a USB4/TBT root port (PCIe hotplug device) this generic device will add ACPI properties for the PCIe tunnel routed to the external port: device pci 07.0 on chip soc/intel/common/block/pcie device generic 0 on end end end TEST=boot on volteer with the USB4 root port devices in chipset.cb and ensure they are enabled properly and there are no errors printed in the coreboot log, and that the device properties are created in the SSDT. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95 --- M src/device/pci_device.c M src/device/pciexp_device.c 2 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46542/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ce3e509..691ad6b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1006,16 +1006,11 @@ prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { - if (dev->path.type == DEVICE_PATH_PCI) { - if (dev->path.pci.devfn == devfn) { - /* Unlink from the list. */ - *prev = dev->sibling; - dev->sibling = NULL; - break; - } - } else { - printk(BIOS_ERR, "child %s not a PCI device\n", - dev_path(dev)); + if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == devfn) { + /* Unlink from the list. */ + *prev = dev->sibling; + dev->sibling = NULL; + break; } prev = &dev->sibling; } @@ -1283,6 +1278,16 @@ prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { + + /* + * If static device is not PCI then enable it here and don't + * treat it as a leftover device. + */ + if (dev->path.type != DEVICE_PATH_PCI) { + enable_static_device(dev); + continue; + } + /* * The device is only considered leftover if it is not hidden * and it has a Vendor ID of 0 (the default for a device that diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865..4b723ac 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -180,6 +180,8 @@ for (bus = dev->link_list ; bus ; bus = bus->next) { for (child = bus->children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI) + continue; pciexp_configure_ltr(child); if (child->ops && child->ops->scan_bus) pciexp_enable_ltr(child); @@ -443,6 +445,9 @@ struct device *root = dev->bus->dev; unsigned int root_cap, cap; + if (dev->path.type != DEVICE_PATH_PCI) + return; + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (!cap) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/46542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95 Gerrit-Change-Number: 46542 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Export enable_static_device() function
by Duncan Laurie (Code Review) 21 Oct '20

21 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46541 ) Change subject: device: Export enable_static_device() function ...................................................................... device: Export enable_static_device() function The work done by enable_static_devices() and scan_generic_bus() is common and can be used by other device handlers to enable a single static device. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266 --- M src/device/root_device.c M src/include/device/device.h 2 files changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46541/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index 640ea50..1f51786 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -7,6 +7,18 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; +void enable_static_device(struct device *dev) +{ + if (dev->chip_ops && dev->chip_ops->enable_dev) + dev->chip_ops->enable_dev(dev); + + if (dev->ops && dev->ops->enable) + dev->ops->enable(dev); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(dev), + dev->enabled ? "enabled" : "disabled"); +} + /** * Enable devices on static buses. * @@ -32,15 +44,7 @@ for (link = bus->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); + enable_static_device(child); } } } @@ -58,18 +62,9 @@ link->secondary = ++bus_max; for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - + enable_static_device(child); printk(BIOS_DEBUG, "bus: %s[%d]->", dev_path(child->bus->dev), child->bus->link_num); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); } } diff --git a/src/include/device/device.h b/src/include/device/device.h index 031091a..3a0795e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -358,6 +358,7 @@ return config_of(pcidev_on_root(0, 0)); } +void enable_static_device(struct device *dev); void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); -- To view, visit https://review.coreboot.org/c/coreboot/+/46541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266 Gerrit-Change-Number: 46541 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020