coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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3474 discussions

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/22//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45952/22//COMMIT_MSG@13 PS22, Line 13: Also, make the TCO SMI option select ACPI PM timer, since TCO won't work : without it. this turns out to be wrong. I assumed that TCO depends on the hardware PM timer because I wasn't able to trigger a TCO SMI (tested by triggering the intruder). However, I did more tests today and finally found the reason why that SMI wasn't triggered: there's a bug in Linux leading to a soft-lockup when a TCO SMI gets triggered. It works fine before Linux starts. I'll drop that dependeny and adapt the help texts... -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 23:28:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in libgfxinit[master]: hw-gfx-gma: Use Broxton panel registers for CFL+
by Angel Pons (Code Review) 22 Oct '20

22 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/46625 ) Change subject: hw-gfx-gma: Use Broxton panel registers for CFL+ ...................................................................... Patch Set 4: > Patch Set 4: > > (1 comment) > > We just learned that Coffee Lake can be paired with a > 200 series PCH. In this case, the current code would > match, but this change would break it. > > So this asks for a more comprehensive solution. I'm > afraid, we'll have to add `PCH` type. Or maybe let's > call it `Chipset`? That would better apply to all > generations (also G45, and the small core SoCs). We > could have the chipset in Kconfig and derive the > generation from that internally. Agreed. This change would need better handling to account for CFL+UPT. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I389fa4fb81fab22ace2e75334184495134036ecb Gerrit-Change-Number: 46625 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 21 Oct 2020 22:51:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparty/amd_blobs: update submodule pointer
by Felix Held (Code Review) 22 Oct '20

22 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46594 ) Change subject: 3rdparty/amd_blobs: update submodule pointer ...................................................................... 3rdparty/amd_blobs: update submodule pointer This now tracks a recently created upstream repository located at https://github.com/amd/firmware_binaries BUG=b:166107781 Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46594/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index e393a88..8c668ab 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d +Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b -- To view, visit https://review.coreboot.org/c/coreboot/+/46594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16 Gerrit-Change-Number: 46594 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#25). Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/block/acpi: add code for CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. This way all SoCs using the common code get the CPPC entries added. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 25 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/dnv_ns: enable common CPU code and hook up VMX configuration
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, Matt Delco, Nico Huber, David Guckian, Julien Viard de Galbert, Tim Wawrzynczak, Vanessa Eusebio, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46474 to look at the new patch set (#12). Change subject: soc/intel/dnv_ns: enable common CPU code and hook up VMX configuration ...................................................................... soc/intel/dnv_ns: enable common CPU code and hook up VMX configuration Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. This also retrieves the VMX and Feature Control Lock Kconfig and enables them by default, like done for SKL and CNL already. Since FSP does not configure VMX at all, hook up the common code call for enabling VMX. Change-Id: Iab556055fb229a7e3387ddbd4ff1cb461e36f7b2 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/cpu.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46474/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/46474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab556055fb229a7e3387ddbd4ff1cb461e36f7b2 Gerrit-Change-Number: 46474 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46465 to look at the new patch set (#14). Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/soc/intel/skylake/acpi.c 2 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46465/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46464 to look at the new patch set (#16). Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... cpu/intel/common: correct MSR for the Nominal Performance in CPPC The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 2 files changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46464/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 16 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46463 to look at the new patch set (#15). Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... cpu/intel/common: implement the two missing CPPC v2 autonomous registers This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46463/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45826 to look at the new patch set (#19). Change subject: soc/intel/icl: enable common CPU code ...................................................................... soc/intel/icl: enable common CPU code Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/icelake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45826/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Frans Hendriks, Jeremy Soller, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46462 to look at the new patch set (#12). Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 51 files changed, 2 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46462/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020