coreboot-gerrit October 2020

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Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 22 Oct '20

22 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Maulik V Vaghela, Rizwan Qureshi, Stefan Reinauer, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#8). Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... util/ifdtool: Enable CPU read of the ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch provides an command line option "-r" which will enable read access to CSME region when locking. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has uploaded a new patch set (#19) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 13 files changed, 250 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 19 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 18: (3 comments) https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/Kco… File src/soc/intel/xeon_sp/Kconfig: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/Kco… PS16, Line 66: REG_SCRIPT > W-why? the code in soc/intel/xeon_sp/pmc.c used it :-( With SMM this code is actually used so the linker actually complains about undefined reference to reg_script_run_on_dev https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/skx… File src/soc/intel/xeon_sp/skx/cpu.c: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/skx… PS16, Line 215: 1 << 12 > `4 * KiB` would also work and IMHO would be more readable Done https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/smi… File src/soc/intel/xeon_sp/smihandler.c: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/smi… PS16, Line 2: /* This file is part of the coreboot project. */ > This comment should be gone Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 18 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 22 Oct 2020 13:56:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: dedede: Create metaknight variant
by Tim Chen (Code Review) 22 Oct '20

22 Oct '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46568 to review the following change. Change subject: dedede: Create metaknight variant ...................................................................... dedede: Create metaknight variant Create the metaknight variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:169813211 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_METAKNIGHT Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h A src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h A src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc A src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/metaknight/overridetree.cb 8 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46568/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 377702d..a273c9c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -94,6 +94,7 @@ default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE default "Magolor" if BOARD_GOOGLE_MAGOLOR + default "Metaknight" if BOARD_GOOGLE_METAKNIGHT config MAX_CPUS int @@ -123,5 +124,6 @@ default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR + default "metaknight" if BOARD_GOOGLE_METAKNIGHT endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 563a309..689df68 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -63,3 +63,8 @@ select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_METAKNIGHT + bool "-> Metaknight" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt new file mode 100644 index 0000000..59381dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a Gerrit-Change-Number: 46568 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has uploaded a new patch set (#18) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 13 files changed, 251 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 18 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Angel Pons (Code Review) 22 Oct '20

22 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 16: Code-Review+1 (5 comments) https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/Kco… File src/soc/intel/xeon_sp/Kconfig: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/Kco… PS16, Line 66: REG_SCRIPT W-why? https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/skx… File src/soc/intel/xeon_sp/skx/cpu.c: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/skx… PS16, Line 15: Any reason to have a space here? https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/skx… PS16, Line 215: 1 << 12 `4 * KiB` would also work and IMHO would be more readable https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/smi… File src/soc/intel/xeon_sp/smihandler.c: https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/smi… PS16, Line 2: /* This file is part of the coreboot project. */ This comment should be gone https://review.coreboot.org/c/coreboot/+/46231/16/src/soc/intel/xeon_sp/smi… PS16, Line 14: #include <chip.h> Any reason to include so much stuff? -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 16 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 22 Oct 2020 13:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has uploaded a new patch set (#16) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 12 files changed, 259 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 16 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 15: (5 comments) https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… PS13, Line 271: pmc_clear_tco_status > > is there a need for preprocessor directives? […] Done https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx… PS13, Line 176: * TODO: Now that all APs have been relocated as well as the BSP let SMIs > remove TODO Done https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… File src/soc/intel/xeon_sp/include/soc/nvs.h: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… PS13, Line 14: u8 uior; > > you need to sync the ACPI GNVS against this struct […] Removed because unneeded. ACPI is just a mess and the GNVS are not aligned. https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx… File src/soc/intel/xeon_sp/skx/Makefile.inc: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx… PS13, Line 12: subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm > duplicate entry Done https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… PS13, Line 293: uintptr_t tseg_base = pci_s_read_config32(PCI_DEV(0, > > use get_tseg_base_lim instead > > Ok. It's also broken btw... It only exists for skx and get's removed in CB:46094. -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 15 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 22 Oct 2020 13:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has uploaded a new patch set (#15) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 12 files changed, 257 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 15 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 22 Oct '20

22 Oct '20

Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 11 files changed, 254 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 14 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020