coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Jamie Ryu (Code Review) 21 Oct '20

21 Oct '20

Jamie Ryu has uploaded a new patch set (#53) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 8 files changed, 629 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 53 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Patrick Rudolph (Code Review) 21 Oct '20

21 Oct '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 13: (5 comments) https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/bloc… PS13, Line 271: pmc_clear_tco_status is there a need for preprocessor directives? https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx… PS13, Line 176: * TODO: Now that all APs have been relocated as well as the BSP let SMIs remove TODO https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… File src/soc/intel/xeon_sp/include/soc/nvs.h: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/inc… PS13, Line 14: u8 uior; you need to sync the ACPI GNVS against this struct https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx… File src/soc/intel/xeon_sp/skx/Makefile.inc: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx… PS13, Line 12: subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm duplicate entry https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unc… PS13, Line 293: uintptr_t tseg_base = pci_s_read_config32(PCI_DEV(0, use get_tseg_base_lim instead -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 13 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 21 Oct 2020 08:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Wim Vervoorn (Code Review) 21 Oct '20

21 Oct '20

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 07:40:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel,mb/*: get rid of legacy pad macros
by Patrick Georgi (Code Review) 21 Oct '20

21 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46567 ) Change subject: soc/intel,mb/*: get rid of legacy pad macros ...................................................................... soc/intel,mb/*: get rid of legacy pad macros Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/51nb/x210/gpio.h M src/mainboard/asrock/h110m/include/gpio.h M src/mainboard/facebook/monolith/gpio.h M src/mainboard/google/eve/gpio.h M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/endeavour/gpio.c M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h M src/mainboard/google/glados/variants/cave/include/variant/gpio.h M src/mainboard/google/glados/variants/chell/include/variant/gpio.h M src/mainboard/google/glados/variants/glados/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h M src/mainboard/google/poppy/variants/atlas/gpio.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nautilus/gpio.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/rammus/gpio.c M src/mainboard/google/poppy/variants/soraka/gpio.c M src/mainboard/intel/cedarisland_crb/include/gpio.h M src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h M src/mainboard/intel/kunimitsu/gpio.h M src/mainboard/intel/saddlebrook/gpio.h M src/mainboard/kontron/bsl6/gpio.h M src/mainboard/libretrend/lt1000/gpio.h M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/protectli/vault_kbl/gpio.h M src/mainboard/purism/librem_skl/gpio.h M src/mainboard/razer/blade_stealth_kbl/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio_defs.h M src/soc/intel/skylake/Kconfig M src/soc/intel/xeon_sp/Kconfig 40 files changed, 2,179 insertions(+), 2,216 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Frans Hendriks: Looks good to me, but someone else must approve -- To view, visit https://review.coreboot.org/c/coreboot/+/46567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Gerrit-Change-Number: 46567 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn (private) <wim(a)vervoorn.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Patrick Georgi (Code Review) 21 Oct '20

21 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... soc/intel: convert XTAL frequency constant to Kconfig This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/elkhartlake/include/soc/cpu.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/cpu.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/cpu.h 25 files changed, 85 insertions(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dc9e823..1a3f072 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -136,6 +136,9 @@ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index ee8051d..e6a21c1 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -111,15 +111,17 @@ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 3c11183..71c2f47 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -19,7 +19,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c1b5252..69d42bd 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -157,6 +157,9 @@ int default 100 +config CPU_XTAL_HZ + default 19200000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 490820c..38b830a 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -6,9 +6,6 @@ #include <cpu/x86/msr.h> #include <intelblocks/msr.h> -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 - struct device; void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c6d2eec..e0de93e 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -180,15 +180,17 @@ void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dc2be28..24f64b1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -245,6 +245,9 @@ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 216 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ddedb3f..0622034 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -114,19 +114,22 @@ { msr_t msr; + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); } + static void set_energy_perf_bias(u8 policy) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index b356d3a9..3542a2b 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -22,9 +22,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9e95a8a..9023b58 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -99,6 +99,11 @@ it would get enabled. If CPU supports MKTME, this same config option enables MKTME. +config CPU_XTAL_HZ + int + help + Base clock which virtually everything runs on. + config CPU_SUPPORTS_PM_TIMER_EMULATION bool default n diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 40770d0..05077ad 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -133,6 +133,9 @@ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 382bbf7..271d244 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -105,15 +105,17 @@ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h index 6ee34f2..ec3cd3e 100644 --- a/src/soc/intel/elkhartlake/include/soc/cpu.h +++ b/src/soc/intel/elkhartlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 027ed7d..21da528 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -127,6 +127,9 @@ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 2823fd7..e76f61f 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -105,15 +105,17 @@ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index a231333..5dc22de 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ba7e621..d5adc60 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -137,6 +137,9 @@ int default 133 +config CPU_XTAL_HZ + default 38400000 + config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 3a50929..1944e5c 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -105,15 +105,17 @@ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index c61f2ee..40cebd4 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 14d4fa1..55e74cd 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -241,6 +241,9 @@ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f1b40f6..5ec0023 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -169,15 +169,17 @@ */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 740b3d3..473068c 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -25,9 +25,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0021da5..2b5f0ba 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -138,6 +138,9 @@ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index be056fb..1a5165d 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -111,15 +111,17 @@ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 47a41eb..2d6336a 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -21,7 +21,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig for PM Timer emulation support
by Patrick Georgi (Code Review) 21 Oct '20

21 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46017 ) Change subject: soc/intel/common: add Kconfig for PM Timer emulation support ...................................................................... soc/intel/common: add Kconfig for PM Timer emulation support Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 9 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b8a2a13..dc9e823 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -13,6 +13,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index da57931..c1b5252 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ # CPU specific options select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select IOAPIC select PCR_COMMON_IOSF_1_0 select SSE2 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9bd9f43..dc2be28 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -79,6 +79,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 995a956..9e95a8a 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -98,3 +98,11 @@ /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, it would get enabled. If CPU supports MKTME, this same config option enables MKTME. + +config CPU_SUPPORTS_PM_TIMER_EMULATION + bool + default n + help + Select this if the SoC's ucode supports PM ACPI timer emulation (Common + timer Copy), which is required to be able to disable the TCO PM ACPI + timer for power saving. diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7e78805..40770d0 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -13,6 +13,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0343263..027ed7d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -12,6 +12,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8efa361..ba7e621 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -13,6 +13,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select COS_MAPPED_TO_MSB select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4abe29e..14d4fa1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -24,6 +24,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d1689da..0021da5 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -13,6 +13,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB -- To view, visit https://review.coreboot.org/c/coreboot/+/46017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Gerrit-Change-Number: 46017 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/dedede/variants/drawcia: update PL1 max and min power values
by Sumeet R Pawnikar (Code Review) 21 Oct '20

21 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46502 ) Change subject: mb/google/dedede/variants/drawcia: update PL1 max and min power values ...................................................................... mb/google/dedede/variants/drawcia: update PL1 max and min power values Update PL1 max and min power values BUG=None BRANCH=None TEST=build and verify on dralat system Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46502/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 044ff08..ac7a97e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -93,8 +93,8 @@ register "controls.power_limits" = "{ .pl1 = { - .min_power = 4800, - .max_power = 6000, + .min_power = 3800, + .max_power = 5800, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200, -- To view, visit https://review.coreboot.org/c/coreboot/+/46502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Gerrit-Change-Number: 46502 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: HACK: Disable DSI bist pattern
by yongqiang niu (Code Review) 21 Oct '20

21 Oct '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46582 to review the following change. Change subject: HACK: Disable DSI bist pattern ...................................................................... HACK: Disable DSI bist pattern Let's try to output real data BUG=b:155713214 TEST=boot asurada Change-Id: I9eca8b0d7e5cef45f5868f986ce32f3b5c92a9ac --- M src/soc/mediatek/common/dsi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46582/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index ac289c8..6f0d7e6d 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -130,8 +130,8 @@ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) tmp_reg1 = SYNC_PULSE_MODE; } -#if 1 //DSI pattern write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +#if 0 //DSI pattern write32(&dsi0->dsi_bist_pattern, 0xff00); write32(&dsi0->dsi_bist_con, 0x40); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eca8b0d7e5cef45f5868f986ce32f3b5c92a9ac Gerrit-Change-Number: 46582 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/asurada: fix EC_IN_RW polarity
by Hung-Te Lin (Code Review) 21 Oct '20

21 Oct '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46570 ) Change subject: mb/google/asurada: fix EC_IN_RW polarity ...................................................................... mb/google/asurada: fix EC_IN_RW polarity EC_IN_RW should be low active. Please merge this to CB:46386. BUG=None TEST=None Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: If23898ebc6a1a0bcec910873a07b7470f9aa3dd5 --- M src/mainboard/google/asurada/chromeos.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46570/1 diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 18a350b..a57392b 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -20,7 +20,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/46570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If23898ebc6a1a0bcec910873a07b7470f9aa3dd5 Gerrit-Change-Number: 46570 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: allow to override chip-wrapped devices
by Michael Niewöhner (Code Review) 21 Oct '20

21 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46531 ) Change subject: util/sconfig: allow to override chip-wrapped devices ...................................................................... Patch Set 7: Code-Review-1 > Patch Set 7: > > > Patch Set 7: > > > > > Patch Set 7: > > > > > > > Patch Set 7: > > > > > > > > > > I'm not sure if we actually want to allow changing the chip. > > > > > > Alternatively, we could error out and fix the drivers. Some- > > > > > > thing like CB:41745 might help. > > > > > > > > > > Well, when we turn it around (having the driver inside the device instead of wrapping the device) the problem should be gone. This is what CB:41745 does, right? > > > > > > > > It also adds another pointer to a config struct separate from > > > > the chip's one. It wouldn't solve the problem if trees conflict, > > > > but could avoid conflicting trees in some cases. > > > > > > I agree with Nico, this is, as things currently stand, just an error in whoever is writing the devicetrees. Technically, it is wrong to not have both devices wrapped with the same chip driver (sconfig assumes the hierarchy w/r/t devices & chips is the same in that respect) > > > > Just to be sure I get this right, you want to 1) have the devices wrapped by drivers in the chipset dt and 2) wrap them even when just disabling a device in a devtree? > > The PCI devices corresponding to the internal controllers must not be wrapped by any chip drivers. This is how almost all the internal chip devices are organized in coreboot. The only exception is the CNVi device which happened to be wrapped inconsistently. I have some patches that I plan to push this week to fix that. > > If there is a need to wrap a chip driver for the internal devices for any reason (ACPI generation, etc.), then that can be done by adding a virtual/dummy device under the controller device. This device wouldn't have to be modified by the mainboard unless it needs to override some chip config. Thus, the only cases where a mainboard would have to follow the chip wrapping to match the chipset tree is: > 1. For SoC chip > 2. For any virtual device chips that require chip config changes. Thank you very much for your detailed response! Looking forward to your patches :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/46531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Gerrit-Change-Number: 46531 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Oct 2020 00:25:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020