coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: cpu/intel/common: rework code previously moved to common cpu code
by Nico Huber (Code Review) 21 Oct '20

21 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46588 ) Change subject: cpu/intel/common: rework code previously moved to common cpu code ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/46588/3/src/include/cpu/x86/msr.h File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/46588/3/src/include/cpu/x86/msr.h@… PS3, Line 24: #define CPUID_EPP (1 << 3) Should be named after it's location, e.g. CPUID_6_ECX_SOMETHING. Is it really about EPP? And it looks like a completely random location? Even for the entries below... they are bits in cpuid(1).ecx AFAICT. -- To view, visit https://review.coreboot.org/c/coreboot/+/46588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Gerrit-Change-Number: 46588 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Oct 2020 21:45:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 8: > Patch Set 7: > > Just curious: Should the device tree update go together with this CL? If that CL gets delayed for some unknown reason, will this CL break any functionality? Not yet, we haven't fully switched to using the type-c connector class -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Oct 2020 21:36:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: acpi: Skip writing references for disabled devices in Type-C config
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45877 ) Change subject: acpi: Skip writing references for disabled devices in Type-C config ...................................................................... acpi: Skip writing references for disabled devices in Type-C config When emitting ACPI tables for the Type-C connector class, skip writing out a device reference if it is to a disabled device. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf --- M src/acpi/acpigen_usb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45877/1 diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 90a9b77..7448b3b 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -71,7 +71,7 @@ const char *path; char *fresh; - if (!dev) + if (!dev || !dev->enabled) return; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/45877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf Gerrit-Change-Number: 45877 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45747 to look at the new patch set (#8). Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 13 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45747/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()
by Felix Singer (Code Review) 20 Oct '20

20 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46427 ) Change subject: libpayload/storage/ahci: Use pci_dev struct in ahci_initialize() ...................................................................... libpayload/storage/ahci: Use pci_dev struct in ahci_initialize() Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/libpayload/drivers/storage/ahci.c M payloads/libpayload/drivers/storage/storage.c M payloads/libpayload/include/storage/ahci.h 3 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46427/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index e54bfbf..7c67182 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -228,34 +228,33 @@ }; #endif -void ahci_initialize(pcidev_t dev) +void ahci_initialize(struct pci_dev *dev) { int i; - const u16 class = pci_read_config16(dev, 0xa); - if (class != 0x0106) + pcidev_t pcidev = PCI_DEV(dev->bus, dev->dev, dev->func); + + if (dev->device_class != PCI_CLASS_STORAGE_AHCI) return; - const u16 vendor = pci_read_config16(dev, 0x00); - const u16 device = pci_read_config16(dev, 0x02); #if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) - const u32 vendor_device = pci_read_config32(dev, 0x0); + const u32 vendor_device = dev->vendor_id | dev->device_id >> 16; for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) break; if (i == ARRAY_SIZE(working_controllers)) { printf("ahci: Not using untested SATA controller " - "%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev), - PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + "%02x:%02x.%02x (%04x:%04x).\n", dev->bus, + dev->dev, dev->func, dev->vendor_id, dev->device_id); return; } #endif printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n", - PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id); hba_ctrl_t *const ctrl = phys_to_virt( - pci_read_config32(dev, 0x24) & ~0x3ff); + pci_read_config32(pcidev, 0x24) & ~0x3ff); hba_port_t *const ports = ctrl->ports; /* Reset host controller. */ @@ -274,8 +273,8 @@ ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; /* Enable bus mastering. */ - const u16 command = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + const u16 command = pci_read_config16(pcidev, PCI_COMMAND); + pci_write_config16(pcidev, PCI_COMMAND, command | PCI_COMMAND_MASTER); /* Probe for devices. */ for (i = 0; i < 32; ++i) { diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index e720a2d..f2bde77 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -112,11 +112,9 @@ struct pci_dev *dev; for (dev = lib_sysinfo.pacc->devices; dev; dev = dev->next) { - const uint32_t pcidev = PCI_DEV(dev->bus, dev->dev, dev->func); - switch (dev->device_class) { case PCI_CLASS_STORAGE_AHCI: - ahci_initialize(pcidev); + ahci_initialize(dev); break; default: break; diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 2843624..18a0920 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -26,9 +26,11 @@ * SUCH DAMAGE. */ +#include <pci/pci.h> + #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(pcidev_t dev); +void ahci_initialize(struct pci_dev *dev); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Gerrit-Change-Number: 46427 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: libpayload/storage/ahci: Don't rescan PCI bus
by Felix Singer (Code Review) 20 Oct '20

20 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46416 ) Change subject: libpayload/storage/ahci: Don't rescan PCI bus ...................................................................... libpayload/storage/ahci: Don't rescan PCI bus Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M payloads/libpayload/drivers/storage/ahci.c M payloads/libpayload/drivers/storage/storage.c M payloads/libpayload/include/pci/pci.h M payloads/libpayload/include/storage/ahci.h 4 files changed, 18 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46416/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index ff22b19..e54bfbf 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -227,7 +227,8 @@ 0x8086 | 0x5ae3 << 16, /* Apollo Lake */ }; #endif -static void ahci_init_pci(pcidev_t dev) + +void ahci_initialize(pcidev_t dev) { int i; @@ -282,19 +283,3 @@ ahci_port_probe(ctrl, &ports[i], i + 1); } } - -void ahci_initialize(void) -{ - int bus, dev, func; - - for (bus = 0; bus < 256; ++bus) { - for (dev = 0; dev < 32; ++dev) { - const u16 class = - pci_read_config16(PCI_DEV(bus, dev, 0), 0xa); - if (class != 0xffff) { - for (func = 0; func < 8; ++func) - ahci_init_pci(PCI_DEV(bus, dev, func)); - } - } - } -} diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index 24b9024..9412f86 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -27,6 +27,7 @@ */ #include <libpayload.h> +#include <pci/pci.h> #if CONFIG(LP_STORAGE_AHCI) # include <storage/ahci.h> #endif @@ -108,7 +109,19 @@ */ void storage_initialize(void) { + struct pci_dev *dev; + + for (dev = lib_sysinfo.pacc->devices; dev; dev = dev->next) { + const uint32_t pcidev = PCI_DEV(dev->bus, dev->dev, dev->func); + + switch (dev->device_class) { + case PCI_CLASS_STORAGE_AHCI: #if CONFIG(LP_STORAGE_AHCI) - ahci_initialize(); + ahci_initialize(pcidev); #endif + break; + default: + break; + } + } } diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index ea11a05..ad88590 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -66,6 +66,7 @@ #define PCI_ROM_ADDRESS1 0x38 // on bridges #define PCI_ROM_ADDRESS_MASK ~0x7ff +#define PCI_CLASS_STORAGE_AHCI 0x0106 #define PCI_CLASS_MEMORY_OTHER 0x0580 #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 0aa0322..2843624 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -29,6 +29,6 @@ #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(void); +void ahci_initialize(pcidev_t dev); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Gerrit-Change-Number: 46416 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: libpayload: Store pacc pointer in lib_sysinfo
by Felix Singer (Code Review) 20 Oct '20

20 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46348 ) Change subject: libpayload: Store pacc pointer in lib_sysinfo ...................................................................... libpayload: Store pacc pointer in lib_sysinfo Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M payloads/libpayload/arch/x86/sysinfo.c M payloads/libpayload/include/sysinfo.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46348/1 diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c index ffa57bb..e38e641 100644 --- a/payloads/libpayload/arch/x86/sysinfo.c +++ b/payloads/libpayload/arch/x86/sysinfo.c @@ -78,5 +78,10 @@ lib_sysinfo.memrange[1].type = CB_MEM_RAM; } +#if CONFIG(PCI) + lib_sysinfo.pacc = pci_alloc(); + pci_scan_bus(lib_sysinfo.pacc); +#endif + return ret; } diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index fe3d330..26e3287 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -130,6 +130,8 @@ /* Pointer to FMAP cache in CBMEM */ uintptr_t fmap_cache; + + struct pci_access *pacc; }; extern struct sysinfo_t lib_sysinfo; -- To view, visit https://review.coreboot.org/c/coreboot/+/46348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Gerrit-Change-Number: 46348 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: payloads/coreinfo: Rename pci_scan_bus()
by Felix Singer (Code Review) 20 Oct '20

20 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46557 ) Change subject: payloads/coreinfo: Rename pci_scan_bus() ...................................................................... payloads/coreinfo: Rename pci_scan_bus() Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M payloads/coreinfo/pci_module.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46557/1 diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 0385e9d..ff01770 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -151,7 +151,7 @@ return 0; } -static void pci_scan_bus(int bus) +static void ci_pci_scan_bus(int bus) { int slot, func; unsigned int val; @@ -196,7 +196,7 @@ busses = pci_read_config32(dev, REG_PRIMARY_BUS); - pci_scan_bus((busses >> 8) & 0xff); + ci_pci_scan_bus((busses >> 8) & 0xff); } } @@ -240,7 +240,7 @@ static int pci_module_init(void) { - pci_scan_bus(0); + ci_pci_scan_bus(0); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Gerrit-Change-Number: 46557 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Nico Huber (Code Review) 20 Oct '20

20 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Oct 2020 20:33:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/var/terrador: Update DPTF parameters
by David Wu (Code Review) 20 Oct '20

20 Oct '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46487 ) Change subject: mb/google/volteer/var/terrador: Update DPTF parameters ...................................................................... mb/google/volteer/var/terrador: Update DPTF parameters Update DPTF parameters for terrador BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46487/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..56b4fbd 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -17,6 +17,50 @@ register "SaGv" = "SaGv_Disabled" device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 89, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Gerrit-Change-Number: 46487 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 11

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020