coreboot-gerrit October 2020

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Change in coreboot[master]: amdfwtool: Get size and location of BIOSBIN
by Bao Zheng (Code Review) 20 Oct '20

20 Oct '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46092 to review the following change. Change subject: amdfwtool: Get size and location of BIOSBIN ...................................................................... amdfwtool: Get size and location of BIOSBIN BUG=b:154957411 TEST=Build & boot on mandolin Change-Id: I5a26047726f897c57325387cb304fddbc73f6504 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46092/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..c6bd657 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -208,10 +208,9 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf # TODO(b/154957411): Refactor amdfwtool to extract the address and size from # the elf file. -PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') # This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. -PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) - +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') -- To view, visit https://review.coreboot.org/c/coreboot/+/46092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a26047726f897c57325387cb304fddbc73f6504 Gerrit-Change-Number: 46092 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Frans Hendriks (Code Review) 20 Oct '20

20 Oct '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Oct 2020 12:10:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Frans Hendriks, Jeremy Soller, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46462 to look at the new patch set (#8). Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 51 files changed, 2 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46462/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sb/intel/ibexpeak: Align to coreboot's coding style
by Angel Pons (Code Review) 20 Oct '20

20 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46530 ) Change subject: sb/intel/ibexpeak: Align to coreboot's coding style ...................................................................... sb/intel/ibexpeak: Align to coreboot's coding style Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 92 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46530/1 diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index 8957bfe..e76ef7e 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -35,21 +35,24 @@ RCBA32(0x3598) = 0; reg32 = 0; - for (i = 0; i < TOTAL_USB_PORTS; i++) + for (i = 0; i < TOTAL_USB_PORTS; i++) { if (!portmap[i].enabled) reg32 |= (1 << i); + } RCBA32(USBPDO) = reg32; reg32 = 0; /* The OC pins of the first 8 USB ports are mapped in USBOCM1 */ - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + } RCBA32(USBOCM1) = reg32; reg32 = 0; /* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */ - for (i = 8; i < TOTAL_USB_PORTS; i++) + for (i = 8; i < TOTAL_USB_PORTS; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + } RCBA32(USBOCM2) = reg32; /* Relock registers. */ diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d4f1925..8269dd9 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -89,12 +89,13 @@ static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Interrupt 11 is not used by legacy devices and so can always be used for - PCI interrupts. Full legacy IRQ routing is complicated and hard to - get right. Fortunately all modern OS use MSI and so it's not that big of - an issue anyway. Still we have to provide a reasonable default. Using - interrupt 11 for it everywhere is a working default. ACPI-aware OS can - move it to any interrupt and others will just leave them at default. + /* + * Interrupt 11 is not used by legacy devices and so can always be used for + * PCI interrupts. Full legacy IRQ routing is complicated and hard to + * get right. Fortunately all modern OS use MSI and so it's not that big of + * an issue anyway. Still we have to provide a reasonable default. Using + * interrupt 11 for it everywhere is a working default. ACPI-aware OS can + * move it to any interrupt and others will just leave them at default. */ const u8 pirq_routing = 11; @@ -279,87 +280,81 @@ printk(BIOS_DEBUG, "Mobile 5 PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32 (0x1d44) = 0x00000000; - (void) RCBA32 (0x1d44); - RCBA32 (0x1d48) = 0x00030000; - (void) RCBA32 (0x1d48); - RCBA32 (0x1e80) = 0x000c0801; - (void) RCBA32 (0x1e80); - RCBA32 (0x1e84) = 0x000200f0; - (void) RCBA32 (0x1e84); + RCBA32(0x1d44) = 0x00000000; + (void)RCBA32(0x1d44); + RCBA32(0x1d48) = 0x00030000; + (void)RCBA32(0x1d48); + RCBA32(0x1e80) = 0x000c0801; + (void)RCBA32(0x1e80); + RCBA32(0x1e84) = 0x000200f0; + (void)RCBA32(0x1e84); - const u32 rcba2010[] = - { - /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, - /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 - }; - for (i = 0; i < ARRAY_SIZE(rcba2010); i++) - { - RCBA32 (0x2010 + 4 * i) = rcba2010[i]; - RCBA32 (0x2010 + 4 * i); + const u32 rcba2010[] = { + /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, + /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 + }; + for (i = 0; i < ARRAY_SIZE(rcba2010); i++) { + RCBA32(0x2010 + 4 * i) = rcba2010[i]; + RCBA32(0x2010 + 4 * i); } - RCBA32 (0x2100) = 0x00000000; - (void) RCBA32 (0x2100); - RCBA32 (0x2104) = 0x00000757; - (void) RCBA32 (0x2104); - RCBA32 (0x2108) = 0x00170001; - (void) RCBA32 (0x2108); + RCBA32(0x2100) = 0x00000000; + (void)RCBA32(0x2100); + RCBA32(0x2104) = 0x00000757; + (void)RCBA32(0x2104); + RCBA32(0x2108) = 0x00170001; + (void)RCBA32(0x2108); - RCBA32 (0x211c) = 0x00000000; - (void) RCBA32 (0x211c); - RCBA32 (0x2120) = 0x00010000; - (void) RCBA32 (0x2120); + RCBA32(0x211c) = 0x00000000; + (void)RCBA32(0x211c); + RCBA32(0x2120) = 0x00010000; + (void)RCBA32(0x2120); - RCBA32 (0x21fc) = 0x00000000; - (void) RCBA32 (0x21fc); - RCBA32 (0x2200) = 0x20000044; - (void) RCBA32 (0x2200); - RCBA32 (0x2204) = 0x00000001; - (void) RCBA32 (0x2204); - RCBA32 (0x2208) = 0x00003457; - (void) RCBA32 (0x2208); + RCBA32(0x21fc) = 0x00000000; + (void)RCBA32(0x21fc); + RCBA32(0x2200) = 0x20000044; + (void)RCBA32(0x2200); + RCBA32(0x2204) = 0x00000001; + (void)RCBA32(0x2204); + RCBA32(0x2208) = 0x00003457; + (void)RCBA32(0x2208); - const u32 rcba2210[] = - { - /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, - /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, - /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, - /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, - /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 - }; + const u32 rcba2210[] = { + /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, + /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, + /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, + /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, + /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 + }; - for (i = 0; i < ARRAY_SIZE(rcba2210); i++) - { - RCBA32 (0x2210 + 4 * i) = rcba2210[i]; - RCBA32 (0x2210 + 4 * i); + for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { + RCBA32(0x2210 + 4 * i) = rcba2210[i]; + RCBA32(0x2210 + 4 * i); } - const u32 rcba2300[] = - { - /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, - /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, - /* 2320: */ 0xcccc0cfc, 0x0fbb0fff - }; + const u32 rcba2300[] = { + /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, + /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, + /* 2320: */ 0xcccc0cfc, 0x0fbb0fff + }; - for (i = 0; i < ARRAY_SIZE(rcba2300); i++) - { - RCBA32 (0x2300 + 4 * i) = rcba2300[i]; - RCBA32 (0x2300 + 4 * i); + for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { + RCBA32(0x2300 + 4 * i) = rcba2300[i]; + RCBA32(0x2300 + 4 * i); } - RCBA32 (0x37fc) = 0x00000000; - (void) RCBA32 (0x37fc); - RCBA32 (0x3dfc) = 0x00000000; - (void) RCBA32 (0x3dfc); - RCBA32 (0x3e7c) = 0xffffffff; - (void) RCBA32 (0x3e7c); - RCBA32 (0x3efc) = 0x00000000; - (void) RCBA32 (0x3efc); - RCBA32 (0x3f00) = 0x0000010b; - (void) RCBA32 (0x3f00); + RCBA32(0x37fc) = 0x00000000; + (void)RCBA32(0x37fc); + RCBA32(0x3dfc) = 0x00000000; + (void)RCBA32(0x3dfc); + RCBA32(0x3e7c) = 0xffffffff; + (void)RCBA32(0x3e7c); + RCBA32(0x3efc) = 0x00000000; + (void)RCBA32(0x3efc); + RCBA32(0x3f00) = 0x0000010b; + (void)RCBA32(0x3f00); } static void enable_hpet(void) @@ -573,7 +568,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); acpigen_pop_len(); } } @@ -610,7 +605,7 @@ .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, - .write_acpi_tables = acpi_write_hpet, + .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 472f8e9..0c58f7f 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -12,7 +12,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index b355d9d..bff8d24 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -119,13 +119,13 @@ static inline void write_cb(u32 dword) { - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); + write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -261,9 +261,8 @@ udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); return -1; } @@ -298,8 +297,8 @@ /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); return -1; } diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 4d48eba..958d1db 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -68,7 +68,7 @@ u16 reg16; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 7c9ac82..56da504 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -17,7 +17,7 @@ /* Enable clock gating */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index cce464b..0c5e954 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -102,7 +102,7 @@ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -131,7 +131,10 @@ } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) { + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + } printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); -- To view, visit https://review.coreboot.org/c/coreboot/+/46530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Gerrit-Change-Number: 46530 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/dedede: Add P-sensor for Boten
by Alec Wang (Code Review) 20 Oct '20

20 Oct '20

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46333 ) Change subject: mb/google/dedede: Add P-sensor for Boten ...................................................................... mb/google/dedede: Add P-sensor for Boten Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46333/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 2ba6d9d..1346470 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -9,9 +9,9 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | #| I2C2 | Touchscreen | #| I2C4 | Audio | + #| I2C5 | P-Sensor | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -21,15 +21,15 @@ .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }" # USB Port Configuration @@ -39,7 +39,7 @@ register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, @@ -149,7 +149,16 @@ register "uid" = "1" device i2c 29 on end end - end + end # I2C 4 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + device i2c 28 on end + end + end # I2C 5 device pci 1f.3 on end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Gerrit-Change-Number: 46333 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: mb/google/dedede: add PEN for Boten
by Alec Wang (Code Review) 20 Oct '20

20 Oct '20

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45807 ) Change subject: mb/google/dedede: add PEN for Boten ...................................................................... mb/google/dedede: add PEN for Boten Add PEN to devicetree for boten BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb 3 files changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/45807/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index bd7d36e..fbc669f 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -2,6 +2,7 @@ def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DPTF_USE_EISA_HID + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 05a567f..f889c7f 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), /* C19 : AP_I2C_EMR_SCL */ diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 61dff93..b1fcbe6 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -9,9 +9,8 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | Stylus | #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -28,14 +27,35 @@ .i2c[2] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device pci 15.1 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wake_gpe" = "GPE0_DW2_12" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Gerrit-Change-Number: 45807 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

7 37

Change in coreboot[master]: mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS
by Angel Pons (Code Review) 20 Oct '20

20 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46488 ) Change subject: mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS ...................................................................... mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46488/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 844604a..f55cf09 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -18,6 +18,10 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 +config CBFS_SIZE + hex + default 0x200000 + config MAINBOARD_DIR string default "asrock/b85m_pro4" -- To view, visit https://review.coreboot.org/c/coreboot/+/46488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Gerrit-Change-Number: 46488 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Nico Huber (Code Review) 20 Oct '20

20 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/46274/18/src/cpu/intel/common/comm… File src/cpu/intel/common/common.h: https://review.coreboot.org/c/coreboot/+/46274/18/src/cpu/intel/common/comm… PS18, Line 40: void set_energy_perf_bias(u8 policy); Please write things out (or add comments). For instance, I can't say from the top of my head what TPR or DCA are. The `policy` parameter could be an enum? Or should also be commented. -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Oct 2020 10:44:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by Nico Huber (Code Review) 20 Oct '20

20 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46278 ) Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Oct 2020 10:27:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/model_{2065x,206ax}: fix AES-NI locking
by Nico Huber (Code Review) 20 Oct '20

20 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46535 ) Change subject: cpu/intel/model_{2065x,206ax}: fix AES-NI locking ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Gerrit-Change-Number: 46535 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Oct 2020 10:24:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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