coreboot-gerrit October 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Do dram fast calibration
by CK HU (Code Review) 20 Oct '20

20 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44569 to review the following change. Change subject: soc/mediatek/mt8192: Do dram fast calibration ...................................................................... soc/mediatek/mt8192: Do dram fast calibration Load params from flash and use those params do dram fast calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/emi.c M src/soc/mediatek/mt8192/include/soc/emi.h A src/soc/mediatek/mt8192/memory.c 5 files changed, 162 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44569/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 2412204..55b9999 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -15,4 +15,27 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config DEBUG_DRAM + bool "Output verbose DRAM related debug messages" + default y + help + This option enables additional DRAM related debug messages. + +config MT8192_DRAM_EMCP + bool + default n + help + The eMCP platform should select this option to run at different DRAM + frequencies. + +config MT8192_DRAM_DVFS + bool + default n + help + This options enables DRAM calibration with multiple frequencies (low, + medium and high) for DVFS feature. + +config MEMORY_TEST + bool + default y endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 01db141..19ab639 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -19,6 +19,8 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/mmu_operations.c +romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 7b1d3c2..9e48918 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -8,3 +8,7 @@ return dram_size; } + +void mt_set_emi(const struct dramc_data *dparam) +{ +} diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h index 0348573..02a90be 100644 --- a/src/soc/mediatek/mt8192/include/soc/emi.h +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -3,8 +3,11 @@ #ifndef SOC_MEDIATEK_MT8192_EMI_H #define SOC_MEDIATEK_MT8192_EMI_H -#include <types.h> +#include <soc/dramc_param.h> size_t sdram_size(void); +void mt_set_emi(const struct dramc_data *dparam); +void mt_mem_init(struct dramc_param_ops *dparam_ops); +int complex_mem_test(u8 *start, unsigned int len); #endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c new file mode 100644 index 0000000..84c13b7 --- /dev/null +++ b/src/soc/mediatek/mt8192/memory.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <bootmode.h> +#include <cbfs.h> +#include <console/console.h> +#include <ip_checksum.h> +#include <security/vboot/vboot_common.h> +#include <soc/emi.h> +#include <symbols.h> + +static int mt_mem_test(const struct dramc_data *dparam) +{ + if (CONFIG(MEMORY_TEST)) { + u8 *addr = _dram; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { + int i = complex_mem_test(addr, 0x2000); + + printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s.\n", + (i == 0) ? "pass" : "fail"); + + if (i != 0) { + printk(BIOS_ERR, "DRAM memory test failed\n"); + return -1; + } + + addr += ddr_info->rank_size[rank]; + } + } + + return 0; +} + +static u32 compute_checksum(const struct dramc_param *dparam) +{ + return (u32)compute_ip_checksum(&dparam->dramc_datas, + sizeof(dparam->dramc_datas)); +} + +static int dram_run_fast_calibration(const struct dramc_param *dparam) +{ + if (!is_valid_dramc_param(dparam)) { + printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n"); + dump_param_header((void *)dparam); + return -1; + } + + const u32 checksum = compute_checksum(dparam); + if (dparam->header.checksum != checksum) { + printk(BIOS_ERR, + "Invalid DRAM calibration checksum from flash " + "(expected: %#x, saved: %#x)\n", + checksum, dparam->header.checksum); + return DRAMC_ERR_INVALID_CHECKSUM; + } + + printk(BIOS_INFO, "DRAM calibration data valid pass\n"); + mt_set_emi(&dparam->dramc_datas); + if (mt_mem_test(&dparam->dramc_datas) == 0) + return 0; + + return DRAMC_ERR_FAST_CALIBRATION; +} + +static void mem_init_set_default_config(struct dramc_param *dparam, + u32 ddr_geometry) +{ + memset(dparam, 0, sizeof(*dparam)); + + if (CONFIG(MT8192_DRAM_EMCP)) + dparam->dramc_datas.ddr_info.ddr_type = DDR_TYPE_EMCP; + + if (CONFIG(MT8192_DRAM_DVFS)) + dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS; + dparam->dramc_datas.ddr_info.ddr_geometry = ddr_geometry; + + printk(BIOS_INFO, "DRAM-K: ddr_type:%d, config_dvfs:%d, ddr_geometry:%d\n", + dparam->dramc_datas.ddr_info.ddr_type, + dparam->dramc_datas.ddr_info.config_dvfs, + dparam->dramc_datas.ddr_info.ddr_geometry); +} + +static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry) +{ + struct dramc_param *dparam = dparam_ops->param; + + /* Load calibration params from flash and run fast calibration */ + mem_init_set_default_config(dparam, ddr_geometry); + if (dparam_ops->read_from_flash(dparam)) { + printk(BIOS_INFO, "DRAM-K: Fast Calibration\n"); + if (dram_run_fast_calibration(dparam) != 0) { + printk(BIOS_ERR, "Failed to run fast calibration\n"); + + /* need erase the flash data immediately when fast calibration fail */ + memset(dparam, 0xa5, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } else { + printk(BIOS_INFO, "Fast Calibration PASS\n"); + return; + } + } else { + printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); + } +} + +static void setup_dramc_voltage_before_calibration(void) +{ +//TODO +} + +static void restore_dramc_voltage_after_calibration(void) +{ +//TODO +//switch_dramc_voltage_to_auto_mode() + +/* After DRAM calibration, restore vcore voltage to default setting */ +//pmic_set_vcore_vol(800000); +} + +void mt_mem_init(struct dramc_param_ops *dparam_ops) +{ + const struct sdram_info *sdram_param = get_sdram_config(); + + setup_dramc_voltage_before_calibration(); + mt_mem_init_run(dparam_ops, sdram_param->ddr_geometry); + restore_dramc_voltage_after_calibration(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded Gerrit-Change-Number: 44569 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/12/src/soc/intel/icelake/Kco… File src/soc/intel/icelake/Kconfig: https://review.coreboot.org/c/coreboot/+/45826/12/src/soc/intel/icelake/Kco… PS12, Line 62: select SET_IA32_FC_LOCK_BIT > I'm a bit surprised to find it down here. Could be grouped with […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Oct 2020 09:48:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45826 to look at the new patch set (#14). Change subject: soc/intel/icl: enable common CPU code ...................................................................... soc/intel/icl: enable common CPU code Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/icelake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45826/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46464 to look at the new patch set (#10). Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... cpu/intel/common: correct MSR for the Nominal Performance in CPPC The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 2 files changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46464/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46460 to look at the new patch set (#4). Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... soc/intel: drop unneeded ISST configuration code The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* (de)activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capbability, since one can configure the OS to not enable HWP if that is desired. To reduce complexity and duplicated code without actual benefit, this code, as well as the devicetree option get dropped in this change. This change has one side effect: all boards explicitly disabling or not explicitly enabling ISST now gain ISST support. If the OS is configured to enable HWP if supported, it will do so. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 7 files changed, 0 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46460/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: drop obsolete ISST workaround
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46459 to look at the new patch set (#4). Change subject: mb/google/dedede: drop obsolete ISST workaround ...................................................................... mb/google/dedede: drop obsolete ISST workaround Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/waddledee/Makefile.inc D src/mainboard/google/dedede/variants/waddledee/variant.c M src/mainboard/google/dedede/variants/waddledoo/Makefile.inc D src/mainboard/google/dedede/variants/waddledoo/variant.c 6 files changed, 0 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46459/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Gerrit-Change-Number: 46459 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: replace dt option by MSR write for disabling HWP ca...
by Michael Niewöhner (Code Review) 20 Oct '20

20 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46459 ) Change subject: mb/google/dedede: replace dt option by MSR write for disabling HWP capability ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 2: > > > > Karthikeyan, can you tell us more about the reasons to disable ISST in "early silicon" on these boards, please? > > Sorry for the delay in the response. In the early revisions of Jasperlake silicon with ISST enabled, CPU hangs while booting to OS. The hang point is different - sometimes as soon as the control hits the kernel, whereas sometimes 10s after starting the kernel. > > Having said that, boards with those silicon revisions were used only for development purposes and have been phased out. So this support can be dropped. Thanks for your feedback! That makes it a little easier :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/46459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Gerrit-Change-Number: 46459 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 20 Oct 2020 09:27:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
by Bill XIE (Code Review) 20 Oct '20

20 Oct '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45229 ) Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ...................................................................... mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an enabled integrated graphics device (though no output for it). Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 490 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/1 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md new file mode 100644 index 0000000..8684809 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -0,0 +1,96 @@ +# Supermicro X11SSH-F + +This section details how to run coreboot on the [Supermicro X11SSH-F]. + +## Flashing coreboot + +The board can be flashed externally. [STM32-based programmers] worked. + +The flash IC "W25Q128.V" (detected by flashrom) can be found near PCH PCIe Slot 4. It is sometime +socketed, and covered by a sticker, hindering the observation of its precise model. + +It can be programmed in-system with a clip like pomona 5250. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## Tested and working + +- SeaBIOS payload to boot Kali Linux live USB +- ECC ram (Linux' ie31200 driver works) +- Integrated graphics device available without output +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- S3 resume not working +- SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled) + +## ToDo + +- Fix known issues +- Testing other payloads + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 1x 3.0 x4 (in x8) | +| | 1x 3.0 x2 (in M.2 slot with key M) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port (connector may absent) | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSH-F] +- [Board manual] + +[Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[STM32-based programmers]: https://github.com/dword1511/stm32-vserprog diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index a446835..c4df4848 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -25,6 +25,7 @@ string default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F + default "X11SSH-F" if BOARD_SUPERMICRO_X11SSH_F config MAINBOARD_DIR string @@ -34,6 +35,7 @@ string default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F + default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F config OVERRIDE_DEVICETREE string @@ -89,5 +91,6 @@ string default "0896" if BOARD_SUPERMICRO_X11SSM_F default "089C" if BOARD_SUPERMICRO_X11SSH_TF + default "0884" if BOARD_SUPERMICRO_X11SSH_F endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index 7b2eaaf..7cb19ae 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SUPERMICRO_X11SSM_F bool "X11SSM-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSH_F + bool "X11SSH-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt new file mode 100644 index 0000000..bf0cd99 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSH-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h new file mode 100644 index 0000000..bbaad7d8 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _GPIO_X11SSH_TF_H +#define _GPIO_X11SSH_TF_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +/*** XXX TODO XXX */ +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb new file mode 100644 index 0000000..ed571ba --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -0,0 +1,137 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + + # PCIe configuration + # Enable i210-AT (GbE) + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + + # Enable M.2 + register "PcieRpEnable[4]" = "1" + + # Enable ASpeed PCI bridge + register "PcieRpEnable[6]" = "1" + + # Enable JPCIE1 + register "PcieRpEnable[8]" = "1" + + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end # CPU PCIE Slot (JPCIE3) + device pci 01.1 on # CPU PCIE Slot (JPCIE2) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 02.0 on end # Integrated Graphics Device (No Output) + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on end # GbE + end + device pci 1c.1 on # PCI Express Port 2 + device pci 00.0 on end # GbE + end + device pci 1c.4 on # PCI Express Port 5 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + drq 0xf0 = 0x00 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + drq 0xf0 = 0x00 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/45229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Gerrit-Change-Number: 45229 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 38

Change in coreboot[master]: WIP: soc/mediatek/mt8192: add display debug log
by yongqiang niu (Code Review) 20 Oct '20

20 Oct '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46584 ) Change subject: WIP: soc/mediatek/mt8192: add display debug log ...................................................................... WIP: soc/mediatek/mt8192: add display debug log Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: Ie2fb7c51d32392ec33cf389df3f60130ced3887e --- M src/soc/mediatek/mt8192/ddp.c 1 file changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46584/1 diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c index 0d5eab5..8136d2b 100644 --- a/src/soc/mediatek/mt8192/ddp.c +++ b/src/soc/mediatek/mt8192/ddp.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/mmio.h> #include <edid.h> #include <soc/addressmap.h> @@ -166,6 +167,70 @@ clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); } +//#define cnt_va_to_pa(va) (((void*)(va) - )) +struct module_info { + const char *name; + void *va; + //u32 pa; + u32 offset; + u32 lenght; +}; + +struct module_info dump_info[] = { + {"mmsys", (void *)MMSYS_BASE, 0x100, 0x100}, + +#if 1 + {"mmsys", (void *)MMSYS_BASE, 0xf00, 0x100}, + {"mutex", (void *)DISP_MUTEX_BASE, 0x000, 0x100}, + {"ovl0", (void *)DISP_OVL0_BASE, 0x000, 0x100}, + {"ovl0", (void *)DISP_OVL0_BASE, 0xf00, 0x100}, + {"ovl0_2l", (void *)DISP_OVL1_BASE, 0x000, 0x100}, + {"ovl0_2l", (void *)DISP_OVL1_BASE, 0xf00, 0x100}, + {"rdma0", (void *)DISP_RDMA0_BASE, 0x000, 0x100}, + {"color0", (void *)DISP_COLOR0_BASE, 0x400, 0x100}, + {"color0", (void *)DISP_COLOR0_BASE, 0xc00, 0x100}, + {"ccorr0", (void *)DISP_CCORR0_BASE, 0x000, 0x100}, + {"aal0", (void *)DISP_AAL0_BASE, 0x000, 0x100}, + {"aal0", (void *)DISP_AAL0_BASE, 0x400, 0x100}, + {"gamma0", (void *)DISP_GAMMA0_BASE, 0x000, 0x100}, + {"postmask0", (void *)DISP_POSTMASK0_BASE, 0x000, 0x100}, + {"dither0", (void *)DISP_DITHER0_BASE, 0x000, 0x100}, + {"dsi0", (void *)DSI0_BASE, 0x000, 0x100}, +#endif +}; + +static void dump_module(struct module_info *comp) +{ + u32 i; + void *local_offset; + + printk(BIOS_INFO, "start dump module %s\n", comp->name); + + local_offset = (comp->va + comp->offset); + + for (i = 0; i < comp->lenght/4; i+=4, local_offset+=16) { + printk(BIOS_INFO, "0x%08llX | %08X %08X %08X %08X\n", + (u64)local_offset, + read32((local_offset + 0x0)), + read32((local_offset + 0x4)), + read32((local_offset + 0x8)), + read32((local_offset + 0xc))); + } +} + +static void dump_disp_info(void) +{ + u32 i; + struct module_info *comp; + + printk(BIOS_INFO, "%s\n", __func__); + + for (i = 0; i < sizeof(dump_info)/ sizeof(struct module_info); i++) { + comp = &dump_info[i]; + dump_module(comp); + } +} + void mtk_ddp_init(void) { disp_clock_on(); @@ -196,4 +261,8 @@ rdma_start(); ovl_layer_config(fmt, bpp, width, height); ovl_bgclr_in_sel(1); + + dump_disp_info(); + + //while(1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2fb7c51d32392ec33cf389df3f60130ced3887e Gerrit-Change-Number: 46584 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: ec/google/chromeec: Add wrappers to get/set the voltage
by Yidi Lin (Code Review) 20 Oct '20

20 Oct '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46404 ) Change subject: ec/google/chromeec: Add wrappers to get/set the voltage ...................................................................... ec/google/chromeec: Add wrappers to get/set the voltage Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46404/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 82de088..39cf895 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1616,3 +1616,50 @@ return 0; } + +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv) +{ + struct ec_params_regulator_set_voltage params = { + .index = index, + .min_mv = min_mv, + .max_mv = max_mv, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_SET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) +{ + struct ec_params_regulator_get_voltage params = { + .index = index, + }; + struct ec_response_regulator_get_voltage resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_GET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *voltage_mv = resp.voltage_mv; + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ad3768c..0e28344 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,6 +353,23 @@ */ int google_chromeec_ap_reset(void); +/** + * Set voltage for the voltage regulator within the range specified. + * @param index Regulator ID + * @param min_mv Minimum voltage + * @param max_mv Maximum voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv); +/** + * Get the currently configured voltage for the voltage regulator. + * @param index Regulator ID + * @param *voltage_mv If successful, voltage_mv is filled with current voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT -- To view, visit https://review.coreboot.org/c/coreboot/+/46404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Gerrit-Change-Number: 46404 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020