Change in coreboot[master]: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an enabled integrated graphics device (though no output for it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 490 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/1
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md new file mode 100644 index 0000000..8684809 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -0,0 +1,96 @@ +# Supermicro X11SSH-F + +This section details how to run coreboot on the [Supermicro X11SSH-F]. + +## Flashing coreboot + +The board can be flashed externally. [STM32-based programmers] worked. + +The flash IC "W25Q128.V" (detected by flashrom) can be found near PCH PCIe Slot 4. It is sometime +socketed, and covered by a sticker, hindering the observation of its precise model. + +It can be programmed in-system with a clip like pomona 5250. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## Tested and working + +- SeaBIOS payload to boot Kali Linux live USB +- ECC ram (Linux' ie31200 driver works) +- Integrated graphics device available without output +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- S3 resume not working +- SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled) + +## ToDo + +- Fix known issues +- Testing other payloads + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 1x 3.0 x4 (in x8) | +| | 1x 3.0 x2 (in M.2 slot with key M) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port (connector may absent) | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSH-F] +- [Board manual] + +[Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[STM32-based programmers]: https://github.com/dword1511/stm32-vserprog diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index a446835..c4df4848 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -25,6 +25,7 @@ string default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F + default "X11SSH-F" if BOARD_SUPERMICRO_X11SSH_F
config MAINBOARD_DIR string @@ -34,6 +35,7 @@ string default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F + default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F
config OVERRIDE_DEVICETREE string @@ -89,5 +91,6 @@ string default "0896" if BOARD_SUPERMICRO_X11SSM_F default "089C" if BOARD_SUPERMICRO_X11SSH_TF + default "0884" if BOARD_SUPERMICRO_X11SSH_F
endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index 7b2eaaf..7cb19ae 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SUPERMICRO_X11SSM_F bool "X11SSM-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSH_F + bool "X11SSH-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt new file mode 100644 index 0000000..bf0cd99 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSH-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h new file mode 100644 index 0000000..bbaad7d8 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _GPIO_X11SSH_TF_H +#define _GPIO_X11SSH_TF_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +/*** XXX TODO XXX */ +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb new file mode 100644 index 0000000..ed571ba --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -0,0 +1,137 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + + # PCIe configuration + # Enable i210-AT (GbE) + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + + # Enable M.2 + register "PcieRpEnable[4]" = "1" + + # Enable ASpeed PCI bridge + register "PcieRpEnable[6]" = "1" + + # Enable JPCIE1 + register "PcieRpEnable[8]" = "1" + + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end # CPU PCIE Slot (JPCIE3) + device pci 01.1 on # CPU PCIE Slot (JPCIE2) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 02.0 on end # Integrated Graphics Device (No Output) + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on end # GbE + end + device pci 1c.1 on # PCI Express Port 2 + device pci 00.0 on end # GbE + end + device pci 1c.4 on # PCI Express Port 5 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + drq 0xf0 = 0x00 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + drq 0xf0 = 0x00 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#3).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an enabled integrated graphics device (though no output for it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 495 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG@11 PS3, Line 11: (though no output for it) If the integrated graphics device is unusable, I'd disable it. If it can be used for compute tasks, then I'd mention that it's enabled for this reason so that no one disables it again.
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working I think this is because of FSP-M and SPS firmware. SPS firmware doesn't support CpuReplacementCheck, so FSP-M always does a full memory training.
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel I'd disable it then.
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 73: smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" I'd break these SMBIOS lines in two
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
I think this is because of FSP-M and SPS firmware. […]
I had never tested S3 with vendor firmware (or maybe I just don't remember anymore). Did you?
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8: didn't check this, yet. was that just copied or is it verified with inteltool/intelp2m?
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 229: /*** XXX TODO XXX */ that can be dropped
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 32: # FIXME: find out why FSP crashes without this does that still apply?
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 78: on disable it since there is no output
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#4).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an integrated graphics device (though it has no output, it is said to be able to be used for compute tasks, so I decide to enable it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 520 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/4
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG@11 PS3, Line 11: (though no output for it)
If the integrated graphics device is unusable, I'd disable it. […]
It is said to be able to be used for compute tasks, so I will mention that.
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
I had never tested S3 with vendor firmware (or maybe I just don't remember anymore). […]
Done
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel
I'd disable it then.
It is said to be able to be used for compute tasks, should I disable it currently?
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
didn't check this, yet. […]
COnfirmed with inteltool/intelp2m, but with a lot of _PAD_CFG_STRUCT() unknown how to simplify.
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 229: /*** XXX TODO XXX */
that can be dropped
Done
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 32: # FIXME: find out why FSP crashes without this
does that still apply?
These can be removed.
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 73: smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
I'd break these SMBIOS lines in two
Done
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 78: on
disable it since there is no output
It is said to be able to be used for compute tasks, should I disable it currently?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG@11 PS3, Line 11: (though no output for it)
It is said to be able to be used for compute tasks, so I will mention that.
Sorry if I didn't explain myself clearly before. I don't know if the IGD can be used for compute tasks on this board. But if it doesn't work at all with coreboot, then I doubt it is possible.
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel
I'd disable it then. […]
If it doesn't work at all, I would disable it. I was thinking that you may have wanted to use it for compute-related tasks, but if this is not the case, then it should be off.
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 78: on
It is said to be able to be used for compute tasks, should I disable it currently?
If it doesn't work, I would disable it.
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG@11 PS3, Line 11: (though no output for it)
Sorry if I didn't explain myself clearly before. […]
The IGD is enabled, properly initialized, and is said capable to be used for compute tasks (e.g. https://forums.servethehome.com/index.php?threads/issue-with-e3-1245-v6-igpu... ), under the vendor firmware, so it just has not gotten working under coreboot YET.
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel
If it doesn't work at all, I would disable it. […]
It works under the vendor firmware, and I do want to use it for for compute-related tasks. I just has not gotten the way to initialize it to the state just as how the vendor firmware does.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG@11 PS3, Line 11: (though no output for it)
The IGD is enabled, properly initialized, and is said capable to be used for compute tasks (e.g. […]
Oh, I understand now. Thanks for the clarification.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
Done
uhm, "Done" means what? ;) did you test this with vendor firmware? if it doesn't work with vendor, please mention that
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel
It works under the vendor firmware, and I do want to use it for for compute-related tasks. […]
What CPU do you use?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: Currentlt Currently, ...
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize fails to be initialized
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 14: # Additional FSP Configuration : # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_Auto" : what for? there is no display (connector)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 18: # PCIe configuration : # Enable i210-AT (GbE) : register "PcieRpEnable[0]" = "1" : register "PcieRpEnable[1]" = "1" : : # Enable M.2 : register "PcieRpEnable[4]" = "1" : : # Enable ASpeed PCI bridge : register "PcieRpEnable[6]" = "1" : : # Enable JPCIE1 : register "PcieRpEnable[8]" = "1" : move these down to the devicetree, please
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 39: - The IGD has an invalid state on coreboot and failed to be initialize by Linux kernel
What CPU do you use?
I'm sorry, I missed https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG#11 .
CPU is e3-1245v6, which supports IGD.
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 78: on
If it doesn't work, I would disable it.
see https://review.coreboot.org/c/coreboot/+/45229/3//COMMIT_MSG#11
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 4:
Some minor stuff left, then we can merge this ;-)
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#5).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an integrated graphics device (though it has no output, it is said to be able to be used for compute tasks, so I decide to enable it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 520 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/5
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
uhm, "Done" means what? ;) did you test this with vendor firmware? if it doesn't work with vendor, p […]
S3 doesn't work with vendor, which is mentioned in the document.
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: Currentlt
Currently, ...
Done
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize
fails to be initialized
This seems to be because of a problematic kernel command line parameter. I am going to confirm it before mark this resolved.
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize
fails to be initialized
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 14: # Additional FSP Configuration : # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_Auto" :
what for? there is no display (connector)
I will change it into "Display_PCH_PCIe", but would it interfere if a graphic card is installed on the PEG?
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 18: # PCIe configuration : # Enable i210-AT (GbE) : register "PcieRpEnable[0]" = "1" : register "PcieRpEnable[1]" = "1" : : # Enable M.2 : register "PcieRpEnable[4]" = "1" : : # Enable ASpeed PCI bridge : register "PcieRpEnable[6]" = "1" : : # Enable JPCIE1 : register "PcieRpEnable[8]" = "1" :
move these down to the devicetree, please
What do you mean? Tree-style configs already lies below, or can these above and the tree-style configs below substitute each other?
Register configs for PCI-E ports and tree-style configs co-exist in override trees of other variants.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 5:
(24 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
S3 doesn't work with vendor, which is mentioned in the document.
Sorry, I may be just blind... I don't see any comment on vendor fw, just "S3 resume not working" (which would mean "not working in coreboot").
What about this? "S3 not working (vendor and coreboto) due to lacking S3 support in Intel SPS"
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize
This seems to be because of a problematic kernel command line parameter. […]
Add some notes about using IGD for computaion, please, if you're able to resolve the issue
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 23: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0 this does not match the prior version (GPO) but now means PAD_NC. Can you provide the raw values from inteltool, please?
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 30: PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), changed from DRIVER to ACPI; please provide raw inteltool output
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 40: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0 TX_RX_DISABLE + no NFx -> PAD_NC was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 54: /* GPIO */ drop comment
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 77: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), : _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), not sure about these, yet; provide intel raw output, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 85: AD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), TX_RX_DISABLE + no NFx -> PAD_NC was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 94: G_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL( the prior version is correct
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 97: PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), TX_RX_DISABLE + no NFx -> PAD_NC was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 101: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), : TX_RX_DISABLE + no NFx -> PAD_NC was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 104: _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU the prior version was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 126: TRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 < probably PAD_CFG_GPI or even NC; provide raw value, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 131: PAD_NC(GPP_E0, NONE), why did this change from NF1 to NC?
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 137: RUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K the prior version was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 157: G_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), probably PAD_CFG_GPI or even NC; provide raw value, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 173: FG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 probably PAD_CFG_GPI or even NC; provide raw value, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 189: PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI changed from DRIVER to ACPI; reason?
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 202: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | ( probably PAD_CFG_GPI or even NC; provide raw value, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 206: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) probably PAD_CFG_GPI or even NC; provide raw value, please
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 236: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) : | PAD_BUF(TX_RX_DISABLE) | 1, 0), : TX_RX_DISABLE + no NFx -> PAD_NC was right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 14: # Additional FSP Configuration : # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_Auto" :
I will change it into "Display_PCH_PCIe", but would it interfere if a graphic card is installed on t […]
Sorry for the confusion; I haven't thought about that case. Let's keep Display_Auto, so both PEG and PCH PCIe work. :-)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 18: # PCIe configuration : # Enable i210-AT (GbE) : register "PcieRpEnable[0]" = "1" : register "PcieRpEnable[1]" = "1" : : # Enable M.2 : register "PcieRpEnable[4]" = "1" : : # Enable ASpeed PCI bridge : register "PcieRpEnable[6]" = "1" : : # Enable JPCIE1 : register "PcieRpEnable[8]" = "1" :
What do you mean? Tree-style configs already lies below, or can these above and the tree-style confi […]
The PcieRpEnable fsp settings are going to be set via the on/off setting in the devicetree in the near future. This is already done e.g. in cannonlake. To make review easier later, we started moving these settings into the devicetree:
device pci 1c.4 on # PCI Express Port 5 register "PcieRpEnable[4]" = "1" smbios_slot_desc ... end
https://review.coreboot.org/c/coreboot/+/45229/5/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/5/src/mainboard/supermicro/x1... PS5, Line 15: # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_PCH_PCIe" That was my fault, sorry. Let's keep auto see https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1...
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
COnfirmed with inteltool/intelp2m, but with a lot of _PAD_CFG_STRUCT() unknown how to simplify.
I have added some comments below; would be great if you could provide the raw inteltool output; just put it to some paste site or ping me in irc (c0d3z3r0)
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#6).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an integrated graphics device (though it has no output, it is said to be able to be used for compute tasks, so I decide to enable it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 515 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/6
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
Sorry, I may be just blind... […]
Done
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize
Add some notes about using IGD for computaion, please, if you're able to resolve the issue
Done
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
I have added some comments below; would be great if you could provide the raw inteltool output; just […]
inteltool dunp: https://pastebin.com/yzfpLx9f
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 14: # Additional FSP Configuration : # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_Auto" :
Sorry for the confusion; I haven't thought about that case. […]
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 18: # PCIe configuration : # Enable i210-AT (GbE) : register "PcieRpEnable[0]" = "1" : register "PcieRpEnable[1]" = "1" : : # Enable M.2 : register "PcieRpEnable[4]" = "1" : : # Enable ASpeed PCI bridge : register "PcieRpEnable[6]" = "1" : : # Enable JPCIE1 : register "PcieRpEnable[8]" = "1" :
The PcieRpEnable fsp settings are going to be set via the on/off setting in the devicetree in the ne […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 6:
(7 comments)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 21: If an IGD is integrated with CPU, it will be enabled on this board. Though there is no video output add a newline above
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 22: it is said capable to be it is said to be capable of being used for
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC huh? what for?
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: switcheroo add a link?
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
inteltool dunp: https://pastebin. […]
great, thanks! I'll check that in the next days
https://review.coreboot.org/c/coreboot/+/45229/5/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/5/src/mainboard/supermicro/x1... PS5, Line 15: # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_PCH_PCIe"
That was my fault, sorry. Let's keep auto see https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/45229/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/6/src/mainboard/supermicro/x1... PS6, Line 82: smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" : smbios_slot_desc "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" : uhm, that won't work ;)
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#7).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an integrated graphics device (though it has no output, it is said to be able to be used for compute tasks, so I decide to enable it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 516 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/7
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 21: If an IGD is integrated with CPU, it will be enabled on this board. Though there is no video output
add a newline above
Done
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 22: it is said capable to be
it is said to be capable of being used for
Done
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: switcheroo
add a link?
Done
https://review.coreboot.org/c/coreboot/+/45229/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/6/src/mainboard/supermicro/x1... PS6, Line 82: smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" : smbios_slot_desc "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" :
uhm, that won't work ;)
Done
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
huh? what for?
Is there any further question here?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
Is there any further question here?
yup, I don't get what you want to render for the BMC? the BMC has it's own VGA graphics device
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
great, thanks! I'll check that in the next days
sorry for letting you wait; I'm going to check this now :)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
yup, I don't get what you want to render for the BMC? the BMC has it's own VGA graphics device
well, I guess I got it. with switcheroo one can offload the rendering and do the output via the BMC VGA chip?
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
Is there any further question here?
@Bill Did you try it? Did it work?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(18 comments)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 23: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0
this does not match the prior version (GPO) but now means PAD_NC. […]
PAD_NC(GPP_A12, NONE),
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 30: PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI),
changed from DRIVER to ACPI; please provide raw inteltool output
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 40: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0
TX_RX_DISABLE + no NFx -> PAD_NC was right
yes, B2-B10 are NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 77: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), : _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
not sure about these, yet; provide intel raw output, please
all three NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 94: G_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(
the prior version is correct
PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 97: PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
TX_RX_DISABLE + no NFx -> PAD_NC was right
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 101: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), :
TX_RX_DISABLE + no NFx -> PAD_NC was right
D0 - NC D1 is right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 104: _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU
the prior version was right
PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 126: TRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 <
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 131: PAD_NC(GPP_E0, NONE),
why did this change from NF1 to NC?
NC is right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 137: RUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K
the prior version was right
PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE),
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 157: G_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 173: FG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1
probably PAD_CFG_GPI or even NC; provide raw value, please
G0-G3 NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 189: PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI
changed from DRIVER to ACPI; reason?
G12-G16 - NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 202: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 206: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1)
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 236: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) : | PAD_BUF(TX_RX_DISABLE) | 1, 0), :
TX_RX_DISABLE + no NFx -> PAD_NC was right
PAD_NC(GPD7, NONE) GPD8 is right
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
sorry for letting you wait; I'm going to check this now :)
see comments in patchset 4
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
well, I guess I got it. with switcheroo one can offload the rendering and do the output via the BMC VGA chip?
Yes. The graphic card within BMC has no hardware-accelerated rendering capability, while the IGD has such capability but without output. If their capabilities are combined via switcheroo, it may be possible to achieve better graphic performance.
@Bill Did you try it? Did it work?
Not yet. It should be related little to coreboot, for it should mostly related to OS configuration, and may also be done under the vendor firmware.
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#8).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another x11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, Ethernet interfaces, and an integrated graphics device (though it has no output, it is said to be able to be used for compute tasks, so I decide to enable it).
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 487 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/8
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 8: Code-Review+1
(22 comments)
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/6/Documentation/mainboard/sup... PS6, Line 23: render graphics for BMC
well, I guess I got it. […]
Since it's not board-related there's no reason it wouldn't work when the CPU is IGD-capable. However, *because* it is not board-related, we should think about moving this later to some more generic docs section.
I don't want to block this change any longer, so I mark this as resolved for now. Let's maybe move that in some follow-up.
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... PS8, Line 23: it, (The onboard VGA port is connected to BMC) it it (the onboard VGA port is connected to BMC), it
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... PS8, Line 24: probably rendering graphics for BMC or other graphic cards to output via [vga_witcheroo] Let's just drop mentioning BMC here, since it could confuse people. What about this?
... or for offloading graphics rendering via "muxless" [vga_witcheroo].
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 84: PAD_NC(GPP_C23, NONE) got lost ;)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 23: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0
PAD_NC(GPP_A12, NONE),
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 30: PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI),
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 40: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0
yes, B2-B10 are NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 54: /* GPIO */
drop comment
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 77: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), : _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
all three NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 85: AD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
TX_RX_DISABLE + no NFx -> PAD_NC was right
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 94: G_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(
PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE)
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 97: PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 101: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), :
D0 - NC […]
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 104: _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU
PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE)
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 126: TRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 <
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 137: RUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K
PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE),
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 157: G_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 173: FG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1
G0-G3 NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 189: PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI
G12-G16 - NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 202: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 206: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1)
NC
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 236: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) : | PAD_BUF(TX_RX_DISABLE) | 1, 0), :
PAD_NC(GPD7, NONE) […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 2: can you do one last test with the adapted gpio config, please?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@9 PS8, Line 9: x11 X11
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@10 PS8, Line 10: Ethernet ethernet
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@11 PS8, Line 11: and an integrated graphics device (though it has no output, it is said : to be able to be used for compute tasks, so I decide to enable it). drop this, since it's not board-related but depends on which cpu one installs
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45229
to look at the new patch set (#9).
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 488 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45229/9
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 2:
can you do one last test with the adapted gpio config, please?
Sure. I will do it tomorrow along with my own task.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 9:
(7 comments)
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@9 PS8, Line 9: x11
X11
Done
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@10 PS8, Line 10: Ethernet
ethernet
Done
https://review.coreboot.org/c/coreboot/+/45229/8//COMMIT_MSG@11 PS8, Line 11: and an integrated graphics device (though it has no output, it is said : to be able to be used for compute tasks, so I decide to enable it).
drop this, since it's not board-related but depends on which cpu one installs
Done
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... PS8, Line 23: it, (The onboard VGA port is connected to BMC) it
it (the onboard VGA port is connected to BMC), it
Done
https://review.coreboot.org/c/coreboot/+/45229/8/Documentation/mainboard/sup... PS8, Line 24: probably rendering graphics for BMC or other graphic cards to output via [vga_witcheroo]
Let's just drop mentioning BMC here, since it could confuse people. What about this? […]
Done
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 84:
PAD_NC(GPP_C23, NONE) got lost ;)
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 97: PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
Done
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 9: Code-Review+1
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 2:
Sure. I will do it tomorrow along with my own task.
It works with no noticeable problem.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/8/src/mainboard/supermicro/x1... PS8, Line 2:
It works with no noticeable problem.
Awesome :)
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb 6 files changed, 488 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md new file mode 100644 index 0000000..f009bbe --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -0,0 +1,103 @@ +# Supermicro X11SSH-F + +This section details how to run coreboot on the [Supermicro X11SSH-F]. + +## Flashing coreboot + +The board can be flashed externally. [STM32-based programmers] worked. + +The flash IC "W25Q128.V" (detected by flashrom) can be found near PCH PCIe Slot 4. It is sometime +socketed, and covered by a sticker, hindering the observation of its precise model. + +It can be programmed in-system with a clip like pomona 5250. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## IGD + +If an IGD is integrated with CPU, it will be enabled on this board. Though there is no video output +for it (The onboard VGA port is connected to BMC), it is said to be capable of being used for compute +tasks, or for offloading graphics rendering via "muxless" [vga_witcheroo]. + +## Tested and working + +- SeaBIOS payload to boot Kali Linux live USB +- ECC ram (Linux' ie31200 driver works) +- Integrated graphics device available without output +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- S3 resume not working (vendor and coreboot) +- SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled) + +## ToDo + +- Fix known issues +- Testing other payloads + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 1x 3.0 x4 (in x8) | +| | 1x 3.0 x2 (in M.2 slot with key M) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port (connector may absent) | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSH-F] +- [Board manual] + +[Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[STM32-based programmers]: https://github.com/dword1511/stm32-vserprog +[vga_switcheroo]: https://01.org/linuxgraphics/gfx-docs/drm/gpu/vga-switcheroo.html diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index a446835..c4df4848 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -25,6 +25,7 @@ string default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F + default "X11SSH-F" if BOARD_SUPERMICRO_X11SSH_F
config MAINBOARD_DIR string @@ -34,6 +35,7 @@ string default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F + default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F
config OVERRIDE_DEVICETREE string @@ -89,5 +91,6 @@ string default "0896" if BOARD_SUPERMICRO_X11SSM_F default "089C" if BOARD_SUPERMICRO_X11SSH_TF + default "0884" if BOARD_SUPERMICRO_X11SSH_F
endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index 7b2eaaf..7cb19ae 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SUPERMICRO_X11SSM_F bool "X11SSM-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSH_F + bool "X11SSH-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt new file mode 100644 index 0000000..bf0cd99 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSH-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h new file mode 100644 index 0000000..93e0574 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _GPIO_X11SSH_F_H +#define _GPIO_X11SSH_F_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_NC(GPP_F9, NONE), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H4, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +#endif /* _GPIO_X11SSH_F_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb new file mode 100644 index 0000000..c3f4bf1 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -0,0 +1,129 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + + # Additional FSP Configuration + # This board has an IGD with no output. + register "PrimaryDisplay" = "Display_Auto" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end # CPU PCIE Slot (JPCIE3) + device pci 01.1 on # CPU PCIE Slot (JPCIE2) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 02.0 on end # Integrated Graphics Device (No Output) + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.1 on # PCI Express Port 2 + register "PcieRpEnable[1]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" + end + device pci 1c.6 on # PCI Express Port 7 + register "PcieRpEnable[6]" = "1" + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + register "PcieRpEnable[8]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + drq 0xf0 = 0x00 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + drq 0xf0 = 0x00 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end
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Angel Pons (Code Review) -
Bill XIE (Code Review)
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Felix Singer (Code Review)
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Michael Niewöhner (Code Review)