coreboot-gerrit October 2020

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Change in coreboot[master]: edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h
by Ronak Kanabar (Code Review) 29 Oct '20

29 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45906 ) Change subject: edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9698861be1f969ddca7f171767a54ac486502c74 Gerrit-Change-Number: 45906 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 06:55:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Ronak Kanabar (Code Review) 29 Oct '20

29 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 06:55:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Remove deprecated header
by Ronak Kanabar (Code Review) 29 Oct '20

29 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45908 ) Change subject: vendorcode/intel/fsp: Remove deprecated header ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c Gerrit-Change-Number: 45908 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 06:54:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group
by Maulik V Vaghela (Code Review) 29 Oct '20

29 Oct '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/g… File src/soc/intel/jasperlake/gpio.c: https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/g… PS2, Line 50: INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), > Thanks for sharing more context. It helps. Thank you karthik. I have aligned GPIO properly by also checking pinctrl driver also. Now all host own offset are aligning with EDS also. -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Oct 2020 05:51:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group
by Maulik V Vaghela (Code Review) 29 Oct '20

29 Oct '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/g… File src/soc/intel/jasperlake/gpio.c: https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/g… PS4, Line 37: INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ : INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ : INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ : INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ > HOSTSW_OWN register for GPP_B is at offset 0xC8, GPP_A at 0xCC, GPP_S at 0xD0, GPP_R at 0xD4. […] Done https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/g… PS4, Line 60: INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288) > Going by your explanation, this group's HOSTSW_OWN register will be at offset 0xC0. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Oct 2020 05:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group
by Maulik V Vaghela (Code Review) 29 Oct '20

29 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46842 to look at the new patch set (#5). Change subject: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group ...................................................................... soc/intel/jasperlake: Move reserved gpio at the end of comm pad group In gpio.c file, we have community group array for each comm, representing gpio groups within that community. Like there might be group H,D, VGPIO and C within community 1. Community also may have some reserved gpio and we also define those in an array which indicates OS can't use those GPIO (through PAD_BASE_NONE) Now when we define reserved pads in the middle of actual community pads, it creates an issue while calculating an offset for GPIO host own pad register. This is because function actually checks current gpio index (lets say vgpio_39 in our case) and tries to get group index from an array which we have defined. If we have defined reserved gpios in between 2 communities, index calculated will also account for reserved GPIO and register offset calculation will move to next set of register (offset 0xC instead of offset 0x8). Because of this coreboot won't configure HOST_OWN_PAD register correctly and driver will not be able to get non-SMI interrupts for related gpio. Moving all reserved community pads at the end solves this issue. BUG=None BRANCH=None TEST=VGPIO community index is correctly calculated. Drawlat board boots fine with this change and warm reset also works. Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/gpio.c 1 file changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: Do dram full calibration
by CK HU (Code Review) 29 Oct '20

29 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44570 to review the following change. Change subject: soc/mediatek/mt8192: Do dram full calibration ...................................................................... soc/mediatek/mt8192: Do dram full calibration If no correct params was found in flash, do dram full calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 19ab639..dd80beb 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,16 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 84c13b7..96a8c91 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -64,6 +64,39 @@ return DRAMC_ERR_FAST_CALIBRATION; } +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) + return -1; + + if (cbfs_prog_stage_load(&dram)) + return -2; + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -103,6 +136,20 @@ } else { printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "Successfully loaded blobs and run DRAM calibration\n"); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } } static void setup_dramc_voltage_before_calibration(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Gerrit-Change-Number: 44570 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable super-i/o LDNs 0x0f and 0x14
by Nico Huber (Code Review) 29 Oct '20

29 Oct '20

Hello Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46021 to review the following change. Change subject: mb/asus/f2a85-m_pro: Enable super-i/o LDNs 0x0f and 0x14 ...................................................................... mb/asus/f2a85-m_pro: Enable super-i/o LDNs 0x0f and 0x14 The LDNs don't have a 0x30 register to enable them. However, with the devices set to `off`, coreboot won't configure them. Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46021/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 654716b..4e124f2 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -97,10 +97,10 @@ end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off # GPIO Push-pull/Open-drain selection + device pnp 2e.f on # GPIO Push-pull/Open-drain selection irq 0xe6 = 7f end - device pnp 2e.14 off # PORT80 UART + device pnp 2e.14 on # PORT80 UART irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep -- To view, visit https://review.coreboot.org/c/coreboot/+/46021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Gerrit-Change-Number: 46021 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Clean up super-i/o GPIO settings
by Nico Huber (Code Review) 29 Oct '20

29 Oct '20

Hello Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46020 to review the following change. Change subject: mb/asus/f2a85-m_pro: Clean up super-i/o GPIO settings ...................................................................... mb/asus/f2a85-m_pro: Clean up super-i/o GPIO settings Drop useless writes to read-only registers and don't re-write default 0x00 values. In detail: * Don't write read-only status registers. * Don't try to write input bits in data registers (iow. mask data values: `data &= ~io`). * Don't write data registers if all GPIOs are set as inputs (`io == 0xff`). * Don't write default 0x00 for inversion and multiplex registers. Note: Both GPIO0 and WDT1 values look spurious. Maybe they were dumped with the virtual devices disabled? Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 2 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46020/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index aa2d52e..654716b 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -46,36 +46,18 @@ device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 irq 0xf4 = 0xff # GPIO6 i/o - irq 0xf5 = 0xff # GPIO6 data - irq 0xf6 = 0x00 # GPIO6 inversion - irq 0xf7 = 0x00 # GPIO6 status - irq 0xf8 = 0x00 # GPIO6 multiplex irq 0xe0 = 0x7f # GPIO7 i/o - irq 0xe1 = 0x10 # GPIO7 data - irq 0xe2 = 0x00 # GPIO7 inversion - irq 0xe3 = 0x00 # GPIO7 status - irq 0xec = 0x00 # GPIO7 multiplex - - irq 0xe4 = 0xff # GPIO8 i/o - irq 0xe5 = 0xff # GPIO8 data - irq 0xe6 = 0xff # GPIO8 inversion - irq 0xe7 = 0xff # GPIO8 status - irq 0xed = 0xff # GPIO8 multiplex + irq 0xe1 = 0x00 # GPIO7 data end device pnp 2e.008 off # WDT1 end device pnp 2e.108 on # GPIO0, GPIO1 irq 0xe0 = 0xff # GPIO0 i/o - irq 0xe1 = 0xff # GPIO0 data irq 0xe2 = 0xff # GPIO0 inversion - irq 0xe3 = 0xff # GPIO0 status irq 0xe4 = 0xff # GPIO0 multiplex irq 0xf0 = 0xff # GPIO1 i/o - irq 0xf1 = 0x28 # GPIO1 data - irq 0xf2 = 0x00 # GPIO1 inversion - irq 0xf3 = 0x00 # GPIO1 status irq 0xf4 = 0x08 # GPIO1 multiplex irq 0xf5 = 0xff # WDT1 control mode @@ -88,32 +70,16 @@ end device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff # GPIO2 i/o - irq 0xe1 = 0x90 # GPIO2 data - irq 0xe2 = 0x00 # GPIO2 inversion - irq 0xe3 = 0x00 # GPIO2 status - irq 0xe9 = 0x00 # GPIO2 multiplex end device pnp 2e.309 on # GPIO3 irq 0xe4 = 0x7f # GPIO3 i/o - irq 0xe5 = 0x76 # GPIO3 data - irq 0xe6 = 0x00 # GPIO3 inversion - irq 0xe7 = 0x00 # GPIO3 status - irq 0xea = 0x00 # GPIO3 multiplex - irq 0xfe = 0x00 # GPIO3/4 debounce + irq 0xe5 = 0x00 # GPIO3 data end device pnp 2e.409 on # GPIO4 irq 0xf0 = 0xff # GPIO4 i/o - irq 0xf1 = 0x7b # GPIO4 data - irq 0xf2 = 0x00 # GPIO4 inversion - irq 0xe8 = 0x00 # GPIO4 status - irq 0xee = 0x00 # GPIO4 multiplex end device pnp 2e.509 on # GPIO5 irq 0xf4 = 0xff # GPIO5 i/o - irq 0xf5 = 0xef # GPIO5 data - irq 0xf6 = 0x00 # GPIO5 inversion - irq 0xf7 = 0x00 # GPIO5 status - irq 0xeb = 0x00 # GPIO5 multiplex end device pnp 2e.609 on # GPIO6 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a Gerrit-Change-Number: 46020 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Comment and group super-i/o GPIO settings
by Nico Huber (Code Review) 29 Oct '20

29 Oct '20

Hello Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46019 to review the following change. Change subject: mb/asus/f2a85-m_pro: Comment and group super-i/o GPIO settings ...................................................................... mb/asus/f2a85-m_pro: Comment and group super-i/o GPIO settings Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 53 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46019/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index aa21321..aa2d52e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,71 +45,75 @@ end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - irq 0xe0 = 0x7f - irq 0xe1 = 0x10 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe4 = 0xff - irq 0xe5 = 0xff - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xec = 0x00 - irq 0xed = 0xff - irq 0xf4 = 0xff - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 - irq 0xf8 = 0x00 + irq 0xf4 = 0xff # GPIO6 i/o + irq 0xf5 = 0xff # GPIO6 data + irq 0xf6 = 0x00 # GPIO6 inversion + irq 0xf7 = 0x00 # GPIO6 status + irq 0xf8 = 0x00 # GPIO6 multiplex + + irq 0xe0 = 0x7f # GPIO7 i/o + irq 0xe1 = 0x10 # GPIO7 data + irq 0xe2 = 0x00 # GPIO7 inversion + irq 0xe3 = 0x00 # GPIO7 status + irq 0xec = 0x00 # GPIO7 multiplex + + irq 0xe4 = 0xff # GPIO8 i/o + irq 0xe5 = 0xff # GPIO8 data + irq 0xe6 = 0xff # GPIO8 inversion + irq 0xe7 = 0xff # GPIO8 status + irq 0xed = 0xff # GPIO8 multiplex end device pnp 2e.008 off # WDT1 end device pnp 2e.108 on # GPIO0, GPIO1 - irq 0xe0 = 0xff - irq 0xe1 = 0xff - irq 0xe2 = 0xff - irq 0xe3 = 0xff - irq 0xe4 = 0xff - irq 0xf0 = 0xff - irq 0xf1 = 0x28 - irq 0xf2 = 0x00 - irq 0xf3 = 0x00 - irq 0xf4 = 0x08 - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0xff + irq 0xe0 = 0xff # GPIO0 i/o + irq 0xe1 = 0xff # GPIO0 data + irq 0xe2 = 0xff # GPIO0 inversion + irq 0xe3 = 0xff # GPIO0 status + irq 0xe4 = 0xff # GPIO0 multiplex + + irq 0xf0 = 0xff # GPIO1 i/o + irq 0xf1 = 0x28 # GPIO1 data + irq 0xf2 = 0x00 # GPIO1 inversion + irq 0xf3 = 0x00 # GPIO1 status + irq 0xf4 = 0x08 # GPIO1 multiplex + + irq 0xf5 = 0xff # WDT1 control mode + irq 0xf6 = 0x00 # WDT1 counter + irq 0xf7 = 0xff # WDT1 control / status end device pnp 2e.009 off # GPIO8 end device pnp 2e.109 on # GPIO1 end device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff - irq 0xe1 = 0x90 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe9 = 0x00 + irq 0xe0 = 0xff # GPIO2 i/o + irq 0xe1 = 0x90 # GPIO2 data + irq 0xe2 = 0x00 # GPIO2 inversion + irq 0xe3 = 0x00 # GPIO2 status + irq 0xe9 = 0x00 # GPIO2 multiplex end device pnp 2e.309 on # GPIO3 - irq 0xe4 = 0x7f - irq 0xe5 = 0x76 - irq 0xe6 = 0x00 - irq 0xe7 = 0x00 - irq 0xea = 0x00 - irq 0xfe = 0x00 + irq 0xe4 = 0x7f # GPIO3 i/o + irq 0xe5 = 0x76 # GPIO3 data + irq 0xe6 = 0x00 # GPIO3 inversion + irq 0xe7 = 0x00 # GPIO3 status + irq 0xea = 0x00 # GPIO3 multiplex + irq 0xfe = 0x00 # GPIO3/4 debounce end device pnp 2e.409 on # GPIO4 - irq 0xe8 = 0x00 - irq 0xf0 = 0xff - irq 0xf1 = 0x7b - irq 0xf2 = 0x00 - irq 0xee = 0x00 + irq 0xf0 = 0xff # GPIO4 i/o + irq 0xf1 = 0x7b # GPIO4 data + irq 0xf2 = 0x00 # GPIO4 inversion + irq 0xe8 = 0x00 # GPIO4 status + irq 0xee = 0x00 # GPIO4 multiplex end device pnp 2e.509 on # GPIO5 - irq 0xeb = 0x00 - irq 0xf4 = 0xff - irq 0xf5 = 0xef - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 + irq 0xf4 = 0xff # GPIO5 i/o + irq 0xf5 = 0xef # GPIO5 data + irq 0xf6 = 0x00 # GPIO5 inversion + irq 0xf7 = 0x00 # GPIO5 status + irq 0xeb = 0x00 # GPIO5 multiplex end device pnp 2e.609 on # GPIO6 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f Gerrit-Change-Number: 46019 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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