coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 28 Oct '20

28 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... soc/intel: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 13 files changed, 34 insertions(+), 174 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 39a4265..9fab277 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -23,7 +23,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -62,25 +61,6 @@ wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 79fab1a..64889e5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c +bootblock-y += ../common/block/cpu/pm_timer_emulation.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index aaf6258..748f76a 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -234,8 +234,6 @@ void pch_log_state(void); -void enable_pm_timer_emulation(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e0de93e..6e96b57 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -178,24 +178,6 @@ return prev_sleep_state; } -void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static int rtc_failed(uint32_t gen_pmcon1) { return !!(gen_pmcon1 & RPS); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 20da942..61b1989 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -14,7 +14,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/systemagent.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> @@ -58,29 +57,6 @@ wrmsr(MSR_POWER_CTL, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -135,7 +111,6 @@ set_aesni_lock(); - /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index deddb67..7692076 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -11,3 +11,4 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c +ramstage-$(CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION) += pm_timer_emulation.c diff --git a/src/soc/intel/common/block/cpu/pm_timer_emulation.c b/src/soc/intel/common/block/cpu/pm_timer_emulation.c new file mode 100644 index 0000000..8f56da5 --- /dev/null +++ b/src/soc/intel/common/block/cpu/pm_timer_emulation.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <soc/iomap.h> +#include <soc/pm.h> + +void enable_pm_timer_emulation(void) +{ + msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + + /* + * The derived frequency is calculated as follows: + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. + */ + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index d2b00ef..4dfbef4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -156,4 +156,10 @@ /* Get a supported PRMRR size in bytes with respect to users choice */ int get_valid_prmrr_size(void); +/* + * Enable the emulated ACPI timer in case it's not available or to allow + * disabling the PM ACPI timer (PM1_TMR) for power saving. + */ +void enable_pm_timer_emulation(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 720a295..d0fa019 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -17,7 +17,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -56,25 +55,6 @@ wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index ea2b357..1734ba6 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -17,7 +17,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -56,25 +55,6 @@ wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -127,7 +107,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 312fc7d..6518945 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -17,7 +17,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -56,25 +55,6 @@ wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1682503..6872c12 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,7 +21,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -96,29 +95,6 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows disabling of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d7234e7..36dfa1b 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -23,7 +23,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -62,25 +61,6 @@ wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 24 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 28 Oct '20

28 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… PS27, Line 53: Further, it must be disabled, if S0ix : is enabled. > Is this true for all SoCs supported by common/? I think it's true, but I'm not sure. it is true for all SoCs selecting PM_ACPI_TIMER_OPTIONAL -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Oct 2020 21:27:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/tiogapass/dsdt: Remove unnecessary comments
by Maxim Polyakov (Code Review) 28 Oct '20

28 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45767 ) Change subject: mb/ocp/tiogapass/dsdt: Remove unnecessary comments ...................................................................... mb/ocp/tiogapass/dsdt: Remove unnecessary comments Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45767/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 78475e0..677d2ca 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -11,12 +11,8 @@ 0x20110725 // OEM revision ) { - // platform ACPI tables #include "acpi/platform.asl" - - // global NVS and variables #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/45767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Gerrit-Change-Number: 45767 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Tim Wawrzynczak (Code Review) 28 Oct '20

28 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 27: (2 comments) https://review.coreboot.org/c/coreboot/+/45952/27//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45952/27//COMMIT_MSG@15 PS27, Line 15: SoCs, where the hardware PM Timer can be : disabled suggestion: "SoCs that support disabling the hardware PM timer" https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… PS27, Line 53: Further, it must be disabled, if S0ix : is enabled. Is this true for all SoCs supported by common/? I think it's true, but I'm not sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Oct 2020 20:36:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 28 Oct '20

28 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc… PS27, Line 54: is enabled. > Indeed. The TCO watchdog gets disabled. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Oct 2020 19:57:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ifdtool: add "reserved" regions
by Stefan Reinauer (Code Review) 28 Oct '20

28 Oct '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46822 ) Change subject: ifdtool: add "reserved" regions ...................................................................... ifdtool: add "reserved" regions This will let you at least dump / add these regions. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 --- M util/ifdtool/ifdtool.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46822/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 220c140..93f6f3f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1642,7 +1642,7 @@ " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" "\n"); } @@ -1732,6 +1732,12 @@ region_type = 3; else if (!strcasecmp("Platform", region_type_string)) region_type = 4; + else if (!strcasecmp("res1", region_type_string)) + region_type = 5; + else if (!strcasecmp("res2", region_type_string)) + region_type = 6; + else if (!strcasecmp("res3", region_type_string)) + region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; if (region_type == -1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 Gerrit-Change-Number: 46822 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Arthur Heymans (Code Review) 28 Oct '20

28 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 56: (1 comment) https://review.coreboot.org/c/coreboot/+/27369/56/src/soc/intel/common/base… File src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h: https://review.coreboot.org/c/coreboot/+/27369/56/src/soc/intel/common/base… PS56, Line 7: Caller should implement this function Then you generally don't want a weak function but just fail the build? -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 56 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Wed, 28 Oct 2020 19:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in gerrit-avatars[master]: Add my avatar
by Ricardo Ribalda (Code Review) 28 Oct '20

28 Oct '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/46897 ) Change subject: Add my avatar ...................................................................... Add my avatar Change-Id: Id3211b47bed66c098aecdf4361d6db012108faf0 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- A 1003185.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/97/46897/1 diff --git a/1003185.jpg b/1003185.jpg new file mode 100644 index 0000000..e0e67ca --- /dev/null +++ b/1003185.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/46897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: Id3211b47bed66c098aecdf4361d6db012108faf0 Gerrit-Change-Number: 46897 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/ocp/tiogapass/acpi: Move uncore from \_SB scope
by Maxim Polyakov (Code Review) 28 Oct '20

28 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45766 ) Change subject: mb/ocp/tiogapass/acpi: Move uncore from \_SB scope ...................................................................... mb/ocp/tiogapass/acpi: Move uncore from \_SB scope Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45766/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251..78475e0 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -18,9 +18,5 @@ #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> - - // Xeon-SP ACPI tables - Scope (\_SB) { - #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> - } + #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/45766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Gerrit-Change-Number: 45766 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/google/zork: Revert temp acpi backlight fix
by Josie Nordrum (Code Review) 28 Oct '20

28 Oct '20

Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46823 ) Change subject: mb/google/zork: Revert temp acpi backlight fix ...................................................................... mb/google/zork: Revert temp acpi backlight fix Remove code to turn on backlight during ACPI mode because backlight has been properly enabled in ACPI. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum(a)google.com> Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6 --- M src/mainboard/google/zork/smihandler.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46823/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 6ef2704..1c26d45 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -34,10 +34,5 @@ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); - /* Temporary fix - Needs to go into ACPI instead */ - /* Turn on the backlight when we go to ACPI mode */ - if (apmc == APM_CNT_ACPI_ENABLE) - gpio_set(GPIO_85, 0); - return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6 Gerrit-Change-Number: 46823 Gerrit-PatchSet: 1 Gerrit-Owner: Josie Nordrum <josienordrum(a)google.com> Gerrit-MessageType: newchange

4 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020