coreboot-gerrit October 2020

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Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 28 Oct '20

28 Oct '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/46441/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46441/7//COMMIT_MSG@8 PS7, Line 8: : We are implementing a mechanism in coreboot to update CSME firmware, : this requires coreboot to be able to read CSME region. > The current mechanism is not relying on determining the version by reading CSE region, however we ar […] Done https://review.coreboot.org/c/coreboot/+/46441/7//COMMIT_MSG@13 PS7, Line 13: This patch will enable read access to CSME region when locking. > A check in ifdtool to see if there is already a non-default region access applied can be implemented […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 10 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Usha P <usha.p(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Oct 2020 11:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Angel Pons (Code Review) 28 Oct '20

28 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 28 Oct 2020 11:27:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/common/acpi: convert irqlinks.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 28 Oct '20

28 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45277 ) Change subject: sb/common/acpi: convert irqlinks.asl to ASL+ Syntax ...................................................................... sb/common/acpi: convert irqlinks.asl to ASL+ Syntax Change-Id: I92b49c56c52216906a0349e09ca3cc96bca59196 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/acpi/irqlinks.asl 1 file changed, 48 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45277/1 diff --git a/src/southbridge/intel/common/acpi/irqlinks.asl b/src/southbridge/intel/common/acpi/irqlinks.asl index 3f3386d..7d66107 100644 --- a/src/southbridge/intel/common/acpi/irqlinks.asl +++ b/src/southbridge/intel/common/acpi/irqlinks.asl @@ -8,7 +8,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link @@ -28,10 +28,10 @@ CreateWordField(RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link @@ -87,10 +87,10 @@ CreateWordField(RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = (One << (PRTB & 0x0F)) Return (RTLB) } @@ -103,14 +103,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0, PRTB } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link @@ -146,10 +146,10 @@ CreateWordField(RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = (One << (PRTC & 0x0F)) Return (RTLC) } @@ -162,14 +162,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link @@ -205,10 +205,10 @@ CreateWordField(RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = (One << (PRTD & 0x0F)) Return (RTLD) } @@ -221,14 +221,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link @@ -264,10 +264,10 @@ CreateWordField(RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = (One << (PRTE & 0x0F)) Return (RTLE) } @@ -280,14 +280,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link @@ -323,10 +323,10 @@ CreateWordField(RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = (One << (PRTF & 0x0F)) Return (RTLF) } @@ -339,14 +339,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link @@ -382,10 +382,10 @@ CreateWordField(RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = (One << (PRTG & 0x0F)) Return (RTLG) } @@ -398,14 +398,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link @@ -441,10 +441,10 @@ CreateWordField(RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = Zero // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = (One << (PRTH & 0x0F)) Return (RTLH) } @@ -457,14 +457,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) -- To view, visit https://review.coreboot.org/c/coreboot/+/45277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92b49c56c52216906a0349e09ca3cc96bca59196 Gerrit-Change-Number: 45277 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params
by Maulik V Vaghela (Code Review) 28 Oct '20

28 Oct '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46872 ) Change subject: soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params ...................................................................... soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params JasperLake FSP provides an option to pass custom dll tuning upd values to be filled from coreboot. Coreboot was not using this parameters till now. With new EMMC devices being used, we may need to tune dll settings of EMMC. This patch enables developer or OEM to fill in custom dll tuning values via devicetree of respective board. Emmc tuning params customization through devicetree was already available for previous Intel SoCs, porting this feature for Jasperlake. BUG=None BRANCH=None TEST=Compilation succeeds and jslrvp boots fine with this patch Change-Id: I69940faa5ffd2c8f5532cea5c9b185cede1bf1b3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46872/1 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5e90530..624541a 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -125,6 +125,20 @@ /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; + /* Set if FSP should use HS400 DLL values from policy */ + uint8_t ScsEmmcUseCustomDlls; + /* Emmc Tx CMD Delay control register value */ + uint32_t ScsEmmcTxCmdDelayRegValue; + /* Emmc Tx DATA Delay control 1 register value */ + uint32_t ScsEmmcTxDataDelay1RegValue; + /* Emmc Tx DATA Delay control 2 register value */ + uint32_t ScsEmmcTxDataDelay2RegValue; + /* Emmc Rx CMD + DATA Delay control 1 register value */ + uint32_t ScsEmmcRxCmdDataDelay1RegValue; + /* Emmc Rx CMD + DATA Delay control 2 register value */ + uint32_t ScsEmmcRxCmdDataDelay2RegValue; + /* Emmc Rx Strobe Delay control register value */ + uint32_t ScsEmmcRxStrobeDelayRegValue; /* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index db27234..67aa6db 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -199,8 +199,25 @@ /* eMMC configuration */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); params->ScsEmmcEnabled = is_dev_enabled(dev); - if (params->ScsEmmcEnabled) + if (params->ScsEmmcEnabled) { params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->EmmcUseCustomDlls = config->ScsEmmcUseCustomDlls; + /* Emmc custom Dll tuning parameters */ + if (config->ScsEmmcUseCustomDlls) { + params->EmmcTxCmdDelayRegValue = \ + config->ScsEmmcTxCmdDelayRegValue; + params->EmmcTxDataDelay1RegValue = \ + config->ScsEmmcTxDataDelay1RegValue; + params->EmmcTxDataDelay2RegValue = \ + config->ScsEmmcTxDataDelay2RegValue; + params->EmmcRxCmdDataDelay1RegValue = \ + config->ScsEmmcRxCmdDataDelay1RegValue; + params->EmmcRxCmdDataDelay2RegValue = \ + config->ScsEmmcRxCmdDataDelay2RegValue; + params->EmmcRxStrobeDelayRegValue = \ + config->ScsEmmcRxStrobeDelayRegValue; + } + } /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); -- To view, visit https://review.coreboot.org/c/coreboot/+/46872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69940faa5ffd2c8f5532cea5c9b185cede1bf1b3 Gerrit-Change-Number: 46872 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Patrick Georgi (Code Review) 28 Oct '20

28 Oct '20

Hello build bot (Jenkins), Greg Edelston, Dossym Nurmukhanov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45208 to look at the new patch set (#4). Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... console: Allow VPD to disable an otherwise enabled coreboot console With VPD compiled in, no output is sent to the serial console if VPD_RO has an entry `disable_serial` set to 1. This allows using an image for both deployment and testing scenarios with only the VPD entry modified to toggle (the typically slow) serial console. By looking for a positive value in an as-yet undefined VPD entry the change is transparent: the behavior doesn't change at all unless the entry is added. BUG=b:151346403 BRANCH=none TEST=Taking a Chrome OS config for google/eve, it behaves as expected with no entry present and both entry states (1, 0 - everything else falls back to 0) with negligible performance loss. Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/console/init.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45208/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/mrc_cache: Fix size comparison in mrc_cache update
by Tim Wawrzynczak (Code Review) 28 Oct '20

28 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46824 ) Change subject: drivers/mrc_cache: Fix size comparison in mrc_cache update ...................................................................... drivers/mrc_cache: Fix size comparison in mrc_cache update `mrc_cache_needs_update` is comparing the "new size" of the MRC data (minus metadata size) to the size including the metadata, which causes the driver to think the data has changed, and so it will rewrite the MRC cache on every boot. This patch removes the metadata size from the comparison. BUG=b:171513942 BRANCH=volteer TEST=1) Memory training data gets written the on a boot where the data was wiped out. 2) Memory training data does not get written back on every subsequent boot. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51 --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46824/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3b98dba..eb43123 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -337,10 +337,10 @@ const void *new_data, size_t new_data_size) { void *mapping, *data_mapping; - size_t size = region_device_sz(rdev); + size_t old_data_size = region_device_sz(rdev) - sizeof(struct mrc_metadata); bool need_update = false; - if (new_data_size != size) + if (new_data_size != old_data_size) return true; mapping = rdev_mmap_full(rdev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51 Gerrit-Change-Number: 46824 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/nightfury: Set internal pull-down for GPP_D19
by shkim (Code Review) 28 Oct '20

28 Oct '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46816 to review the following change. Change subject: mb/google/nightfury: Set internal pull-down for GPP_D19 ...................................................................... mb/google/nightfury: Set internal pull-down for GPP_D19 Add internal pull-down for GPP_D19 to improve DMIC noise issue on nightfury. BUG=b:171669255 BRANCH=firmware-hatch-12672.B TEST=Built and checked GPP_D19 voltage after booting Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/nightfury/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46816/1 diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 951723e..eb6217d 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -37,6 +37,8 @@ /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, DN_20K, DEEP, NF1), /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ PAD_NC(GPP_E4, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/46816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Gerrit-Change-Number: 46816 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Patrick Georgi (Code Review) 28 Oct '20

28 Oct '20

Hello build bot (Jenkins), Greg Edelston, Dossym Nurmukhanov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45208 to look at the new patch set (#3). Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... console: Allow VPD to disable an otherwise enabled coreboot console With VPD compiled in, no output is sent to the serial console if VPD_RO has an entry `disable_serial` set to 1. This allows using an image for both deployment and testing scenarios with only the VPD entry modified to toggle (the typically slow) serial console. By looking for a positive value in an as-yet undefined VPD entry the change is transparent: the behavior doesn't change at all unless the entry is added. BUG=b:151346403 BRANCH=none TEST=Taking a Chrome OS config for google/eve, it behaves as expected with no entry present and both entry states (1, 0 - everything else falls back to 0) with negligible performance loss. Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/console/init.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45208/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/intel/xeon_sp: Override cache error correction type and cache...
by Morgan Jang (Code Review) 28 Oct '20

28 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46119 ) Change subject: src/soc/intel/xeon_sp: Override cache error correction type and cache sram type in SMBIOS type 7 ...................................................................... src/soc/intel/xeon_sp: Override cache error correction type and cache sram type in SMBIOS type 7 TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/ramstage.c 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46119/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 3bbf6b7..40dafb5 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c new file mode 100644 index 0000000..d4334da --- /dev/null +++ b/src/soc/intel/xeon_sp/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> + +unsigned int smbios_cache_error_correction_type(void) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Gerrit-Change-Number: 46119 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT
by Morgan Jang (Code Review) 28 Oct '20

28 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46833 ) Change subject: soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT ...................................................................... soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46833/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 8820517..d60684b 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -53,8 +53,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE); + fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } void uncore_inject_dsdt(const struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/46833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Gerrit-Change-Number: 46833 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020