Hello Paul Menzel,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46015
to review the following change.
Change subject: mb/asus/f2a85-m_pro: Enable GPIO0 on the super-i/o
......................................................................
mb/asus/f2a85-m_pro: Enable GPIO0 on the super-i/o
It was enabled by the vendor firmware.
Also drop spurious `io 0x60 = 0x00` setting. It's the default anyway
and the resource is kept disabled (it's controlled by the virtual
LDN 2e.008).
Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46015/1
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
index 3f9135c..aa21321 100644
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
@@ -61,8 +61,9 @@
irq 0xf7 = 0x00
irq 0xf8 = 0x00
end
- device pnp 2e.8 off # WDT1, GPIO0, GPIO1
- io 0x60 = 0x00
+ device pnp 2e.008 off # WDT1
+ end
+ device pnp 2e.108 on # GPIO0, GPIO1
irq 0xe0 = 0xff
irq 0xe1 = 0xff
irq 0xe2 = 0xff
--
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Gerrit-Branch: master
Gerrit-Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a
Gerrit-Change-Number: 46015
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
Hello Felix Singer,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46849
to review the following change.
Change subject: payloads/filo: Set stable tag to something that builds
......................................................................
payloads/filo: Set stable tag to something that builds
Also rename the prompt to "tested" to make it more obvious that there
is no really stable version.
Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M payloads/external/FILO/Kconfig
M payloads/external/FILO/Makefile
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46849/1
diff --git a/payloads/external/FILO/Kconfig b/payloads/external/FILO/Kconfig
index 94d5e18..1cf171d 100644
--- a/payloads/external/FILO/Kconfig
+++ b/payloads/external/FILO/Kconfig
@@ -5,9 +5,9 @@
default FILO_STABLE
config FILO_STABLE
- bool "0.6.0"
+ bool "tested"
help
- Stable FILO version
+ Tested FILO version
config FILO_MASTER
bool "HEAD"
diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile
index a89ea2a..6175cfe 100644
--- a/payloads/external/FILO/Makefile
+++ b/payloads/external/FILO/Makefile
@@ -1,6 +1,6 @@
TAG-$(CONFIG_FILO_MASTER)=origin/master
NAME-$(CONFIG_FILO_MASTER)=MASTER
-TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad
+TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412
NAME-$(CONFIG_FILO_STABLE)=STABLE
project_git_repo=https://review.coreboot.org/filo.git
--
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Gerrit-Change-Number: 46849
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Gerrit-MessageType: newchange
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46909 )
Change subject: soc/intel/broadwell/cpu/acpi.c: Clean up C-state generation
......................................................................
soc/intel/broadwell/cpu/acpi.c: Clean up C-state generation
Do not use `memcpy()` to initialize a single array element, and use the
ARRAY_SIZE macro to specify the for-loop max instead of a magic number.
Change-Id: Ifdf3d6969eaa23c0aab058bbcc6e607bcf3c5736
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/broadwell/cpu/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/46909/1
diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c
index 56a4e99..a12fd0e 100644
--- a/src/soc/intel/broadwell/cpu/acpi.c
+++ b/src/soc/intel/broadwell/cpu/acpi.c
@@ -210,8 +210,8 @@
else
set = cstate_set_non_s0ix;
- for (i = 0; i < 3; i++) {
- memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
+ for (i = 0; i < ARRAY_SIZE(map); i++) {
+ map[i] = cstate_map[set[i]];
map[i].ctype = i + 1;
}
--
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Gerrit-Change-Number: 46909
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45952
to look at the new patch set (#28).
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
Currently, the ACPI PM timer state gets set in devicetree by the option
PmTimerDisabled. However, it is not board design dependent. Thus, add a
user-selectable Kconfig option.
Disabling the PM ACPI Timer is only valid when PM Timer emulation is
supported and is only possible, when there is a hardware PM Timer (APL
does not have one for example). SoCs, where the hardware PM Timer can be
disabled must select `PM_ACPI_TIMER_OPTIONAL`.
This new Kconfig gets used in the follow-up commits of this series.
Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/pmc/Kconfig
1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/28
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 )
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45952/27//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45952/27//COMMIT_MSG@15
PS27, Line 15: SoCs, where the hardware PM Timer can be
: disabled
> suggestion: "SoCs that support disabling the hardware PM timer"
Ack
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 )
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc…
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/45952/27/src/soc/intel/common/bloc…
PS27, Line 53: Further, it must be disabled, if S0ix
: is enabled.
> it is true for all SoCs selecting PM_ACPI_TIMER_OPTIONAL
Ack
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Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 )
Change subject: src/arch/x86:Add support for low power idle table
......................................................................
Patch Set 4:
I started to work on this today, was blocked by few other high priority issues. Will try address all the comments and come back if i have any doubts while implementing this.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 )
Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
......................................................................
Patch Set 19: Code-Review+2
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