Deepika Punyamurtula has uploaded a new patch set (#12) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 )
Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
......................................................................
UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
Configure board specific DPTF parameters for delbin
BUG=b:168958222
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2
---
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
1 file changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/12
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Gerrit-MessageType: newpatchset
Deepika Punyamurtula has uploaded a new patch set (#11) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 )
Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
......................................................................
UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
Configure board specific DPTF parameters for delbin
BUG=b:168958222
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2
---
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
1 file changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/11
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Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 )
Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
......................................................................
Patch Set 10:
(1 comment)
Thank you Frank for the update. Please help address one more about PL4 value.
https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt…
File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt…
PS10, Line 8: .tdp_pl2_override = 51,
Can you also please add .tdp_pl4 = 105, ?
If pl4 = 105 in your case
I have seen that without this it picks up a value of 121 for PL4.
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Gerrit-Comment-Date: Thu, 29 Oct 2020 16:39:10 +0000
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Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46842
to look at the new patch set (#6).
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Correcting the sequence by moving some of the reserved gpio within
community (that's also same in pinctrl driver), helps with the issue.
Also verified offset of hostown pad register for all communities.
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/jasperlake/gpio.c
1 file changed, 8 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/6
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 )
Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
PS7, Line 39: PAD_CFG_GPO(GPP_H17, 1, PLTRST),
> Now with Power Resource object added to USB device, we don't need to do this split initialization in […]
Learn from you, Karthik. Thanks.
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 )
Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/boten/variant.c:
https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded…
PS9, Line 39: power_off_lte_module(slp_typ);
Since we have register "reset_off_delay_ms" = "10" in overridetree.cb now, do we still need this logic here?
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