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Change in coreboot[master]: mb/google/jecht: Prepare devicetree for PCH split
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46703 ) Change subject: mb/google/jecht: Prepare devicetree for PCH split ...................................................................... mb/google/jecht: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, TODO. Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/jecht/devicetree.cb 1 file changed, 94 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46703/1 diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index c4707e0..e550822 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,27 +9,6 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -38,78 +17,102 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 +# chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal +# end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86 Gerrit-Change-Number: 46703 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pei_data: Rename and retype fields
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47003 ) Change subject: soc/intel/broadwell/pei_data: Rename and retype fields ...................................................................... soc/intel/broadwell/pei_data: Rename and retype fields This is to reduce the differences with Haswell MRC. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6c33e7b897316bb34cbefccf79fc3065f69e7585 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pei_data.h M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/refcode.c 3 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47003/1 diff --git a/src/soc/intel/broadwell/pei_data.h b/src/soc/intel/broadwell/pei_data.h index 67d73d9..875f697 100644 --- a/src/soc/intel/broadwell/pei_data.h +++ b/src/soc/intel/broadwell/pei_data.h @@ -234,15 +234,15 @@ uint8_t dqs_map[2][8]; /* Data read from flash and passed into MRC */ - const void *saved_data; - int saved_data_size; + const void *mrc_input; + unsigned int mrc_input_len; /* Disable use of saved data (can be set by mainboard) */ int disable_saved_data; /* Data from MRC that should be saved to flash */ - void *data_to_save; - int data_to_save_size; + void *mrc_output; + unsigned int mrc_output_len; struct pei_memory_info meminfo; } __packed; diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 5339daa..a9b0d16 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -21,15 +21,15 @@ void save_mrc_data(struct pei_data *pei_data) { - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->mrc_output, + pei_data->mrc_output_len); - if (pei_data->data_to_save == NULL || !pei_data->data_to_save_size) + if (pei_data->mrc_output == NULL || !pei_data->mrc_output_len) return; /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->data_to_save, - pei_data->data_to_save_size); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, + pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) @@ -37,21 +37,21 @@ size_t mrc_size; /* Preset just in case there is an error */ - pei_data->saved_data = NULL; - pei_data->saved_data_size = 0; + pei_data->mrc_input = NULL; + pei_data->mrc_input_len = 0; - pei_data->saved_data = + pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &mrc_size); - if (!pei_data->saved_data) { + if (!pei_data->mrc_input) { printk(BIOS_DEBUG, "No MRC cache found.\n"); return; } - pei_data->saved_data_size = mrc_size; + pei_data->mrc_input_len = mrc_size; - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->saved_data, - pei_data->saved_data_size); + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->mrc_input, + pei_data->mrc_input_len); } static const char *const ecc_decoder[] = { @@ -126,7 +126,7 @@ } /* If MRC data is not found, we cannot continue S3 resume */ - if (pei_data->boot_mode == ACPI_S3 && !pei_data->saved_data) { + if (pei_data->boot_mode == ACPI_S3 && !pei_data->mrc_input) { post_code(POST_RESUME_FAILURE); printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); system_reset(); @@ -138,8 +138,8 @@ */ if (pei_data->disable_saved_data) { printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); - pei_data->saved_data = NULL; - pei_data->saved_data_size = 0; + pei_data->mrc_input = NULL; + pei_data->mrc_input_len = 0; } /* Determine if mrc.bin is in the cbfs. */ diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index b3058d3..4ec1fc2 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -64,7 +64,7 @@ broadwell_fill_pei_data(&pei_data); pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0; - pei_data.saved_data = (void *) &dummy; + pei_data.mrc_input = (void *)&dummy; entry = load_reference_code(); if (entry == NULL) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c33e7b897316bb34cbefccf79fc3065f69e7585 Gerrit-Change-Number: 47003 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/pei_data.h: Rename `over_current_pin` fields
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47002 ) Change subject: nb/intel/haswell/pei_data.h: Rename `over_current_pin` fields ...................................................................... nb/intel/haswell/pei_data.h: Rename `over_current_pin` fields For consistency with Broadwell pei_data, rename them to `oc_pin`. Change-Id: I7c2ee59630891cfd927583fef34416579b844f67 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pei_data.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47002/1 diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 6bdfde4..d555b41 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -29,13 +29,13 @@ struct usb2_port_setting { uint16_t length; uint8_t enable; - uint8_t over_current_pin; + uint8_t oc_pin; uint8_t location; } __packed; struct usb3_port_setting { uint8_t enable; - uint8_t over_current_pin; + uint8_t oc_pin; } __packed; struct pei_data -- To view, visit https://review.coreboot.org/c/coreboot/+/47002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c2ee59630891cfd927583fef34416579b844f67 Gerrit-Change-Number: 47002 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Inline single-use functions
by Angel Pons (Code Review) 29 Oct '20

29 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46989 ) Change subject: soc/intel/broadwell: Inline single-use functions ...................................................................... soc/intel/broadwell: Inline single-use functions These functions are only used in a single place, so inline them. Change-Id: Iec47a7a1fd835080f6641afcbcfddf25e1d5f46a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/northbridge.c 3 files changed, 7 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46989/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3a9ac13..300b7e7 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -74,8 +74,13 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); + const struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index 09de2ef..2ce068a 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -155,9 +155,6 @@ /* System Agent identification */ u8 systemagent_revision(void); -uintptr_t sa_get_tolud_base(void); -uintptr_t sa_get_gsm_base(void); - void systemagent_early_init(void); u32 igd_get_reg_em4(void); diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 4e75721..2163a14 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -22,20 +22,6 @@ return pci_read_config8(sa_dev, PCI_REVISION_ID); } -uintptr_t sa_get_tolud_base(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(sa_dev, TOLUD) & ~1; -} - -uintptr_t sa_get_gsm_base(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(sa_dev, BGSM) & ~1; -} - static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/46989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec47a7a1fd835080f6641afcbcfddf25e1d5f46a Gerrit-Change-Number: 46989 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Michael Niewöhner (Code Review) 29 Oct '20

29 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 ) Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... Patch Set 20: Subrata, could you have a look at this, please? -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Oct 2020 21:43:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/acpi: add defines for CPPC versions 1-3
by Michael Niewöhner (Code Review) 29 Oct '20

29 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46986 ) Change subject: include/acpi: add defines for CPPC versions 1-3 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd Gerrit-Change-Number: 46986 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Oct 2020 21:42:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 29 Oct '20

29 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#30). Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/block/acpi: add code for CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. This way all SoCs using the common code get the CPPC entries added. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 30 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 29 Oct '20

29 Oct '20

Hello Felix Singer, Matt Delco, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46465 to look at the new patch set (#19). Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/soc/intel/skylake/acpi.c 2 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46465/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… PS14, Line 39: [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), : [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), : [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000) > nit: this is easier to read if each column lines up Done https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… PS14, Line 68: > nit: extra blank line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 15 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 21:29:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

Deepika Punyamurtula has uploaded a new patch set (#15) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 15 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020