coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/broadwell: Relocate PCH finalisation code
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46709 ) Change subject: soc/intel/broadwell: Relocate PCH finalisation code ...................................................................... soc/intel/broadwell: Relocate PCH finalisation code Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/pch/Makefile.inc A src/soc/intel/broadwell/pch/finalize.c 4 files changed, 56 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/46709/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 4196144..3dafc9d 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -4,15 +4,9 @@ #include <console/console.h> #include <console/post_codes.h> #include <device/pci_ops.h> -#include <reg_script.h> -#include <spi-generic.h> #include <soc/pci_devs.h> -#include <soc/lpc.h> -#include <soc/me.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <soc/pch.h> #include <soc/systemagent.h> -#include <southbridge/intel/common/spi.h> /* * 16.6 System Agent Configuration Locking @@ -55,48 +49,13 @@ MCHBAR32(0x6008) = MCHBAR32(0x6008); } -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) - /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif - - /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), - - /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), - - /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), - - /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), - - /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), - - /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - static void broadwell_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); broadwell_systemagent_finalize(); - spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); - - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - - /* Read+Write this R/WO register */ - RCBA32(LCAP) = RCBA32(LCAP); + broadwell_pch_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 59b5b18..cf27499 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -30,4 +30,6 @@ u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); +void broadwell_pch_finalize(void); + #endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 7e5c65a..1c19613 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += adsp.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += finalize.c ramstage-y += gpio.c romstage-y += gpio.c smm-y += gpio.c diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c new file mode 100644 index 0000000..37afded --- /dev/null +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <reg_script.h> +#include <spi-generic.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> +#include <soc/pch.h> +#include <soc/rcba.h> +#include <soc/spi.h> +#include <southbridge/intel/common/spi.h> + +const struct reg_script pch_finalize_script[] = { +#if !CONFIG(EM100PRO_SPI_CONSOLE) + /* Lock SPIBAR */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, + SPIBAR_HSFS_FLOCKDN), +#endif + + /* TC Lockdown */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), + + /* BIOS Interface Lockdown */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), + + /* Function Disable SUS Well Lockdown */ + REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), + + /* Global SMI Lock */ + REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), + + /* GEN_PMCON Lock */ + REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), + + /* PMSYNC */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), + + REG_SCRIPT_END +}; + +void broadwell_pch_finalize(void) +{ + spi_finalize_ops(); + reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); + + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + + /* Read+Write this R/WO register */ + RCBA32(LCAP) = RCBA32(LCAP); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b Gerrit-Change-Number: 46709 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/broadwell: Get rid of `cpu_is_ult`
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46708 ) Change subject: soc/intel/broadwell: Get rid of `cpu_is_ult` ...................................................................... soc/intel/broadwell: Get rid of `cpu_is_ult` It is only used in a single file, on two functions that already check whether coreboot is running on a Haswell or a Broadwell processor. Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/cpu.h 4 files changed, 4 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46708/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 75ef33f..ce1dd9c 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -19,8 +19,6 @@ ramstage-y += acpi.c ramstage-y += cpu.c -ramstage-y += cpu_info.c -smm-y += cpu_info.c ramstage-y += finalize.c ramstage-y += gma.c ramstage-y += memmap.c diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c deleted file mode 100644 index 8814a48..0000000 --- a/src/soc/intel/broadwell/cpu_info.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/systemagent.h> - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index c77f5c4..3889be3 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -364,6 +364,7 @@ /* Check for ULX GT1 or GT2 */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || devid == IGD_HASWELL_ULX_GT2; @@ -378,7 +379,7 @@ */ if (gpu_is_ulx && cdclk <= GT_CDCLK_337) cdclk = GT_CDCLK_337; - else if (gpu_is_ulx || cpu_is_ult() || + else if (gpu_is_ulx || cpu_is_ult || cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) cdclk = GT_CDCLK_450; else @@ -398,6 +399,7 @@ /* Check for ULX */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; /* Inform power controller of upcoming frequency change */ @@ -428,7 +430,7 @@ (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_450; else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || - (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) + (cpu_is_ult && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_540; else cdclk = GT_CDCLK_675; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 17eed4b..61ecf58 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -50,6 +50,4 @@ return cpuid_eax(1) & 0xf; } -int cpu_is_ult(void); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0 Gerrit-Change-Number: 46708 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/broadwell: Inline CPUID helpers
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46707 ) Change subject: soc/intel/broadwell: Inline CPUID helpers ...................................................................... soc/intel/broadwell: Inline CPUID helpers These functions are small and used in various stages. Inline them. Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/romstage/cpu.c 3 files changed, 12 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46707/1 diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c index 506b1a7..8814a48 100644 --- a/src/soc/intel/broadwell/cpu_info.c +++ b/src/soc/intel/broadwell/cpu_info.c @@ -5,16 +5,6 @@ #include <soc/msr.h> #include <soc/systemagent.h> -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - /* Dynamically determine if the part is ULT. */ int cpu_is_ult(void) { diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736..17eed4b 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -3,7 +3,9 @@ #ifndef _BROADWELL_CPU_H_ #define _BROADWELL_CPU_H_ +#include <arch/cpu.h> #include <device/device.h> +#include <stdint.h> /* CPU types */ #define HASWELL_FAMILY_ULT 0x40650 @@ -38,8 +40,16 @@ (IRTL_1024_NS >> 10)) /* CPU identification */ -u32 cpu_family_model(void); -u32 cpu_stepping(void); +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + int cpu_is_ult(void); #endif diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index 7364876..c9f70a8 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -7,11 +7,6 @@ #include <soc/msr.h> #include <soc/romstage.h> -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - void set_max_freq(void) { msr_t msr, perf_ctl, platform_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/46707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f Gerrit-Change-Number: 46707 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel/broadwell: Move PCH code into pch subdir
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46706 ) Change subject: soc/intel/broadwell: Move PCH code into pch subdir ...................................................................... soc/intel/broadwell: Move PCH code into pch subdir Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc A src/soc/intel/broadwell/pch/Makefile.inc R src/soc/intel/broadwell/pch/adsp.c R src/soc/intel/broadwell/pch/bootblock.c R src/soc/intel/broadwell/pch/early_pch.c R src/soc/intel/broadwell/pch/ehci.c R src/soc/intel/broadwell/pch/elog.c R src/soc/intel/broadwell/pch/fadt.c R src/soc/intel/broadwell/pch/gpio.c R src/soc/intel/broadwell/pch/hda.c R src/soc/intel/broadwell/pch/iobp.c R src/soc/intel/broadwell/pch/lpc.c R src/soc/intel/broadwell/pch/me.c R src/soc/intel/broadwell/pch/me_status.c R src/soc/intel/broadwell/pch/pch.c R src/soc/intel/broadwell/pch/pcie.c R src/soc/intel/broadwell/pch/pmutil.c R src/soc/intel/broadwell/pch/power_state.c R src/soc/intel/broadwell/pch/sata.c R src/soc/intel/broadwell/pch/serialio.c R src/soc/intel/broadwell/pch/smbus.c R src/soc/intel/broadwell/pch/smi.c R src/soc/intel/broadwell/pch/smihandler.c R src/soc/intel/broadwell/pch/uart.c R src/soc/intel/broadwell/pch/usb_debug.c R src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/romstage/Makefile.inc 27 files changed, 40 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/46706/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index e24b949..75ef33f 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,52 +9,28 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +subdirs-y += pch + bootblock-y += bootblock/cpu.c -bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c -ramstage-y += adsp.c ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c -ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c -ramstage-y += gpio.c -romstage-y += gpio.c -smm-y += gpio.c -ramstage-y += hda.c ramstage-y += gma.c -ramstage-y += iobp.c -romstage-y += iobp.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c -ramstage-y += pch.c -romstage-y += pch.c -ramstage-y += pcie.c ramstage-y += pei_data.c romstage-y += pei_data.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += sata.c -ramstage-y += serialio.c -ramstage-y += smbus.c -ramstage-y += smi.c -smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c @@ -63,17 +39,9 @@ smm-y += tsc_freq.c postcar-y += tsc_freq.c verstage-y += tsc_freq.c -bootblock-y += usb_debug.c -romstage-y += usb_debug.c -ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc new file mode 100644 index 0000000..7e5c65a --- /dev/null +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -0,0 +1,38 @@ +bootblock-y += bootblock.c + +ramstage-y += adsp.c +romstage-y += early_pch.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += gpio.c +romstage-y += gpio.c +smm-y += gpio.c +ramstage-y += hda.c +ramstage-y += iobp.c +romstage-y += iobp.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += me.c +ramstage-y += me_status.c +romstage-y += me_status.c +ramstage-y += pch.c +romstage-y += pch.c +ramstage-y += pcie.c +ramstage-y += pmutil.c +romstage-y += pmutil.c +smm-y += pmutil.c +verstage-y += pmutil.c +romstage-y += power_state.c +ramstage-y += sata.c +ramstage-y += serialio.c +ramstage-y += smbus.c +ramstage-y += smi.c +smm-y += smihandler.c +romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c +ramstage-y += ehci.c +ramstage-y += xhci.c +smm-y += xhci.c + +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/pch/adsp.c similarity index 100% rename from src/soc/intel/broadwell/adsp.c rename to src/soc/intel/broadwell/pch/adsp.c diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/pch/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/pch.c rename to src/soc/intel/broadwell/pch/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/pch/early_pch.c similarity index 100% rename from src/soc/intel/broadwell/romstage/pch.c rename to src/soc/intel/broadwell/pch/early_pch.c diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/pch/ehci.c similarity index 100% rename from src/soc/intel/broadwell/ehci.c rename to src/soc/intel/broadwell/pch/ehci.c diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/pch/elog.c similarity index 100% rename from src/soc/intel/broadwell/elog.c rename to src/soc/intel/broadwell/pch/elog.c diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/pch/fadt.c similarity index 100% rename from src/soc/intel/broadwell/fadt.c rename to src/soc/intel/broadwell/pch/fadt.c diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/pch/gpio.c similarity index 100% rename from src/soc/intel/broadwell/gpio.c rename to src/soc/intel/broadwell/pch/gpio.c diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/pch/hda.c similarity index 100% rename from src/soc/intel/broadwell/hda.c rename to src/soc/intel/broadwell/pch/hda.c diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/pch/iobp.c similarity index 100% rename from src/soc/intel/broadwell/iobp.c rename to src/soc/intel/broadwell/pch/iobp.c diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/pch/lpc.c similarity index 100% rename from src/soc/intel/broadwell/lpc.c rename to src/soc/intel/broadwell/pch/lpc.c diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/pch/me.c similarity index 100% rename from src/soc/intel/broadwell/me.c rename to src/soc/intel/broadwell/pch/me.c diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/pch/me_status.c similarity index 100% rename from src/soc/intel/broadwell/me_status.c rename to src/soc/intel/broadwell/pch/me_status.c diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch/pch.c similarity index 100% rename from src/soc/intel/broadwell/pch.c rename to src/soc/intel/broadwell/pch/pch.c diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pch/pcie.c similarity index 100% rename from src/soc/intel/broadwell/pcie.c rename to src/soc/intel/broadwell/pch/pcie.c diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c similarity index 100% rename from src/soc/intel/broadwell/pmutil.c rename to src/soc/intel/broadwell/pch/pmutil.c diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/pch/power_state.c similarity index 100% rename from src/soc/intel/broadwell/romstage/power_state.c rename to src/soc/intel/broadwell/pch/power_state.c diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/pch/sata.c similarity index 100% rename from src/soc/intel/broadwell/sata.c rename to src/soc/intel/broadwell/pch/sata.c diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/pch/serialio.c similarity index 100% rename from src/soc/intel/broadwell/serialio.c rename to src/soc/intel/broadwell/pch/serialio.c diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/pch/smbus.c similarity index 100% rename from src/soc/intel/broadwell/smbus.c rename to src/soc/intel/broadwell/pch/smbus.c diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/pch/smi.c similarity index 100% rename from src/soc/intel/broadwell/smi.c rename to src/soc/intel/broadwell/pch/smi.c diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/smihandler.c rename to src/soc/intel/broadwell/pch/smihandler.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/pch/uart.c similarity index 100% rename from src/soc/intel/broadwell/romstage/uart.c rename to src/soc/intel/broadwell/pch/uart.c diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/usb_debug.c rename to src/soc/intel/broadwell/pch/usb_debug.c diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/pch/xhci.c similarity index 100% rename from src/soc/intel/broadwell/xhci.c rename to src/soc/intel/broadwell/pch/xhci.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index edfec30..b77e7a5 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,9 +1,6 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c -romstage-y += pch.c -romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Gerrit-Change-Number: 46706 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: soc/intel/broadwell: Separate PCH in devicetree
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46700 ) Change subject: soc/intel/broadwell: Separate PCH in devicetree ...................................................................... soc/intel/broadwell: Separate PCH in devicetree Given the huge number of interlinked parts, this change is rather noisy. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 437 insertions(+), 395 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a309762..26a5336 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,27 +15,6 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - register "s0ix_enable" = "1" device cpu_cluster 0 on @@ -46,40 +25,64 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sio_acpi_mode" = "1" + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 60aef30..151c828 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index da80fec..2958cd8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f148964..88778d2 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,32 +7,34 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "sata_devslp_disable" = "0x1" - - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - register "s0ix_enable" = "0" device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus + chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 75c202d..77c5807 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 60aef30..151c828 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index c5d2747..3a429fb 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,30 +10,32 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - register "sata_port0_gen3_tx" = "0x72" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" # Disable S0ix for now register "s0ix_enable" = "0" - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 15.3 on end # GSPI0 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - device pci 1d.0 off end # USB2 EHCI + chip soc/intel/broadwell/pch + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + end end end diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index c4707e0..94fd804 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,27 +9,6 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -38,78 +17,102 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index bff39b7..29041aa 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -25,33 +16,45 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe5..0d0fc72 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + + chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..256077c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..d88c19c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI + end end end diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 220ad6f..06dd38b 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -14,11 +14,11 @@ #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> static void adsp_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45d512a..81c9780 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -7,70 +7,6 @@ #include <stdint.h> struct soc_intel_broadwell_config { - /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; - - /* GPIO SMI configuration */ - uint32_t alt_gp_smi_en; - - /* IDE configuration */ - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - uint32_t sata_port2_gen3_tx; - uint32_t sata_port3_gen3_tx; - uint32_t sata_port0_gen3_dtle; - uint32_t sata_port1_gen3_dtle; - uint32_t sata_port2_gen3_dtle; - uint32_t sata_port3_gen3_dtle; - - /* - * SATA DEVSLP Mux - * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 - * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 - */ - uint8_t sata_devslp_mux; - - /* - * DEVSLP Disable - * 0: DEVSLP is enabled - * 1: DEVSLP is disabled - */ - uint8_t sata_devslp_disable; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Put SerialIO devices into ACPI mode instead of a PCI device */ - uint8_t sio_acpi_mode; - - /* I2C voltage select: 0=3.3V 1=1.8V */ - uint8_t sio_i2c0_voltage; - uint8_t sio_i2c1_voltage; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -107,9 +43,6 @@ struct i915_gpu_controller_info gfx; - /* Enable S0iX support */ - int s0ix_enable; - /* * Minimum voltage for C6/C7 state: * 0x67 = 1.6V (full swing) @@ -132,9 +65,8 @@ /* Enable slow VR ramp rate */ int vr_slow_ramp_rate_enable; - /* Deep SX enable */ - int deep_sx_enable_ac; - int deep_sx_enable_dc; + /* Enable S0iX support */ + int s0ix_enable; /* TCC activation offset */ uint32_t tcc_offset; diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 0b6ef0d..5d7eceb 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -8,7 +8,6 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index dd4e15c..13ffd43 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -25,7 +25,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> @@ -131,7 +131,7 @@ u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? @@ -337,7 +337,7 @@ static void pch_init_deep_sx(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -568,7 +568,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 80ffe2b..40a81d8 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -26,7 +26,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> @@ -950,7 +950,7 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 2a27d92..e0c5bb0 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -166,10 +166,16 @@ } } -void broadwell_pch_enable_dev(struct device *dev) +static void broadwell_pch_enable_dev(struct device *dev) { u16 reg16; + if (dev->path.type != DEVICE_PATH_PCI) + return; + + if (dev->ops && dev->ops->enable) + return; + /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { case PCH_DEV_SLOT_PCIE: @@ -195,4 +201,9 @@ } } +struct chip_operations soc_intel_broadwell_pch_ops = { + CHIP_NAME("Intel Broadwell PCH") + .enable_dev = &broadwell_pch_enable_dev, +}; + #endif diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h new file mode 100644 index 0000000..2164a31 --- /dev/null +++ b/src/soc/intel/broadwell/pch/chip.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ +#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ + +#include <stdint.h> + +struct soc_intel_broadwell_pch_config { + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port2_gen3_tx; + uint32_t sata_port3_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + uint32_t sata_port2_gen3_dtle; + uint32_t sata_port3_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* Deep SX enable */ + int deep_sx_enable_ac; + int deep_sx_enable_dc; +}; + +#endif diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 0d41d42..c98201e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -13,7 +13,7 @@ #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <soc/cpu.h> #include <delay.h> @@ -121,7 +121,7 @@ root_port_config_update_gbe_port(); pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -436,7 +436,7 @@ static void pch_pcie_early(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index d68e17e..149dda1 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -12,7 +12,7 @@ #include <soc/rcba.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> static void pch_route_interrupts(void) { @@ -52,9 +52,9 @@ static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const config_t *config; + const struct device *const dev = pcidev_on_root(0x1f, 0); - config = config_of_soc(); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index c9168325..b496e53 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -11,7 +11,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> static inline u32 sir_read(struct device *dev, int idx) { @@ -27,7 +27,7 @@ static void sata_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -256,7 +256,7 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u16 map = 0x0060; map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 766f5dd..d32a27d 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -14,7 +14,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> /* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) @@ -156,7 +156,7 @@ static void serialio_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 4b4848b..80b9939 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -475,12 +475,6 @@ dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Gerrit-Change-Number: 46700 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 14

Change in coreboot[master]: Revert "broadwell: update processor power limits configuration"
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Tim Wawrzynczak, Puthikorn Voravootivat, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45011 to review the following change. Change subject: Revert "broadwell: update processor power limits configuration" ...................................................................... Revert "broadwell: update processor power limits configuration" This reverts commit fa42d568a00e5daadd35722790c529539227130e. Reason for revert: Passes in an incompatible structure and only happens to boot by chance. Moreover, Broadwell will soon be merged with Haswell and this requires Broadwell to not depend on any Intel common SoC code. Tested on out-of-tree Acer Aspire E5-573, PL values are correct again. Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/msr.h D src/soc/intel/broadwell/include/soc/soc_chip.h M src/soc/intel/broadwell/systemagent.c 8 files changed, 156 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45011/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 67f7563..20219d3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER @@ -35,12 +34,10 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT + select CPU_INTEL_COMMON select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 316b85a..588eb0c 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -24,7 +24,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> -#include <intelblocks/cpulib.h> /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45f91d8..46d895f 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,7 +4,6 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include <drivers/intel/gma/i915.h> -#include <intelblocks/cfg.h> #include <stdint.h> struct soc_intel_broadwell_config { diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1923301..fb4fecb 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -16,7 +16,6 @@ #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> -#include <intelblocks/cpulib.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -26,6 +25,64 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ @@ -231,6 +288,90 @@ RCBA32(PMSYNC_CONFIG2) = pmsync2; } +int cpu_config_tdp_levels(void) +{ + msr_t platform_info; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on server SKU */ + + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Set power limit values in MCHBAR as well */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + + /* Set DDR RAPL power limit by copying from MMIO to MSR */ + msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + wrmsr(MSR_DDR_RAPL_LIMIT, msr); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736..0260585 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -37,6 +37,10 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 1e47b44..250f0f8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -3,8 +3,6 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ -#include <intelblocks/msr.h> - #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -47,6 +45,14 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 +/* long duration in low dword, short duration in high dword */ +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h deleted file mode 100644 index ff77168..0000000 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_BROADWELL_SOC_CHIP_H_ -#define _SOC_BROADWELL_SOC_CHIP_H_ - -#include "../../chip.h" - -#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index b75c4fe..d5d234d 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -8,7 +8,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -405,7 +404,6 @@ static void systemagent_init(struct device *dev) { - struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -425,8 +423,7 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - config = config_of_soc(); - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); + set_power_limits(28); } static struct device_operations systemagent_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96 Gerrit-Change-Number: 45011 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Puthikorn Voravootivat <puthik(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46731 ) Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target` ...................................................................... soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target` This is needed because a follow-up removes Intel common SoC code Kconfig options. This will eventually be deduplicated once merged with Haswell. Tested on out-of-tree Acer E5-573, still boots. Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/cpu.c 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46731/1 diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 00460c6..694c727 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -290,6 +290,28 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +static void configure_thermal_target(void) +{ + config_t *conf; + struct device *lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activation offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -372,7 +394,7 @@ configure_misc(); /* Thermal throttle activation offset */ - configure_tcc_thermal_target(); + configure_thermal_target(); /* Enable Direct Cache Access */ configure_dca_cap(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a Gerrit-Change-Number: 46731 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/google/auron: Move SATA PCI device to overridetree
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46769 ) Change subject: mb/google/auron: Move SATA PCI device to overridetree ...................................................................... mb/google/auron: Move SATA PCI device to overridetree `chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope. Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip. TEST=Sanity-check static.c and verify variant overrides are used. Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 7 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46769/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7..79bb8b0 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -80,7 +80,6 @@ device pnp 0c09.0 on end end end # LPC bridge - device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal # end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index dc70085..f5f3eea 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index b46e34c..5a64648 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 45229ba..5b6ab9f 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -34,6 +34,7 @@ device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus # end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index eae7999..924e7d3 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index dc70085..f5f3eea 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 710fa95..9344575 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,6 +36,7 @@ device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI + device pci 1f.2 on end # SATA Controller # end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Gerrit-Change-Number: 46769 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/purism/librem_bdw: Prepare devicetree for PCH split
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46705 ) Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ...................................................................... mb/purism/librem_bdw: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, TODO. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/1 diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe5..4f34f7d 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + +# chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..237e697 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..b9b29cd 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI +# end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Gerrit-Change-Number: 46705 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/intel/wtm2: Prepare devicetree for PCH split
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46704 ) Change subject: mb/intel/wtm2: Prepare devicetree for PCH split ...................................................................... mb/intel/wtm2: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, TODO. Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/wtm2/devicetree.cb 1 file changed, 40 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46704/1 diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index bff39b7..927a603 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -25,33 +16,45 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + +# chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal +# end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9 Gerrit-Change-Number: 46704 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020