coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling
by Nico Huber (Code Review) 30 Oct '20

30 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45954 ) Change subject: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Gerrit-Change-Number: 45954 Gerrit-PatchSet: 32 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Oct 2020 09:41:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Nico Huber (Code Review) 30 Oct '20

30 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 29: (2 comments) https://review.coreboot.org/c/coreboot/+/45952/29/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/29/src/soc/intel/common/bloc… PS29, Line 56: also stop "also stops" / "will also stop"? https://review.coreboot.org/c/coreboot/+/45952/29/src/soc/intel/common/bloc… PS29, Line 57: TCO SMI interrupts caused by the : intruder continue working, though. Nit, this seems odd to mention as you were the only one suspecting that it doesn't work, FWIW. -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 29 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Oct 2020 09:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: .gitignore: Split into subdirectory files
by Patrick Georgi (Code Review) 30 Oct '20

30 Oct '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46879 ) Change subject: .gitignore: Split into subdirectory files ...................................................................... .gitignore: Split into subdirectory files There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M .gitignore A Documentation/.gitignore A payloads/coreinfo/.gitignore A payloads/external/.gitignore A payloads/libpayload/.gitignore A payloads/nvramcui/.gitignore A util/amdfwtool/.gitignore A util/archive/.gitignore A util/autoport/.gitignore A util/bincfg/.gitignore A util/board_status/.gitignore A util/bucts/.gitignore A util/cbfstool/.gitignore A util/cbmem/.gitignore A util/crossgcc/.gitignore A util/ectool/.gitignore A util/futility/.gitignore A util/genprof/.gitignore A util/ifdtool/.gitignore A util/intelmetool/.gitignore A util/intelp2m/.gitignore A util/inteltool/.gitignore A util/intelvbttool/.gitignore A util/kbc1126/.gitignore A util/msrtool/.gitignore A util/nvramtool/.gitignore A util/pmh7tool/.gitignore A util/spd_tools/.gitignore A util/superiotool/.gitignore A util/vgabios/.gitignore 30 files changed, 129 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46879/1 diff --git a/.gitignore b/.gitignore index 97cc9ce..a607772 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,3 @@ -payloads/libpayload/install/ -payloads/nvramcui/build -payloads/nvramcui/libpayload junit.xml abuild*.xml .config @@ -11,46 +8,8 @@ .ccwrap build/ coreboot-builds/ -payloads/coreinfo/lpbuild/ -payloads/coreinfo/lp.config* -payloads/external/depthcharge/depthcharge/ -payloads/external/FILO/filo/ -payloads/external/GRUB2/grub2/ -payloads/external/LinuxBoot/linuxboot/ -payloads/external/SeaBIOS/seabios/ -payloads/external/tianocore/tianocore/ -payloads/external/tint/tint/ -payloads/external/U-Boot/u-boot/ -payloads/external/Memtest86Plus/memtest86plus/ -payloads/external/iPXE/ipxe/ -util/crossgcc/acpica-unix-*/ -util/crossgcc/binutils-*/ -util/crossgcc/build-*BINUTILS/ -util/crossgcc/build-*EXPAT/ -util/crossgcc/build-*GCC/ -util/crossgcc/build-*GDB/ -util/crossgcc/build-*GMP/ -util/crossgcc/build-*LIBELF/ -util/crossgcc/build-*MPC/ -util/crossgcc/build-*MPFR/ -util/crossgcc/build-*PYTHON/ -util/crossgcc/build-*LVM/ -util/crossgcc/build-*IASL/ -util/crossgcc/expat-*/ -util/crossgcc/gcc-*/ -util/crossgcc/gdb-*/ -util/crossgcc/gmp-*/ -util/crossgcc/libelf-*/ -util/crossgcc/mingwrt-*/ -util/crossgcc/mpc-*/ -util/crossgcc/mpfr-*/ -util/crossgcc/Python-*/ -util/crossgcc/*.src/ -util/crossgcc/tarballs/ -util/crossgcc/w32api-*/ -util/crossgcc/xgcc/ -util/crossgcc/xgcc-*/ -util/crossgcc/xgcc +coreboot-builds*/ + site-local *.\# @@ -66,7 +25,6 @@ *.pyc *.sw[po] /*.rom -coreboot-builds*/ # Development friendly files tags @@ -76,60 +34,9 @@ xgcc/ tarballs/ -# -# KDE editors create lots of backup files whenever -# a file is edited, so just ignore them +# editor backup files, temporary files, IDE project files *~ *.kate-swp -# Ignore Kdevelop project file *.kdev4 -util/*/.dependencies -util/*/.test -util/amdfwtool/amdfwtool -util/archive/archive -util/bincfg/bincfg -util/board_status/board-status -util/bucts/bucts -util/cbfstool/cbfs-compression-tool -util/cbfstool/cbfstool -util/cbfstool/fmaptool -util/cbfstool/ifwitool -util/cbfstool/rmodtool -util/cbmem/.dependencies -util/cbmem/cbmem -util/ectool/ectool -util/futility/futility -util/genprof/genprof -util/getpir/getpir -util/ifdtool/ifdtool -util/intelmetool/intelmetool -util/inteltool/.dependencies -util/inteltool/inteltool -util/intelp2m/intelp2m -util/intelp2m/generate/gpio.h -util/intelvbttool/intelvbttool -util/msrtool/Makefile -util/msrtool/Makefile.deps -util/msrtool/msrtool -util/nvramtool/.dependencies -util/nvramtool/nvramtool -util/pmh7tool/pmh7tool -util/runfw/googlesnow -util/superiotool/superiotool -util/vgabios/testbios -util/autoport/autoport -util/kbc1126/kbc1126_ec_dump -util/kbc1126/kbc1126_ec_insert -util/spd_tools/*/gen_spd -util/spd_tools/*/gen_part_id - -Documentation/*.aux -Documentation/*.idx -Documentation/*.log -Documentation/*.toc -Documentation/*.out -Documentation/*.pdf -Documentation/_build - doxygen/* diff --git a/Documentation/.gitignore b/Documentation/.gitignore new file mode 100644 index 0000000..a8f5d5f --- /dev/null +++ b/Documentation/.gitignore @@ -0,0 +1,7 @@ +*.aux +*.idx +*.log +*.toc +*.out +*.pdf +_build diff --git a/payloads/coreinfo/.gitignore b/payloads/coreinfo/.gitignore new file mode 100644 index 0000000..101045e --- /dev/null +++ b/payloads/coreinfo/.gitignore @@ -0,0 +1,2 @@ +lpbuild/ +lp.config* diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore new file mode 100644 index 0000000..ebca429 --- /dev/null +++ b/payloads/external/.gitignore @@ -0,0 +1,10 @@ +depthcharge/depthcharge/ +FILO/filo/ +GRUB2/grub2/ +LinuxBoot/linuxboot/ +SeaBIOS/seabios/ +tianocore/tianocore/ +tint/tint/ +U-Boot/u-boot/ +Memtest86Plus/memtest86plus/ +iPXE/ipxe/ diff --git a/payloads/libpayload/.gitignore b/payloads/libpayload/.gitignore new file mode 100644 index 0000000..c7b20fc --- /dev/null +++ b/payloads/libpayload/.gitignore @@ -0,0 +1 @@ +install/ diff --git a/payloads/nvramcui/.gitignore b/payloads/nvramcui/.gitignore new file mode 100644 index 0000000..4885853 --- /dev/null +++ b/payloads/nvramcui/.gitignore @@ -0,0 +1,2 @@ +build +libpayload diff --git a/util/amdfwtool/.gitignore b/util/amdfwtool/.gitignore new file mode 100644 index 0000000..221a616 --- /dev/null +++ b/util/amdfwtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +amdfwtool diff --git a/util/archive/.gitignore b/util/archive/.gitignore new file mode 100644 index 0000000..ea0035f --- /dev/null +++ b/util/archive/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +archive diff --git a/util/autoport/.gitignore b/util/autoport/.gitignore new file mode 100644 index 0000000..dc8599e --- /dev/null +++ b/util/autoport/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +autoport diff --git a/util/bincfg/.gitignore b/util/bincfg/.gitignore new file mode 100644 index 0000000..ee1b394 --- /dev/null +++ b/util/bincfg/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +bincfg diff --git a/util/board_status/.gitignore b/util/board_status/.gitignore new file mode 100644 index 0000000..44847a9 --- /dev/null +++ b/util/board_status/.gitignore @@ -0,0 +1 @@ +board-status diff --git a/util/bucts/.gitignore b/util/bucts/.gitignore new file mode 100644 index 0000000..c5a4708 --- /dev/null +++ b/util/bucts/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +bucts diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore new file mode 100644 index 0000000..28fb4b2 --- /dev/null +++ b/util/cbfstool/.gitignore @@ -0,0 +1,7 @@ +.dependencies +.test +cbfs-compression-tool +cbfstool +fmaptool +ifwitool +rmodtool diff --git a/util/cbmem/.gitignore b/util/cbmem/.gitignore new file mode 100644 index 0000000..4905bd3 --- /dev/null +++ b/util/cbmem/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +cbmem diff --git a/util/crossgcc/.gitignore b/util/crossgcc/.gitignore new file mode 100644 index 0000000..0dfddd3 --- /dev/null +++ b/util/crossgcc/.gitignore @@ -0,0 +1,28 @@ +acpica-unix-*/ +binutils-*/ +build-*BINUTILS/ +build-*EXPAT/ +build-*GCC/ +build-*GDB/ +build-*GMP/ +build-*LIBELF/ +build-*MPC/ +build-*MPFR/ +build-*PYTHON/ +build-*LVM/ +build-*IASL/ +expat-*/ +gcc-*/ +gdb-*/ +gmp-*/ +libelf-*/ +mingwrt-*/ +mpc-*/ +mpfr-*/ +Python-*/ +*.src/ +tarballs/ +w32api-*/ +xgcc/ +xgcc-*/ +xgcc diff --git a/util/ectool/.gitignore b/util/ectool/.gitignore new file mode 100644 index 0000000..67d81e4 --- /dev/null +++ b/util/ectool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +ectool diff --git a/util/futility/.gitignore b/util/futility/.gitignore new file mode 100644 index 0000000..aa3b0c7 --- /dev/null +++ b/util/futility/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +futility diff --git a/util/genprof/.gitignore b/util/genprof/.gitignore new file mode 100644 index 0000000..14ffbb6 --- /dev/null +++ b/util/genprof/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +genprof diff --git a/util/ifdtool/.gitignore b/util/ifdtool/.gitignore new file mode 100644 index 0000000..6cdb423 --- /dev/null +++ b/util/ifdtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +ifdtool diff --git a/util/intelmetool/.gitignore b/util/intelmetool/.gitignore new file mode 100644 index 0000000..5de15c0 --- /dev/null +++ b/util/intelmetool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +intelmetool diff --git a/util/intelp2m/.gitignore b/util/intelp2m/.gitignore new file mode 100644 index 0000000..0696ea0 --- /dev/null +++ b/util/intelp2m/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +intelp2m +generate/gpio.h diff --git a/util/inteltool/.gitignore b/util/inteltool/.gitignore new file mode 100644 index 0000000..767fbcc --- /dev/null +++ b/util/inteltool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +inteltool diff --git a/util/intelvbttool/.gitignore b/util/intelvbttool/.gitignore new file mode 100644 index 0000000..d4d9279 --- /dev/null +++ b/util/intelvbttool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +intelvbttool diff --git a/util/kbc1126/.gitignore b/util/kbc1126/.gitignore new file mode 100644 index 0000000..9ded0a5 --- /dev/null +++ b/util/kbc1126/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +kbc1126_ec_dump +kbc1126_ec_insert diff --git a/util/msrtool/.gitignore b/util/msrtool/.gitignore new file mode 100644 index 0000000..13137c6 --- /dev/null +++ b/util/msrtool/.gitignore @@ -0,0 +1,5 @@ +.dependencies +.test +msrtool +Makefile +Makefile.deps diff --git a/util/nvramtool/.gitignore b/util/nvramtool/.gitignore new file mode 100644 index 0000000..ab07341 --- /dev/null +++ b/util/nvramtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +nvramtool diff --git a/util/pmh7tool/.gitignore b/util/pmh7tool/.gitignore new file mode 100644 index 0000000..4b8dbc5 --- /dev/null +++ b/util/pmh7tool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +pmh7tool diff --git a/util/spd_tools/.gitignore b/util/spd_tools/.gitignore new file mode 100644 index 0000000..5cd5413 --- /dev/null +++ b/util/spd_tools/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +*/gen_spd +*/gen_part_id diff --git a/util/superiotool/.gitignore b/util/superiotool/.gitignore new file mode 100644 index 0000000..566cd84 --- /dev/null +++ b/util/superiotool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +superiotool diff --git a/util/vgabios/.gitignore b/util/vgabios/.gitignore new file mode 100644 index 0000000..e19a8a5 --- /dev/null +++ b/util/vgabios/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +testbios -- To view, visit https://review.coreboot.org/c/coreboot/+/46879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Gerrit-Change-Number: 46879 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 30 Oct '20

30 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… PS18, Line 377: 2 > nit: a `#define CPPC_VERSION 2` or similar would be more readable did this a bit different, also see CB:46986 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Oct 2020 06:26:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Subrata Banik (Code Review) 30 Oct '20

30 Oct '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 ) Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Oct 2020 04:29:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] drivers/soundwire/alc711 : Add RT711 soundwire device
by Anil Kumar K (Code Review) 30 Oct '20

30 Oct '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46303 ) Change subject: [WIP] drivers/soundwire/alc711 : Add RT711 soundwire device ...................................................................... [WIP] drivers/soundwire/alc711 : Add RT711 soundwire device Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093 --- A src/drivers/soundwire/alc711/Kconfig A src/drivers/soundwire/alc711/Makefile.inc A src/drivers/soundwire/alc711/alc711.c A src/drivers/soundwire/alc711/chip.h M src/include/device/mipi_ids.h 5 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46303/1 diff --git a/src/drivers/soundwire/alc711/Kconfig b/src/drivers/soundwire/alc711/Kconfig new file mode 100644 index 0000000..bdc02a9 --- /dev/null +++ b/src/drivers/soundwire/alc711/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_ALC711 + bool diff --git a/src/drivers/soundwire/alc711/Makefile.inc b/src/drivers/soundwire/alc711/Makefile.inc new file mode 100644 index 0000000..78e4d1b --- /dev/null +++ b/src/drivers/soundwire/alc711/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC711) += alc711.c diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c new file mode 100644 index 0000000..bbe0ae0 --- /dev/null +++ b/src/drivers/soundwire/alc711/alc711.c @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <acpi/acpi_soundwire.h> +#include <device/device.h> +#include <device/path.h> +#include <device/mipi_ids.h> +#include <device/soundwire.h> +#include <stdio.h> + +#include "chip.h" + +static struct soundwire_address alc711_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC711, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave alc711_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(2), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode alc711_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of + supported input frequencies. */ + .bus_frequency_configs_count = 12, + .bus_frequency_configs = { + 9600 * KHz, 4800 * KHz, 2400 * KHz, 1200 * KHz, /* 9.6 MHz */ + 12000 * KHz, 6000 * KHz, 3000 * KHz, 1500 * KHz, /* 12 MHz */ + 12288 * KHz, 6144 * KHz, 3072 * KHz, 1536 * KHz /* 12.28 MHz */ + }, + /* Support 16 KHz to 96 KHz sampling frequency */ + .sampling_frequency_configs_count = 8, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc711_dp1 = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc711_codec = { + .slave = &alc711_slave, + .audio_mode = { &alc711_audio_mode }, + .dpn = { + { + + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc711_dp1 + }, + { + + /* Data Input for Speaker Path */ + .port = 1, + .source = &alc711_dp1 + } + } + +}; + +static void soundwire_alc711_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc711_address.link_id = dev->path.generic.id; + alc711_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc711_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc711_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc711_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, \ + dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc711_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc711_acpi_name, + .acpi_fill_ssdt = soundwire_alc711_fill_ssdt, +}; + +static void soundwire_alc711_enable(struct device *dev) +{ + dev->ops = &soundwire_alc711_ops; +} + +struct chip_operations drivers_soundwire_alc711_ops = { + CHIP_NAME("Realtek ALC711 SoundWire Codec") + .enable_dev = soundwire_alc711_enable +}; diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h new file mode 100644 index 0000000..6d317fd --- /dev/null +++ b/src/drivers/soundwire/alc711/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ + +struct drivers_soundwire_alc711_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 86b5116..cfbf3dd 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -20,6 +20,7 @@ /* Contributing Members */ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 +#define MIPI_DEV_ID_REALTEK_ALC711 0x0711 #define MIPI_MFG_ID_MAXIM 0x019f #define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 -- To view, visit https://review.coreboot.org/c/coreboot/+/46303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093 Gerrit-Change-Number: 46303 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 30 Oct '20

30 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt… PS10, Line 8: .tdp_pl2_override = 51, > Hi Deepika : […] Hi Ken, If you did not change it, pl4 will be set to 105 from the volteer settings. In that case this should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 15 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 30 Oct 2020 02:47:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Comment-In-Reply-To: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Ken Lu (Code Review) 30 Oct '20

30 Oct '20

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/10/src/mainboard/google/volt… PS10, Line 8: .tdp_pl2_override = 51, > Can you also please add .tdp_pl4 = 105, ? […] Hi Deepika : We did not adjust tdp_pl4 for thermal validation , do we need to set it to be 105 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 15 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 30 Oct 2020 02:40:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: temporarily silent GCC on none reliable macro
by HAOUAS Elyes (Code Review) 30 Oct '20

30 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42448 ) Change subject: temporarily silent GCC on none reliable macro ...................................................................... temporarily silent GCC on none reliable macro GCC-10 highlighted a none reliable MCHBARx_AND_OR macro: x4x: src/northbridge/intel/x4x/x4x.h:79:16: error: overflow in conversion from 'int' to 'u8' {aka 'volatile unsigned char'} changes value from '(int)*(volatile u8 *)((unsigned int)((int)i * 1024) + 4275126888) & -256 | 74' to '74' [-Werror=overflow] 79 | (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) | ^ src/northbridge/intel/x4x/raminit_ddr23.c:627:3: note: in expansion of macro 'MCHBAR8_AND_OR' 627 | MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a); | ^~~~~~~~~~~~~~ src/northbridge/intel/x4x/raminit_ddr23.c: In function 'prog_rcomp': src/northbridge/intel/x4x/x4x.h:83:17: error: overflow in conversion from 'int' to 'u16' {aka 'volatile short unsigned int'} changes value from '(int)*(volatile u16 *)((unsigned int)((int)i * 1024) + 4275127072) & -65536 | 26214' to '26214' [-Werror=overflow] 83 | (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) | ^ and for pineview: src/northbridge/intel/pineview/raminit.c: In function 'sdram_timings': src/northbridge/intel/pineview/pineview.h:98:52: error: overflow in conversion from 'int' to 'u8' {aka 'volatile unsigned char'} changes value from '(int)*4275126567 & -256 | 64' to '64' [-Werror=overflow] 98 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) | ^ src/northbridge/intel/pineview/raminit.c:793:2: note: in expansion of macro 'MCHBAR8_AND_OR' 793 | MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); | ^~~~~~~~~~~~~~ Also initialize 'reply.command' to avoid this error: src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma': src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7))) | ~~~~~^~~~~~~~ cc1: all warnings being treated as errors Change-Id: I07c1b3bd00de27c115994233086d32497b4c0925 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc M src/northbridge/intel/ironlake/raminit.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42448/1 diff --git a/Makefile.inc b/Makefile.inc index 86335d9..4e515c4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -412,6 +412,12 @@ CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie + +# Disable 'overflow' waring for not reliable MCHBARx_AND_OR macro +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X)$(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE)$(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) +CFLAGS_common += -Wno-overflow +endif + ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e85163f..12162ff 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1775,7 +1775,7 @@ { struct uma_reply { u8 group_id; - u8 command; + u8 command = 0; u8 reserved; u8 result; u8 field2; -- To view, visit https://review.coreboot.org/c/coreboot/+/42448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c1b3bd00de27c115994233086d32497b4c0925 Gerrit-Change-Number: 42448 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: soc/intel/broadwell: Drop reg-script to finalize PCH
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46710 ) Change subject: soc/intel/broadwell: Drop reg-script to finalize PCH ...................................................................... soc/intel/broadwell: Drop reg-script to finalize PCH Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/finalize.c 1 file changed, 22 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46710/1 diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c index 37afded..71f0639 100644 --- a/src/soc/intel/broadwell/pch/finalize.c +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> #include <soc/lpc.h> @@ -10,38 +9,31 @@ #include <soc/spi.h> #include <southbridge/intel/common/spi.h> -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) - /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif - - /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), - - /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), - - /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), - - /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), - - /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), - - /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - void broadwell_pch_finalize(void) { spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); + + /* Lock SPIBAR */ + if (!CONFIG(EM100PRO_SPI_CONSOLE)) + RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); + + /* TC Lockdown */ + RCBA32_OR(0x0050, 1 << 31); + + /* BIOS Interface Lockdown */ + RCBA32_OR(GCS, 1 << 0); + + /* Function Disable SUS Well Lockdown */ + RCBA8(FDSW) |= 1 << 7; + + /* Global SMI Lock */ + pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK); + + /* GEN_PMCON Lock */ + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + + /* PMSYNC */ + RCBA32_OR(PMSYNC_CONFIG, 1 << 31); /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); -- To view, visit https://review.coreboot.org/c/coreboot/+/46710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172 Gerrit-Change-Number: 46710 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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