coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Tim Wawrzynczak (Code Review) 30 Oct '20

30 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 16 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 30 Oct 2020 15:46:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: fw_config: Make fw_config_get() public
by Tim Wawrzynczak (Code Review) 30 Oct '20

30 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46604 ) Change subject: fw_config: Make fw_config_get() public ...................................................................... fw_config: Make fw_config_get() public Further patches will make use of this raw 64-bit value. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084 --- M src/include/fw_config.h M src/lib/fw_config.c 2 files changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46604/1 diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 494ce7f..c9ef75f 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -33,6 +33,13 @@ #if CONFIG(FW_CONFIG) /** + * fw_config_get() - Provide firmware configuration value. + * + * Return 64bit firmware configuration value determined for the system. + */ +uint64_t fw_config_get(void); + +/** * fw_config_probe() - Check if field and option matches. * @match: Structure containing field and option to probe. * diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index 0973cbe..e17d40e 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -12,12 +12,7 @@ #include <stdbool.h> #include <stdint.h> -/** - * fw_config_get() - Provide firmware configuration value. - * - * Return 64bit firmware configuration value determined for the system. - */ -static uint64_t fw_config_get(void) +uint64_t fw_config_get(void) { static uint64_t fw_config_value; static bool fw_config_value_initialized; -- To view, visit https://review.coreboot.org/c/coreboot/+/46604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084 Gerrit-Change-Number: 46604 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: fw_config: Convert fw_config to a 64-bit field
by Tim Wawrzynczak (Code Review) 30 Oct '20

30 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45939 ) Change subject: fw_config: Convert fw_config to a 64-bit field ...................................................................... fw_config: Convert fw_config to a 64-bit field We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=added 0x1 to SSFC and 0x201 to FW_CONFIG from ectool on Volteer. Verified via console print that FW_CONFIG is 0x100000201. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/include/fw_config.h M src/lib/fw_config.c M src/mainboard/google/dedede/board_info.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/baseboard/helpers.c M util/sconfig/main.c 8 files changed, 50 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45939/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 40285dc..f9e8c7d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -841,9 +841,20 @@ return cbi_get_uint32(id, CBI_TAG_SKU_ID); } -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config) +/* ChromeOS firmware is treating FW_CONFIG & SSFC as one 64-bit field */ +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config) { - return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG); + uint32_t config; + uint32_t ssfc; + + if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG)) + return -1; + + if (cbi_get_uint32(&ssfc, CBI_TAG_SSFC)) + return -1; + + *fw_config = (uint64_t)((uint64_t)ssfc << 32) | (uint64_t)config; + return 0; } int google_chromeec_cbi_get_oem_id(uint32_t *id) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 9d4e588..d074d1a 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -74,7 +74,7 @@ */ int google_chromeec_cbi_get_oem_id(uint32_t *id); int google_chromeec_cbi_get_sku_id(uint32_t *id); -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); /* version may be stored in CBI as a smaller integer width, but the EC code diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 81980b9..494ce7f 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -18,8 +18,8 @@ struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; /* Generate a pointer to a compound literal of the fw_config structure. */ @@ -53,7 +53,7 @@ * * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL. */ -const struct fw_config *fw_config_get_found(uint32_t field_mask); +const struct fw_config *fw_config_get_found(uint64_t field_mask); #else diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index fdfab0a..a4aa777 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <ec/google/chromeec/ec.h> #include <fw_config.h> +#include <inttypes.h> #include <lib.h> #include <stdbool.h> #include <stdint.h> @@ -14,11 +15,11 @@ /** * fw_config_get() - Provide firmware configuration value. * - * Return 32bit firmware configuration value determined for the system. + * Return 64bit firmware configuration value determined for the system. */ -static uint32_t fw_config_get(void) +static uint64_t fw_config_get(void) { - static uint32_t fw_config_value; + static uint64_t fw_config_value; static bool fw_config_value_initialized; /* Nothing to prepare if setup is already done. */ @@ -35,7 +36,7 @@ __func__); fw_config_value = 0; } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n", + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -47,7 +48,7 @@ printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); } - printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value); + printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -59,7 +60,8 @@ printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name, match->option_name); else - printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n", + printk(BIOS_INFO, "fw_config match found: mask=0x%" PRIx64 " value=0x%" + PRIx64 "\n", match->mask, match->value); return true; } @@ -70,20 +72,20 @@ #if ENV_RAMSTAGE /* - * The maximum number of fw_config fields is limited by the 32-bit mask that is used to + * The maximum number of fw_config fields is limited by the 64-bit mask that is used to * represent them. */ -#define MAX_CACHE_ELEMENTS (8 * sizeof(uint32_t)) +#define MAX_CACHE_ELEMENTS (8 * sizeof(uint64_t)) static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS]; -static size_t probe_index(uint32_t mask) +static size_t probe_index(uint64_t mask) { assert(mask); - return __ffs(mask); + return __ffs_64(mask); } -const struct fw_config *fw_config_get_found(uint32_t field_mask) +const struct fw_config *fw_config_get_found(uint64_t field_mask) { const struct fw_config *config; config = cached_configs[probe_index(field_mask)]; diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index fdb4b5f..22d35d7 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> -int board_info_get_fw_config(uint32_t *fw_config) +int board_info_get_fw_config(uint64_t *fw_config) { return google_chromeec_cbi_get_fw_config(fw_config); } diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bd94ef4..44b2b72 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,7 @@ * @param fw_config Address where the fw_config is stored. * @return 0 on success or negative integer for errors. */ -int board_info_get_fw_config(uint32_t *fw_config); +int board_info_get_fw_config(uint64_t *fw_config); /* Return memory configuration structure. */ const struct mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d95ab82..63ff24a 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -48,9 +48,9 @@ FW_CONFIG_SHIFT_FAN = 27, }; -static int get_fw_config(uint32_t *val) +static int get_fw_config(uint64_t *val) { - static uint32_t known_value; + static uint64_t known_value; if (known_value) { *val = known_value; @@ -67,9 +67,9 @@ return 0; } -static unsigned int extract_field(uint32_t mask, int shift) +static unsigned int extract_field(uint64_t mask, int shift) { - uint32_t fw_config; + uint64_t fw_config; /* On errors nothing is assumed to be set. */ if (get_fw_config(&fw_config)) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index d5504cd..30e08c3 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -4,8 +4,9 @@ #include <assert.h> #include <ctype.h> #include <getopt.h> -/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ +#include <inttypes.h> #include <libgen.h> +/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ #include <sys/stat.h> #include <commonlib/helpers.h> #include <stdint.h> @@ -402,8 +403,8 @@ { struct fw_config_field *field = find_fw_config_field(name); - /* Check that field is within 32bits. */ - if (start_bit > end_bit || end_bit > 31) { + /* Check that field is within 64 bits. */ + if (start_bit > end_bit || end_bit > 63) { printf("ERROR: fw_config field %s has invalid range %u-%u\n", name, start_bit, end_bit); exit(1); @@ -455,12 +456,12 @@ void add_fw_config_option(struct fw_config_field *field, const char *name, unsigned int value) { struct fw_config_option *option; - uint32_t field_max_value; + uint64_t field_max_value; /* Check that option value fits within field mask. */ - field_max_value = (1 << (1 + field->end_bit - field->start_bit)) - 1; - if (value > field_max_value) { - printf("ERROR: fw_config option %s:%s value %u larger than field max %u\n", + field_max_value = (1ull << (1ull + field->end_bit - field->start_bit)) - 1ull; + if ((uint64_t)value > field_max_value) { + printf("ERROR: fw_config option %s:%s value %u larger than field max %" PRIx64 "\n", field->name, name, value, field_max_value); exit(1); } @@ -532,23 +533,23 @@ while (field) { struct fw_config_option *option = field->options; - uint32_t mask; + uint64_t mask; fprintf(fil, "#define FW_CONFIG_FIELD_%s_NAME \"%s\"\n", field->name, field->name); /* Compute mask from start and end bit. */ - mask = ((1 << (1 + field->end_bit - field->start_bit)) - 1); + mask = ((1ull << (1ull + field->end_bit - field->start_bit)) - 1ull); mask <<= field->start_bit; - fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%08x\n", + fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%" PRIx64 "\n", field->name, mask); while (option) { fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_NAME \"%s\"\n", field->name, option->name, option->name); - fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%08x\n", - field->name, option->name, option->value << field->start_bit); + fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%" PRIx64 "\n", + field->name, option->name, (uint64_t)(option->value << (uint64_t)field->start_bit)); option = option->next; } @@ -569,7 +570,7 @@ /* Find matching field. */ struct fw_config_field *field; struct fw_config_option *option; - uint32_t mask, value; + uint64_t mask, value; field = find_fw_config_field(probe->field); if (!field) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Gerrit-Change-Number: 45939 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tigerlake mainboards: switch to devtree aliases for PMC MUX connectors
by Tim Wawrzynczak (Code Review) 30 Oct '20

30 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45878 ) Change subject: tigerlake mainboards: switch to devtree aliases for PMC MUX connectors ...................................................................... tigerlake mainboards: switch to devtree aliases for PMC MUX connectors Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 9 files changed, 67 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45878/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e32b2f9..102c2cc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -47,7 +47,7 @@ register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index fc549c7..1b603f0 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -56,6 +56,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -66,14 +73,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 42d3f2f..5fd136a 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -127,6 +127,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -137,14 +144,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 42d3f2f..5fd136a 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -127,6 +127,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -137,14 +144,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 5079493..9615985 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -208,6 +208,13 @@ end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -217,14 +224,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB4_GEN2 probe DB_USB USB3_ACTIVE probe DB_USB USB4_GEN3 @@ -235,7 +242,7 @@ register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU & HSL follow CC - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB3_PASSIVE end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..bf382b7 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -7,6 +7,7 @@ device domain 0 on device pci 05.0 on end # IPU 0x9A19 + device pci 0d.2 on end # tbt_dma0 device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -166,6 +167,13 @@ end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -175,14 +183,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB4_GEN2 probe DB_USB USB3_ACTIVE probe DB_USB USB4_GEN3 @@ -193,12 +201,12 @@ register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU & HSL follow CC - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB3_PASSIVE end end end end - end # PMC + end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..4ec4849 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -120,6 +120,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -130,14 +137,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5965372..a7ed0bb 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -262,6 +262,8 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -276,14 +278,14 @@ register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "7" register "usb3_port_number" = "4" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 90e7928..4b3859e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -258,6 +258,8 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -272,14 +274,14 @@ register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/45878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Gerrit-Change-Number: 45878 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 21

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 30 Oct '20

30 Oct '20

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 17 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 9bfb1c4..3915cf9 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -3,7 +3,14 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H +#include <device/device.h> +#include <stddef.h> + +#define MAX_TYPEC_PORTS 4 + struct ec_google_chromeec_config { + /* Pointer to PMC Mux connector for each Type-C port */ + DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index b768316..344f5f4 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -16,14 +16,6 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" -/* Avoid adding a false dependency on an SoC or intel/common */ -extern const struct device *soc_get_pmc_mux_device(int port_number); - -__weak const struct device *soc_get_pmc_mux_device(int port_number) -{ - return NULL; -} - const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -121,36 +113,18 @@ static struct usb_pd_port_caps port_caps; static void add_port_location(struct acpi_dp *dsd, int port_number) { - acpi_dp_add_string(dsd, "port-location", - port_location_to_str(port_caps.port_location)); -} - -static int conn_id_to_match; - -/* A callback to match a port's connector for dev_find_matching_device_on_bus */ -static bool match_connector(DEVTREE_CONST struct device *dev) -{ - if (CONFIG(DRIVERS_INTEL_PMC)) { - extern struct chip_operations drivers_intel_pmc_mux_conn_ops; - - return (dev->chip_ops == &drivers_intel_pmc_mux_conn_ops && - dev->path.type == DEVICE_PATH_GENERIC && - dev->path.generic.id == conn_id_to_match); - } - - return false; + acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } static void fill_ssdt_typec_device(const struct device *dev) { + struct ec_google_chromeec_config *config = dev->chip_info; int rv; int i; unsigned int num_ports; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; - const struct device *mux; - const struct device *conn; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -166,32 +140,28 @@ if (rv) continue; - /* Get the MUX device, and find the matching connector on its bus */ - conn = NULL; - mux = soc_get_pmc_mux_device(i); - if (mux) { - conn_id_to_match = i; - conn = dev_find_matching_device_on_bus(mux->link_list, match_connector); - } + if (!config->mux_conn[i]) + printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port " + "#%d\n", i); usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); - struct typec_connector_class_config config = { + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, .data_role = port_caps.data_role_cap, .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, - .orientation_switch = conn, - .usb_role_switch = conn, - .mode_switch = conn, + .orientation_switch = config->mux_conn[i], + .usb_role_switch = config->mux_conn[i], + .mode_switch = config->mux_conn[i], }; - acpigen_write_typec_connector(&config, i, add_port_location); + acpigen_write_typec_connector(&typec_config, i, add_port_location); } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e2127..329bbe9 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -51,13 +51,4 @@ /* API to set ACPI mode */ void pmc_set_acpi_mode(void); -/* - * Returns a reference to the PMC MUX device for the given port number. - * Returns NULL if not found or SoC does not support PMC MUX. - * - * Input: Port number (0-based) - * Output: Const pointer to PMC MUX device - */ -const struct device *soc_get_pmc_mux_device(int port_number); - #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06..dbf3671 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -126,28 +126,6 @@ dev_path(dev)); } -/* FIXME: Rewrite loop below without this. */ -extern struct chip_operations drivers_intel_pmc_mux_ops; - -/* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ -const struct device *soc_get_pmc_mux_device(int port_number) -{ - const struct device *pmc; - struct device *child; - - child = NULL; - pmc = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!pmc || !pmc->link_list) - return NULL; - - while ((child = dev_bus_each_child(pmc->link_list, child)) != NULL) - if (child->chip_ops == &drivers_intel_pmc_mux_ops) - break; - - /* child will either be the correct device or NULL if not found */ - return child; -} - static void soc_acpi_mode_init(struct device *dev) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 13 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 30 Oct '20

30 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 16: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… PS15, Line 54: 10-15W PL1 > Look like 3-15W below in the code Done https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… PS15, Line 55: PL2 is fixed at 64W > Look like 15-51W below in the code Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 16 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 30 Oct 2020 15:23:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Opal Voravootivat <puthik(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 30 Oct '20

30 Oct '20

Deepika Punyamurtula has uploaded a new patch set (#16) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 16 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel/Makefile.inc: Use correct Kconfig symbols
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46943 ) Change subject: cpu/intel/Makefile.inc: Use correct Kconfig symbols ...................................................................... cpu/intel/Makefile.inc: Use correct Kconfig symbols Guard CPU code using CPU Kconfig symbols instead of northbridge symbols. Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Makefile.inc 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/46943/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19..01913de 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,9 +10,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x +subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax +subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 -- To view, visit https://review.coreboot.org/c/coreboot/+/46943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9 Gerrit-Change-Number: 46943 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell/sata.c: Simplify RMW operations
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47025 ) Change subject: soc/intel/broadwell/sata.c: Simplify RMW operations ...................................................................... soc/intel/broadwell/sata.c: Simplify RMW operations Introduce the `sir_unset_and_set_mask` helper and update the one PCI read-modify-write operation that is somehow not reproducible. Change-Id: I334623ab19537a6c16fad2ca293522c71c624eee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 13 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47025/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 3ed136b..ab73dbd 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -27,12 +27,19 @@ pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_init(struct device *dev) { const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; - u16 reg16; int port; printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); @@ -49,10 +56,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~SATA_PORT_MASK; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -208,25 +212,16 @@ sir_write(dev, 0x64, 0x883c9003); /* Step 2: SIR 68h[15:0] = 880Ah */ - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0x880a; - sir_write(dev, 0x68, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a); /* Step 3: SIR 60h[3] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 3); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3); /* Step 4: SIR 60h[0] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0); /* Step 5: SIR 60h[1] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 1); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); -- To view, visit https://review.coreboot.org/c/coreboot/+/47025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I334623ab19537a6c16fad2ca293522c71c624eee Gerrit-Change-Number: 47025 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/broadwell: Iron out more cosmetic differences
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46979 ) Change subject: soc/intel/broadwell: Iron out more cosmetic differences ...................................................................... soc/intel/broadwell: Iron out more cosmetic differences Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I151595ba677ab4e1a3c5e40eb49f63b0b40a027c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/serialio.c M src/soc/intel/broadwell/pch/smbus.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/report_platform.c 11 files changed, 138 insertions(+), 160 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46979/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index db9aced..3a9ac13 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -57,16 +57,16 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index fc56e4e..59c31aa 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -2,7 +2,6 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> - #include "haswell.h" void bootblock_early_northbridge_init(void) @@ -10,16 +9,14 @@ uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent + * non-explicit config accesses use MCFG. This code also assumes that + * bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 8370167..0c881c2 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -23,7 +23,7 @@ #include "haswell.h" -#define GT_RETRY 1000 +#define GTT_RETRY 1000 enum { GT_CDCLK_DEFAULT = 0, GT_CDCLK_337, @@ -42,7 +42,7 @@ /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), @@ -103,10 +103,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), /* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), /* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -126,13 +126,13 @@ /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), /* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY), REG_SCRIPT_END }; @@ -140,7 +140,7 @@ static const struct reg_script broadwell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY), /* Enable push bus metric control and shift */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), @@ -205,10 +205,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000), /* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), /* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -227,12 +227,12 @@ /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), /* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY), REG_SCRIPT_END }; @@ -266,7 +266,8 @@ } int gtt_poll(u32 reg, u32 mask, u32 value) -{ unsigned int try = GT_RETRY; +{ + unsigned int try = GTT_RETRY; u32 data; while (try--) { diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index df3a7550..09de2ef 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -100,7 +100,7 @@ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 +#define INTRDIRCTL 0x5418 #define GDXCBAR 0x5420 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 1409c20..8b1567e 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -53,7 +53,6 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 1319a02..5fec655 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -35,8 +35,7 @@ return pci_read_config32(sa_dev, BGSM) & ~1; } -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -49,19 +48,19 @@ return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); *len = 256 * 1024 * 1024; return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); *len = 128 * 1024 * 1024; return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); *len = 64 * 1024 * 1024; return 1; } @@ -71,35 +70,31 @@ static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = pci_read_config32(dev, index); - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; } -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = MCHBAR32(index); - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; @@ -108,24 +103,22 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; +#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, 0x8000, get_bar, "MCHBAR" }, - { DMIBAR, 0x1000, get_bar, "DMIBAR" }, - { EPBAR, 0x1000, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, + { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, + { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, + { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, + { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, }; +#undef SIZE_KB -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -138,14 +131,13 @@ size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) continue; resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -154,7 +146,8 @@ } } -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ TOUUD * | | @@ -167,13 +160,15 @@ * +--------------------------+ BGSM * | TSEG | * +--------------------------+ TSEGMB + * | DPR | + * +--------------------------+ (DPR top - DPR size) * | Usage DRAM | * +--------------------------+ 0 * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. */ struct map_entry { @@ -183,14 +178,13 @@ const char *description; }; -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); mask = ~mask; value = 0; @@ -217,12 +211,9 @@ .description = desc_, \ } -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) enum { TOM_REG, @@ -235,21 +226,21 @@ BGSM_REG, BDSM_REG, TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES + /* Must be last */ + NUM_MAP_ENTRIES, }; static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), }; static void mc_read_map_entries(struct device *dev, uint64_t *values) @@ -266,22 +257,20 @@ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } - /* One can validate the BDSM and BGSM against the GGC. */ + /* One can validate the BDSM and BGSM against the GGC */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; + unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Read in the MAP registers and report their values. */ + /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); @@ -299,33 +288,29 @@ /* * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG: cacheable + * - TSEG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. + * The default SMRAM space is reserved so that the range doesn't have to be saved + * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a + * bit of an odd place to reserve the region, but the CPU devices don't have + * dev_ops->read_resources() called on them. * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. + * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to + * handle legacy VGA memory. If this range is not omitted the mtrr code will setup + * the area as cacheable, causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation + * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing + * MTRRs covering this region. * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. + * It should be noted that cacheable entry types need to be added in order. The reason + * is that the current MTRR code assumes this and falls over itself if it isn't. * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. + * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ index = *resource_cnt; @@ -365,12 +350,11 @@ /* Reserve everything between A segment and 1MB: * - * 0xa0000 - 0xbffff: legacy VGA + * 0xa0000 - 0xbffff: Legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); @@ -378,43 +362,40 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +static void mc_read_resources(struct device *dev) { int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - /* Read standard PCI resources. */ + /* Read standard PCI resources */ pci_dev_read_resources(dev); - /* Add all fixed MMIO resources. */ + /* Add all fixed MMIO resources */ mc_add_fixed_mmio_resources(dev); - /* Add VT-d MMIO resources if capable */ + /* Add VT-d MMIO resources, if capable */ if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); } - /* Calculate and add DRAM resources. */ + /* Calculate and add DRAM resources */ mc_add_dram_resources(dev, &index); } -static void systemagent_init(struct device *dev) +static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; + MCHBAR8(INTRDIRCTL) = pair; /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; @@ -426,12 +407,12 @@ set_power_limits(28); } -static struct device_operations systemagent_ops = { - .read_resources = systemagent_read_resources, +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, + .init = northbridge_init, .ops_pci = &pci_dev_ops_pci, }; @@ -444,7 +425,7 @@ }; static const struct pci_driver systemagent_driver __pci_driver = { - .ops = &systemagent_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = systemagent_ids }; @@ -461,10 +442,10 @@ static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = &mp_cpu_bus_init, + .init = mp_cpu_bus_init, }; -static void broadwell_enable(struct device *dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -476,6 +457,6 @@ struct chip_operations soc_intel_broadwell_ops = { CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, - .init = &broadwell_init_pre_device, + .enable_dev = enable_dev, + .init = broadwell_init_pre_device, }; diff --git a/src/soc/intel/broadwell/pch/me.h b/src/soc/intel/broadwell/pch/me.h index 5282441..df71fca 100644 --- a/src/soc/intel/broadwell/pch/me.h +++ b/src/soc/intel/broadwell/pch/me.h @@ -436,7 +436,7 @@ u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; - u16 flash_wear_out : 1; + u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; } __packed tdt_state_flag; diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index 97372e3..0c079be 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -143,7 +143,7 @@ { if (acpi_mode) { /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ - RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); + RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5)); } /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c index 76562ce..da0ca87 100644 --- a/src/soc/intel/broadwell/pch/smbus.c +++ b/src/soc/intel/broadwell/pch/smbus.c @@ -19,7 +19,7 @@ /* Enable clock gating */ /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 270b4d2..6304194 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -377,7 +377,7 @@ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); + disable_pm1_control(-1); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } } @@ -430,7 +430,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index ad5a109..b02b234 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -87,7 +87,7 @@ strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32 *)cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; -- To view, visit https://review.coreboot.org/c/coreboot/+/46979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151595ba677ab4e1a3c5e40eb49f63b0b40a027c Gerrit-Change-Number: 46979 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020