coreboot-gerrit October 2020

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Change in coreboot[master]: cpu/x86: increase timeout for CPUs to check in after 2nd SIPI
by Jonathan Zhang (Code Review) 30 Oct '20

30 Oct '20

Hello Tim Chu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46898 to review the following change. Change subject: cpu/x86: increase timeout for CPUs to check in after 2nd SIPI ...................................................................... cpu/x86: increase timeout for CPUs to check in after 2nd SIPI Increase timeout for CPUs to check in after 2nd SIPI completion from 10ms to 100ms. Update logging level for mp init failure cases from BIOS_DEBUG to BIOS_ERR. Without this patch, "mp initialization failure" happens on some reboots on DeltaLake server. As consequence, not all 52 cpus come up in Linux: [root@localhost ~]# lscpu ... CPU(s): 40 Also following Hardware Errors are seen: [ 4.365762] mce: [Hardware Error]: Machine check events logged [ 4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d With this patch, no such failure is observed with 370 reboots. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208 --- M src/cpu/x86/mp_init.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46898/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4870529..db21262 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -434,7 +434,7 @@ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -451,7 +451,7 @@ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -462,7 +462,7 @@ LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -477,7 +477,7 @@ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -488,14 +488,14 @@ LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", + if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { + printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208 Gerrit-Change-Number: 46898 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases
by Duncan Laurie (Code Review) 30 Oct '20

30 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46852 ) Change subject: soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases ...................................................................... soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases Enable the USB4 XHCI driver and remove the ACPI name entry from the SOC level function. Define aliases for the USB2/3 ports on north and south XHCI devices in chipset.cb so they can be referenced in the mainboard devicetree. BUG=b:151731851 TEST=define usb ports by reference in volteer devicetree and ensure they get properties added in SSDT for both north and south XHCI device. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chipset.cb 3 files changed, 70 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46852/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2b5f0ba..9eb229e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -14,6 +14,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB @@ -50,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 46c043f..62201a2 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -66,7 +66,6 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index b60801c..1daa64b 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -32,7 +32,25 @@ device pci 08.0 alias gna off end device pci 09.0 alias npk off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias north_xhci off end + device pci 0d.0 alias north_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias tcss_usb3_port4 off end + end + end + end + end device pci 0d.1 alias north_xdci off end device pci 0d.2 alias tbt_dma0 off end device pci 0d.3 alias tbt_dma1 off end @@ -43,7 +61,55 @@ device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias south_xhci off end + device pci 14.0 alias south_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end device pci 14.1 alias south_xdci off end device pci 14.2 alias shared_ram off end chip drivers/wifi/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/46852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0 Gerrit-Change-Number: 46852 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generation
by Duncan Laurie (Code Review) 30 Oct '20

30 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46851 ) Change subject: soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generation ...................................................................... soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generation In order to generate ACPI entries for USB devices attached to the USB4/TBT/TCSS/North XHCI device it needs to have a driver that will enumerate static devices on the bus. This driver does that and nothing else. BUG=b:151731851 TEST=boot on volteer and check for USB devices on \_SB.PCI0.TXHC.RHUB Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/xhci.c 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46851/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index be0b378..8d18180 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -11,3 +11,10 @@ help Chip driver for adding PCI ops and SSDT generation for common Intel USB4/Thunderbolt root ports. + +config SOC_INTEL_COMMON_BLOCK_USB4_XHCI + bool + default n + help + Chip driver for adding PCI ops and SSDT generation for common Intel + USB4/Thunderbolt North XHCI ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc index 89ce426..91f0991 100644 --- a/src/soc/intel/common/block/usb4/Makefile.inc +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_XHCI) += xhci.c diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c new file mode 100644 index 0000000..4fe60dd --- /dev/null +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/acpi.h> +#include <soc/pci_devs.h> + +static const char *usb4_xhci_acpi_name(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + return "TXHC"; +} + +static struct device_operations usb4_xhci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = usb4_xhci_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI, + 0 +}; + +static const struct pci_driver usb4_xhci __pci_driver = { + .ops = &usb4_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b Gerrit-Change-Number: 46851 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/xeon_sp: Move read_msr_ppin() to common util.c
by Marc Jones (Code Review) 30 Oct '20

30 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46479 ) Change subject: soc/intel/xeon_sp: Move read_msr_ppin() to common util.c ...................................................................... soc/intel/xeon_sp: Move read_msr_ppin() to common util.c Move CPX and SKX read_msr_ppin() to common util.c file. Update the drive/ocp/smbios #include to match. Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/drivers/ocp/dmi/smbios.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/cpu.h M src/soc/intel/xeon_sp/util.c 7 files changed, 35 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46479/1 diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c index 4e54af0..d0ef115 100644 --- a/src/drivers/ocp/dmi/smbios.c +++ b/src/drivers/ocp/dmi/smbios.c @@ -9,7 +9,7 @@ #include <stdio.h> #include <string.h> #include <soc/soc_util.h> -#include <soc/cpu.h> +#include <soc/util.h> #include <smbios.h> #include "ocp_dmi.h" diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 4afe47c..5bde819 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -205,34 +205,3 @@ /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 19f6e4c..693de8f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -10,6 +10,5 @@ #define CPUID_COOPERLAKE_SP_A1 0x05065b void cpx_init_cpus(struct device *dev); -msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 8c2b597..51e2b69 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -3,10 +3,12 @@ #ifndef _XEON_SP_SOC_UTIL_H_ #define _XEON_SP_SOC_UTIL_H_ +#include <cpu/x86/msr.h> #include <hob_iiouds.h> void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); +msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 73d7a73..1a11a42 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -244,34 +244,3 @@ FUNC_EXIT(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index c2af265..0e3028d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -16,6 +16,5 @@ int get_cpu_count(void); void xeon_sp_init_cpus(struct device *dev); -msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 77fc1e4..66b9ef1 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci.h> #include <soc/pci_devs.h> +#include <soc/msr.h> #include <soc/util.h> void get_stack_busnos(uint32_t *bus) @@ -53,3 +54,34 @@ if (bus3) *bus3 = (bus >> 24) & 0xff; } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8 Gerrit-Change-Number: 46479 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move common chip.c code
by Marc Jones (Code Review) 30 Oct '20

30 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46478 ) Change subject: soc/intel/xeon_sp: Move common chip.c code ...................................................................... soc/intel/xeon_sp: Move common chip.c code Move common CPX and SKX chip.c code to chip_common.c. Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c 5 files changed, 541 insertions(+), 1,046 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46478/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 8a26c14..543deeb 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c chip_common.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c new file mode 100644 index 0000000..3641da3 --- /dev/null +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -0,0 +1,526 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> +#include <console/console.h> +#include <post.h> +#include <device/pci.h> +#include <soc/chip_common.h> +#include <soc/soc_util.h> +#include <stdlib.h> + +struct pci_resource { + struct device *dev; + struct resource *res; + struct pci_resource *next; +}; + +struct stack_dev_resource { + uint8_t align; + struct pci_resource *children; + struct stack_dev_resource *next; +}; + +typedef enum { + RES_TYPE_IO = 0, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM, + MAX_RES_TYPES +} ResType; + +static ResType get_res_type(uint64_t flags) +{ + if (flags & IORESOURCE_IO) + return RES_TYPE_IO; + if (flags & IORESOURCE_MEM) { + if (flags & IORESOURCE_PREFETCH) { + printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); + return RES_TYPE_PREF_MEM; + } + /* both 64-bit and 32-bit use below 4GB address space */ + return RES_TYPE_NONPREF_MEM; + } + printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); + die("Invalida resource type"); +} + +static bool need_assignment(uint64_t flags) +{ + if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED)) + return false; + else + return true; +} + +static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) +{ + if (res_type == RES_TYPE_IO) { + assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); + return stack->PciResourceIoBase; + } + if (res_type == RES_TYPE_NONPREF_MEM) { + assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); + return stack->PciResourceMem32Base; + } + assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); + return stack->PciResourceMem64Base; +} + +static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) +{ + if (res_type == RES_TYPE_IO) { + assert(base <= (stack->PciResourceIoLimit + 1)); + stack->PciResourceIoBase = base; + } else if (res_type == RES_TYPE_NONPREF_MEM) { + assert(base <= (stack->PciResourceMem32Limit + 1)); + stack->PciResourceMem32Base = base; + } else { + assert(base <= (stack->PciResourceMem64Limit + 1)); + stack->PciResourceMem64Base = base; + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge); + +void xeonsp_pci_domain_scan_bus(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + struct bus *link = dev->link_list; + + printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", + __FILE__, __func__, dev_path(dev)); + while (link != NULL) { + if (link->secondary == 0) { // scan only PSTACK buses + struct device *d; + for (d = link->children; d; d = d->sibling) + pci_probe_dev(d, link, d->path.pci.devfn); + scan_bridges(link); + } else { + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); + } + link = link->next; + } + DEV_FUNC_EXIT(dev); +} + +static void xeonsp_pci_dev_iterator(struct bus *bus, + void (*dev_iterator)(struct device *, void *), + void (*res_iterator)(struct device *, struct resource *, void *), + void *data) +{ + struct device *curdev; + struct resource *res; + + /* Walk through all devices and find which resources they need. */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct bus *link; + + if (!curdev->enabled) + continue; + + if (!curdev->ops || !curdev->ops->read_resources) { + if (curdev->path.type != DEVICE_PATH_APIC) + printk(BIOS_ERR, "%s missing read_resources\n", + dev_path(curdev)); + continue; + } + + if (dev_iterator) + dev_iterator(curdev, data); + + if (res_iterator) { + for (res = curdev->resource_list; res; res = res->next) + res_iterator(curdev, res, data); + } + + /* Read in the resources behind the current device's links. */ + for (link = curdev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); + } +} + +static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) +{ + post_log_path(dev); + dev->ops->read_resources(dev); +} + +static void xeonsp_pci_dev_dummy_func(struct device *dev) +{ +} + +static void xeonsp_reset_pci_op(struct device *dev, void *data) +{ + if (dev->ops) + dev->ops->read_resources = xeonsp_pci_dev_dummy_func; +} + +static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) +{ + for (int i = 0; i < info->no_of_stacks; ++i) { + if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) + return &info->res[i]; + } + return NULL; +} + +static void add_res_to_stack(struct stack_dev_resource **root, + struct device *dev, struct resource *res) +{ + struct stack_dev_resource *cur = *root; + while (cur) { + if (cur->align == res->align || cur->next == NULL) /* equal or last record */ + break; + else if (cur->align > res->align) { + if (cur->next->align < res->align) /* need to insert new record here */ + break; + cur = cur->next; + } else { + break; + } + } + + struct stack_dev_resource *nr; + if (!cur || cur->align != res->align) { /* need to add new record */ + nr = malloc(sizeof(struct stack_dev_resource)); + if (nr == 0) + die("assign_resource_to_stack(): out of memory.\n"); + memset(nr, 0, sizeof(struct stack_dev_resource)); + nr->align = res->align; + if (!cur) { + *root = nr; /* head node */ + } else if (cur->align > nr->align) { + if (cur->next == NULL) { + cur->next = nr; + } else { + nr->next = cur->next; + cur->next = nr; + } + } else { /* insert in the beginning */ + nr->next = cur; + *root = nr; + } + } else { + nr = cur; + } + + assert(nr != NULL && nr->align == res->align); + + struct pci_resource *npr = malloc(sizeof(struct pci_resource)); + if (npr == NULL) + die("%s: out of memory.\n", __func__); + npr->res = res; + npr->dev = dev; + npr->next = NULL; + + if (nr->children == NULL) { + nr->children = npr; + } else { + struct pci_resource *pr = nr->children; + while (pr->next != NULL) + pr = pr->next; + pr->next = npr; + } +} + +static void reserve_dev_resources(STACK_RES *stack, ResType res_type, + struct stack_dev_resource *res_root, struct resource *bridge) +{ + uint8_t align; + uint64_t orig_base, base; + + orig_base = get_resource_base(stack, res_type); + + align = 0; + base = orig_base; + int first = 1; + while (res_root) { /* loop through all devices grouped by alignment requirements */ + struct pci_resource *pr = res_root->children; + while (pr) { + if (first) { + if (bridge) { /* takes highest alignment */ + if (bridge->align < pr->res->align) + bridge->align = pr->res->align; + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + } else { + orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); + } + base = orig_base; + + if (bridge) + bridge->base = base; + pr->res->base = base; + first = 0; + } else { + pr->res->base = ALIGN_UP(base, 1 << pr->res->align); + } + pr->res->limit = pr->res->base + pr->res->size - 1; + base = pr->res->limit + 1; + pr->res->flags |= (IORESOURCE_ASSIGNED); + pr = pr->next; + } + res_root = res_root->next; + } + + if (bridge) { + /* this bridge doesn't have any resources, will set it to default window */ + if (first) { + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + bridge->base = orig_base; + base = orig_base + (1ULL << bridge->gran); + } + + bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; + + bridge->limit = bridge->base + bridge->size - 1; + bridge->flags |= (IORESOURCE_ASSIGNED); + base = bridge->limit + 1; + } + + set_resource_base(stack, res_type, base); +} + +static void reclaim_resource_mem(struct stack_dev_resource *res_root) +{ + while (res_root) { /* loop through all devices grouped by alignment requirements */ + /* free pci_resource */ + struct pci_resource *pr = res_root->children; + while (pr) { + struct pci_resource *dpr = pr; + pr = pr->next; + free(dpr); + } + + /* free stack_dev_resource */ + struct stack_dev_resource *ddr = res_root; + res_root = res_root->next; + free(ddr); + } +} + +static void assign_bridge_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct resource *res; + if (!dev->enabled) + return; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE) || + (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) + continue; + + assign_stack_resources(stack_list, dev, res); + + if (!bridge) + continue; + + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ + if (!(bridge->flags & IORESOURCE_ASSIGNED)) { + bridge->base = res->base; + bridge->limit = res->limit; + bridge->flags |= (IORESOURCE_ASSIGNED); + } else { + /* update bridge range from child bridge range */ + if (res->base < bridge->base) + bridge->base = res->base; + if (res->limit > bridge->limit) + bridge->limit = res->limit; + } + bridge->size = (bridge->limit - bridge->base + 1); + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct bus *bus; + + /* Read in the resources behind the current device's links. */ + for (bus = dev->link_list; bus; bus = bus->next) { + struct device *curdev; + STACK_RES *stack; + + /* get IIO stack for this bus */ + stack = find_stack_for_bus(stack_list, bus->secondary); + assert(stack != NULL); + + /* Assign resources to bridge */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) + assign_bridge_resources(stack_list, curdev, bridge); + + /* Pick non-bridged resources for resource allocation for each resource type */ + ResType res_types[MAX_RES_TYPES] = { + RES_TYPE_IO, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM + }; + + uint8_t no_res_types = MAX_RES_TYPES; + + /* if it is a bridge, only process matching brigge resource type */ + if (bridge) { + res_types[0] = get_res_type(bridge->flags); + no_res_types = 1; + } + + printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, + no_res_types); + + /* Process each resource type */ + for (int rt = 0; rt < no_res_types; ++rt) { + struct stack_dev_resource *res_root = NULL; + printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct resource *res; + printk(BIOS_DEBUG, "%s:%d dev: %s\n", + __func__, __LINE__, dev_path(curdev)); + if (!curdev->enabled) + continue; + + for (res = curdev->resource_list; res; res = res->next) { + printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", + __func__, __LINE__, + dev_path(curdev), res->flags); + if (res->size == 0 || + get_res_type(res->flags) != res_types[rt] || + (res->flags & IORESOURCE_BRIDGE) || + !need_assignment(res->flags)) + continue; + else + add_res_to_stack(&res_root, curdev, res); + } + } + + /* Allocate resources and update bridge range */ + if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { + reserve_dev_resources(stack, res_types[rt], res_root, bridge); + reclaim_resource_mem(res_root); + } + } + } +} + +static void xeonsp_pci_domain_read_resources(struct device *dev) +{ + struct bus *link; + + DEV_FUNC_ENTER(dev); + + pci_domain_read_resources(dev); + + /* + * Walk through all devices in this domain and read resources. + * Since there is no callback when read resource operation is + * complete for all devices, domain read resource function initiates + * read resources for all devices and swaps read resource operation + * with dummy function to avoid warning. + */ + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); + + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); + + struct iiostack_resource stack_info = {0}; + uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); + if (!pci64bit_alloc_flag) { + /* + * Split 32 bit address space between prefetchable and + * non-prefetchable windows + */ + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + STACK_RES *res = &stack_info.res[s]; + uint64_t length = (res->PciResourceMem32Limit - + res->PciResourceMem32Base + 1)/2; + res->PciResourceMem64Limit = res->PciResourceMem32Limit; + res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); + res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; + } + } + + /* assign resources */ + assign_stack_resources(&stack_info, dev, NULL); + + DEV_FUNC_EXIT(dev); +} + +static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) +{ + if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && + !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { + res->flags &= ~IORESOURCE_ASSIGNED; + } +} + +void xeonsp_pci_domain_set_resources(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + + print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); + + /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ + xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); + + /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ + xeonsp_pci_domain_read_resources(dev); + + struct bus *link = dev->link_list; + while (link != NULL) { + assign_resources(link); + link = link->next; + } + + print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); + + DEV_FUNC_EXIT(dev); +} + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info = {0}; + + DEV_FUNC_ENTER(dev); + + get_iiostack_info(&stack_info); + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + /* only non zero bus no. needs to be enumerated */ + if (stack_info.res[s].BusBase == 0) + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == NULL) + die("%s: out of memory.\n", __func__); + memset(iiostack_bus, 0, sizeof(*iiostack_bus)); + memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); + iiostack_bus->secondary = stack_info.res[s].BusBase; + iiostack_bus->subordinate = stack_info.res[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", + dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } + + DEV_FUNC_EXIT(dev); +} diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 6d2dfba..1e2be19 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,498 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/ioapic.h> -#include <assert.h> #include <console/console.h> -#include <console/debug.h> #include <cpu/x86/lapic.h> #include <device/pci.h> -#include <fsp/api.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> -#include <post.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/cpu.h> #include <soc/ramstage.h> -#include <soc/pm.h> #include <soc/soc_util.h> -#include <stdlib.h> - -/* C620 IOAPIC has 120 redirection entries */ -#define C620_IOAPIC_REDIR_ENTRIES 120 - -struct pci_resource { - struct device *dev; - struct resource *res; - struct pci_resource *next; -}; - -struct stack_dev_resource { - uint8_t align; - struct pci_resource *children; - struct stack_dev_resource *next; -}; - -typedef enum { - RES_TYPE_IO = 0, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM, - MAX_RES_TYPES -} ResType; - -static ResType get_res_type(uint64_t flags) -{ - if (flags & IORESOURCE_IO) - return RES_TYPE_IO; - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_PREFETCH) { - printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); - return RES_TYPE_PREF_MEM; - } - /* both 64-bit and 32-bit use below 4GB address space */ - return RES_TYPE_NONPREF_MEM; - } - printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); - die("Invalida resource type"); -} - -static bool need_assignment(uint64_t flags) -{ - if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED)) - return false; - else - return true; -} - -static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) -{ - if (res_type == RES_TYPE_IO) { - assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); - return stack->PciResourceIoBase; - } - if (res_type == RES_TYPE_NONPREF_MEM) { - assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); - return stack->PciResourceMem32Base; - } - assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); - return stack->PciResourceMem64Base; -} - -static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) -{ - if (res_type == RES_TYPE_IO) { - assert(base <= (stack->PciResourceIoLimit + 1)); - stack->PciResourceIoBase = base; - } else if (res_type == RES_TYPE_NONPREF_MEM) { - assert(base <= (stack->PciResourceMem32Limit + 1)); - stack->PciResourceMem32Base = base; - } else { - assert(base <= (stack->PciResourceMem64Limit + 1)); - stack->PciResourceMem64Base = base; - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge); - -static void xeonsp_cpx_pci_domain_scan_bus(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - struct bus *link = dev->link_list; - - printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", - __FILE__, __func__, dev_path(dev)); - while (link != NULL) { - if (link->secondary == 0) { // scan only PSTACK buses - struct device *d; - for (d = link->children; d; d = d->sibling) - pci_probe_dev(d, link, d->path.pci.devfn); - scan_bridges(link); - } else { - pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - } - link = link->next; - } - DEV_FUNC_EXIT(dev); -} - -static void xeonsp_pci_dev_iterator(struct bus *bus, - void (*dev_iterator)(struct device *, void *), - void (*res_iterator)(struct device *, struct resource *, void *), - void *data) -{ - struct device *curdev; - struct resource *res; - - /* Walk through all devices and find which resources they need. */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - - if (!curdev->enabled) - continue; - - if (!curdev->ops || !curdev->ops->read_resources) { - if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); - continue; - } - - if (dev_iterator) - dev_iterator(curdev, data); - - if (res_iterator) { - for (res = curdev->resource_list; res; res = res->next) - res_iterator(curdev, res, data); - } - - /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); - } -} - -static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) -{ - post_log_path(dev); - dev->ops->read_resources(dev); -} - -static void xeonsp_pci_dev_dummy_func(struct device *dev) -{ -} - -static void xeonsp_reset_pci_op(struct device *dev, void *data) -{ - if (dev->ops) - dev->ops->read_resources = xeonsp_pci_dev_dummy_func; -} - -static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) -{ - for (int i = 0; i < info->no_of_stacks; ++i) { - if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) - return &info->res[i]; - } - return NULL; -} - -static void add_res_to_stack(struct stack_dev_resource **root, - struct device *dev, struct resource *res) -{ - struct stack_dev_resource *cur = *root; - while (cur) { - if (cur->align == res->align || cur->next == NULL) /* equal or last record */ - break; - else if (cur->align > res->align) { - if (cur->next->align < res->align) /* need to insert new record here */ - break; - cur = cur->next; - } else { - break; - } - } - - struct stack_dev_resource *nr; - if (!cur || cur->align != res->align) { /* need to add new record */ - nr = malloc(sizeof(struct stack_dev_resource)); - if (nr == 0) - die("assign_resource_to_stack(): out of memory.\n"); - memset(nr, 0, sizeof(struct stack_dev_resource)); - nr->align = res->align; - if (!cur) { - *root = nr; /* head node */ - } else if (cur->align > nr->align) { - if (cur->next == NULL) { - cur->next = nr; - } else { - nr->next = cur->next; - cur->next = nr; - } - } else { /* insert in the beginning */ - nr->next = cur; - *root = nr; - } - } else { - nr = cur; - } - - assert(nr != NULL && nr->align == res->align); - - struct pci_resource *npr = malloc(sizeof(struct pci_resource)); - if (npr == NULL) - die("%s: out of memory.\n", __func__); - npr->res = res; - npr->dev = dev; - npr->next = NULL; - - if (nr->children == NULL) { - nr->children = npr; - } else { - struct pci_resource *pr = nr->children; - while (pr->next != NULL) - pr = pr->next; - pr->next = npr; - } -} - -static void reserve_dev_resources(STACK_RES *stack, ResType res_type, - struct stack_dev_resource *res_root, struct resource *bridge) -{ - uint8_t align; - uint64_t orig_base, base; - - orig_base = get_resource_base(stack, res_type); - - align = 0; - base = orig_base; - int first = 1; - while (res_root) { /* loop through all devices grouped by alignment requirements */ - struct pci_resource *pr = res_root->children; - while (pr) { - if (first) { - if (bridge) { /* takes highest alignment */ - if (bridge->align < pr->res->align) - bridge->align = pr->res->align; - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - } else { - orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); - } - base = orig_base; - - if (bridge) - bridge->base = base; - pr->res->base = base; - first = 0; - } else { - pr->res->base = ALIGN_UP(base, 1 << pr->res->align); - } - pr->res->limit = pr->res->base + pr->res->size - 1; - base = pr->res->limit + 1; - pr->res->flags |= (IORESOURCE_ASSIGNED); - pr = pr->next; - } - res_root = res_root->next; - } - - if (bridge) { - /* this bridge doesn't have any resources, will set it to default window */ - if (first) { - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - bridge->base = orig_base; - base = orig_base + (1ULL << bridge->gran); - } - - bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; - - bridge->limit = bridge->base + bridge->size - 1; - bridge->flags |= (IORESOURCE_ASSIGNED); - base = bridge->limit + 1; - } - - set_resource_base(stack, res_type, base); -} - -static void reclaim_resource_mem(struct stack_dev_resource *res_root) -{ - while (res_root) { /* loop through all devices grouped by alignment requirements */ - /* free pci_resource */ - struct pci_resource *pr = res_root->children; - while (pr) { - struct pci_resource *dpr = pr; - pr = pr->next; - free(dpr); - } - - /* free stack_dev_resource */ - struct stack_dev_resource *ddr = res_root; - res_root = res_root->next; - free(ddr); - } -} - -static void assign_bridge_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct resource *res; - if (!dev->enabled) - return; - - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) - continue; - - assign_stack_resources(stack_list, dev, res); - - if (!bridge) - continue; - - /* for 1st time update, overlading IORESOURCE_ASSIGNED */ - if (!(bridge->flags & IORESOURCE_ASSIGNED)) { - bridge->base = res->base; - bridge->limit = res->limit; - bridge->flags |= (IORESOURCE_ASSIGNED); - } else { - /* update bridge range from child bridge range */ - if (res->base < bridge->base) - bridge->base = res->base; - if (res->limit > bridge->limit) - bridge->limit = res->limit; - } - bridge->size = (bridge->limit - bridge->base + 1); - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct bus *bus; - - /* Read in the resources behind the current device's links. */ - for (bus = dev->link_list; bus; bus = bus->next) { - struct device *curdev; - STACK_RES *stack; - - /* get IIO stack for this bus */ - stack = find_stack_for_bus(stack_list, bus->secondary); - assert(stack != NULL); - - /* Assign resources to bridge */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) - assign_bridge_resources(stack_list, curdev, bridge); - - /* Pick non-bridged resources for resource allocation for each resource type */ - ResType res_types[MAX_RES_TYPES] = { - RES_TYPE_IO, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM - }; - - uint8_t no_res_types = MAX_RES_TYPES; - - /* if it is a bridge, only process matching brigge resource type */ - if (bridge) { - res_types[0] = get_res_type(bridge->flags); - no_res_types = 1; - } - - printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, - no_res_types); - - /* Process each resource type */ - for (int rt = 0; rt < no_res_types; ++rt) { - struct stack_dev_resource *res_root = NULL; - printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct resource *res; - printk(BIOS_DEBUG, "%s:%d dev: %s\n", - __func__, __LINE__, dev_path(curdev)); - if (!curdev->enabled) - continue; - - for (res = curdev->resource_list; res; res = res->next) { - printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", - __func__, __LINE__, - dev_path(curdev), res->flags); - if (res->size == 0 || - get_res_type(res->flags) != res_types[rt] || - (res->flags & IORESOURCE_BRIDGE) || - !need_assignment(res->flags)) - continue; - else - add_res_to_stack(&res_root, curdev, res); - } - } - - /* Allocate resources and update bridge range */ - if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, res_types[rt], res_root, bridge); - reclaim_resource_mem(res_root); - } - } - } -} - -static void xeonsp_pci_domain_read_resources(struct device *dev) -{ - struct bus *link; - - DEV_FUNC_ENTER(dev); - - pci_domain_read_resources(dev); - - /* - * Walk through all devices in this domain and read resources. - * Since there is no callback when read resource operation is - * complete for all devices, domain read resource function initiates - * read resources for all devices and swaps read resource operation - * with dummy function to avoid warning. - */ - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); - - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - - struct iiostack_resource stack_info = {0}; - uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); - if (!pci64bit_alloc_flag) { - /* - * Split 32 bit address space between prefetchable and - * non-prefetchable windows - */ - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - STACK_RES *res = &stack_info.res[s]; - uint64_t length = (res->PciResourceMem32Limit - - res->PciResourceMem32Base + 1)/2; - res->PciResourceMem64Limit = res->PciResourceMem32Limit; - res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); - res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; - } - } - - /* assign resources */ - assign_stack_resources(&stack_info, dev, NULL); - - DEV_FUNC_EXIT(dev); -} - -static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) -{ - if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && - !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { - res->flags &= ~IORESOURCE_ASSIGNED; - } -} - -static void xeonsp_cpx_pci_domain_set_resources(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - - print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); - - /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ - xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); - - /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ - xeonsp_pci_domain_read_resources(dev); - - struct bus *link = dev->link_list; - while (link != NULL) { - assign_resources(link); - link = link->next; - } - - print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); - - DEV_FUNC_EXIT(dev); -} /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { - mainboard_silicon_init_params(silupd); } @@ -507,8 +29,8 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, - .set_resources = &xeonsp_cpx_pci_domain_set_resources, - .scan_bus = &xeonsp_cpx_pci_domain_scan_bus, + .set_resources = &xeonsp_pci_domain_set_resources, + .scan_bus = &xeonsp_pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = soc_acpi_name @@ -522,45 +44,6 @@ .acpi_fill_ssdt = generate_cpu_entries, }; -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ -static void attach_iio_stacks(struct device *dev) -{ - struct bus *iiostack_bus; - struct iiostack_resource stack_info = {0}; - - DEV_FUNC_ENTER(dev); - - get_iiostack_info(&stack_info); - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - /* only non zero bus no. needs to be enumerated */ - if (stack_info.res[s].BusBase == 0) - continue; - - iiostack_bus = malloc(sizeof(struct bus)); - if (iiostack_bus == NULL) - die("%s: out of memory.\n", __func__); - memset(iiostack_bus, 0, sizeof(*iiostack_bus)); - memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); - iiostack_bus->secondary = stack_info.res[s].BusBase; - iiostack_bus->subordinate = stack_info.res[s].BusBase; - iiostack_bus->dev = NULL; - iiostack_bus->children = NULL; - iiostack_bus->next = NULL; - iiostack_bus->link_num = 1; - - if (dev->link_list == NULL) { - dev->link_list = iiostack_bus; - } else { - struct bus *nlink = dev->link_list; - while (nlink->next != NULL) - nlink = nlink->next; - nlink->next = iiostack_bus; - } - } - - DEV_FUNC_EXIT(dev); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h new file mode 100644 index 0000000..339da07 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CHIP_COMMON_H_ +#define _CHIP_COMMON_H_ + +void xeonsp_pci_domain_set_resources(struct device *dev); +void xeonsp_pci_domain_scan_bus(struct device *dev); +void attach_iio_stacks(struct device *dev); + +#endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index a19a364..4a3ce36 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -1,484 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <cbfs.h> -#include <assert.h> #include <console/console.h> -#include <console/debug.h> -#include <post.h> #include <device/pci.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/ramstage.h> #include <soc/soc_util.h> -struct pci_resource { - struct device *dev; - struct resource *res; - struct pci_resource *next; -}; - -struct stack_dev_resource { - uint8_t align; - struct pci_resource *children; - struct stack_dev_resource *next; -}; - -typedef enum { - RES_TYPE_IO = 0, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM, - MAX_RES_TYPES -} ResType; - -static ResType get_res_type(uint64_t flags) -{ - if (flags & IORESOURCE_IO) - return RES_TYPE_IO; - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_PREFETCH) { - printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); - return RES_TYPE_PREF_MEM; - } - /* both 64-bit and 32-bit use below 4GB address space */ - return RES_TYPE_NONPREF_MEM; - } - printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); - die("Invalida resource type"); -} - -static bool need_assignment(uint64_t flags) -{ - if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED)) - return false; - else - return true; -} - -static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) -{ - if (res_type == RES_TYPE_IO) { - assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); - return stack->PciResourceIoBase; - } - if (res_type == RES_TYPE_NONPREF_MEM) { - assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); - return stack->PciResourceMem32Base; - } - assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); - return stack->PciResourceMem64Base; -} - -static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) -{ - if (res_type == RES_TYPE_IO) { - assert(base <= (stack->PciResourceIoLimit + 1)); - stack->PciResourceIoBase = base; - } else if (res_type == RES_TYPE_NONPREF_MEM) { - assert(base <= (stack->PciResourceMem32Limit + 1)); - stack->PciResourceMem32Base = base; - } else { - assert(base <= (stack->PciResourceMem64Limit + 1)); - stack->PciResourceMem64Base = base; - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge); - -static void xeonsp_pci_domain_scan_bus(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - struct bus *link = dev->link_list; - - printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", - __FILE__, __func__, dev_path(dev)); - while (link != NULL) { - if (link->secondary == 0) { // scan only PSTACK buses - struct device *d; - for (d = link->children; d; d = d->sibling) - pci_probe_dev(d, link, d->path.pci.devfn); - scan_bridges(link); - } else { - pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - } - link = link->next; - } - DEV_FUNC_EXIT(dev); -} - -static void xeonsp_pci_dev_iterator(struct bus *bus, - void (*dev_iterator)(struct device *, void *), - void (*res_iterator)(struct device *, struct resource *, void *), - void *data) -{ - struct device *curdev; - struct resource *res; - - /* Walk through all devices and find which resources they need. */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - - if (!curdev->enabled) - continue; - - if (!curdev->ops || !curdev->ops->read_resources) { - if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); - continue; - } - - if (dev_iterator) - dev_iterator(curdev, data); - - if (res_iterator) { - for (res = curdev->resource_list; res; res = res->next) - res_iterator(curdev, res, data); - } - - /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); - } -} - -static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) -{ - post_log_path(dev); - dev->ops->read_resources(dev); -} - -static void xeonsp_pci_dev_dummy_func(struct device *dev) -{ -} - -static void xeonsp_reset_pci_op(struct device *dev, void *data) -{ - if (dev->ops) - dev->ops->read_resources = xeonsp_pci_dev_dummy_func; -} - -static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) -{ - for (int i = 0; i < info->no_of_stacks; ++i) { - if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) - return &info->res[i]; - } - return NULL; -} - -static void add_res_to_stack(struct stack_dev_resource **root, - struct device *dev, struct resource *res) -{ - struct stack_dev_resource *cur = *root; - while (cur) { - if (cur->align == res->align || cur->next == NULL) /* equal or last record */ - break; - else if (cur->align > res->align) { - if (cur->next->align < res->align) /* need to insert new record here */ - break; - cur = cur->next; - } else { - break; - } - } - - struct stack_dev_resource *nr; - if (!cur || cur->align != res->align) { /* need to add new record */ - nr = malloc(sizeof(struct stack_dev_resource)); - if (nr == 0) - die("assign_resource_to_stack(): out of memory.\n"); - memset(nr, 0, sizeof(struct stack_dev_resource)); - nr->align = res->align; - if (!cur) { - *root = nr; /* head node */ - } else if (cur->align > nr->align) { - if (cur->next == NULL) { - cur->next = nr; - } else { - nr->next = cur->next; - cur->next = nr; - } - } else { /* insert in the beginning */ - nr->next = cur; - *root = nr; - } - } else { - nr = cur; - } - - assert(nr != NULL && nr->align == res->align); - - struct pci_resource *npr = malloc(sizeof(struct pci_resource)); - if (npr == NULL) - die("%s: out of memory.\n", __func__); - npr->res = res; - npr->dev = dev; - npr->next = NULL; - - if (nr->children == NULL) { - nr->children = npr; - } else { - struct pci_resource *pr = nr->children; - while (pr->next != NULL) - pr = pr->next; - pr->next = npr; - } -} - -static void reserve_dev_resources(STACK_RES *stack, ResType res_type, - struct stack_dev_resource *res_root, struct resource *bridge) -{ - uint8_t align; - uint64_t orig_base, base; - - orig_base = get_resource_base(stack, res_type); - - align = 0; - base = orig_base; - int first = 1; - while (res_root) { /* loop through all devices grouped by alignment requirements */ - struct pci_resource *pr = res_root->children; - while (pr) { - if (first) { - if (bridge) { /* takes highest alignment */ - if (bridge->align < pr->res->align) - bridge->align = pr->res->align; - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - } else { - orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); - } - base = orig_base; - - if (bridge) - bridge->base = base; - pr->res->base = base; - first = 0; - } else { - pr->res->base = ALIGN_UP(base, 1 << pr->res->align); - } - pr->res->limit = pr->res->base + pr->res->size - 1; - base = pr->res->limit + 1; - pr->res->flags |= (IORESOURCE_ASSIGNED); - pr = pr->next; - } - res_root = res_root->next; - } - - if (bridge) { - /* this bridge doesn't have any resources, will set it to default window */ - if (first) { - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - bridge->base = orig_base; - base = orig_base + (1ULL << bridge->gran); - } - - bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; - - bridge->limit = bridge->base + bridge->size - 1; - bridge->flags |= (IORESOURCE_ASSIGNED); - base = bridge->limit + 1; - } - - set_resource_base(stack, res_type, base); -} - -static void reclaim_resource_mem(struct stack_dev_resource *res_root) -{ - while (res_root) { /* loop through all devices grouped by alignment requirements */ - /* free pci_resource */ - struct pci_resource *pr = res_root->children; - while (pr) { - struct pci_resource *dpr = pr; - pr = pr->next; - free(dpr); - } - - /* free stack_dev_resource */ - struct stack_dev_resource *ddr = res_root; - res_root = res_root->next; - free(ddr); - } -} - -static void assign_bridge_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct resource *res; - if (!dev->enabled) - return; - - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) - continue; - - assign_stack_resources(stack_list, dev, res); - - if (!bridge) - continue; - - /* for 1st time update, overlading IORESOURCE_ASSIGNED */ - if (!(bridge->flags & IORESOURCE_ASSIGNED)) { - bridge->base = res->base; - bridge->limit = res->limit; - bridge->flags |= (IORESOURCE_ASSIGNED); - } else { - /* update bridge range from child bridge range */ - if (res->base < bridge->base) - bridge->base = res->base; - if (res->limit > bridge->limit) - bridge->limit = res->limit; - } - bridge->size = (bridge->limit - bridge->base + 1); - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct bus *bus; - - /* Read in the resources behind the current device's links. */ - for (bus = dev->link_list; bus; bus = bus->next) { - struct device *curdev; - STACK_RES *stack; - - /* get IIO stack for this bus */ - stack = find_stack_for_bus(stack_list, bus->secondary); - assert(stack != NULL); - - /* Assign resources to bridge */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) - assign_bridge_resources(stack_list, curdev, bridge); - - /* Pick non-bridged resources for resource allocation for each resource type */ - ResType res_types[MAX_RES_TYPES] = { - RES_TYPE_IO, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM - }; - - uint8_t no_res_types = MAX_RES_TYPES; - - /* if it is a bridge, only process matching brigge resource type */ - if (bridge) { - res_types[0] = get_res_type(bridge->flags); - no_res_types = 1; - } - - printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, - no_res_types); - - /* Process each resource type */ - for (int rt = 0; rt < no_res_types; ++rt) { - struct stack_dev_resource *res_root = NULL; - printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct resource *res; - printk(BIOS_DEBUG, "%s:%d dev: %s\n", - __func__, __LINE__, dev_path(curdev)); - if (!curdev->enabled) - continue; - - for (res = curdev->resource_list; res; res = res->next) { - printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", - __func__, __LINE__, - dev_path(curdev), res->flags); - if (res->size == 0 || - get_res_type(res->flags) != res_types[rt] || - (res->flags & IORESOURCE_BRIDGE) || - !need_assignment(res->flags)) - continue; - else - add_res_to_stack(&res_root, curdev, res); - } - } - - /* Allocate resources and update bridge range */ - if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, res_types[rt], res_root, bridge); - reclaim_resource_mem(res_root); - } - } - } -} - -static void xeonsp_pci_domain_read_resources(struct device *dev) -{ - struct bus *link; - - DEV_FUNC_ENTER(dev); - - pci_domain_read_resources(dev); - - /* - * Walk through all devices in this domain and read resources. - * Since there is no callback when read resource operation is - * complete for all devices, domain read resource function initiates - * read resources for all devices and swaps read resource operation - * with dummy function to avoid warning. - */ - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); - - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - - struct iiostack_resource stack_info = {0}; - uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); - if (!pci64bit_alloc_flag) { - /* - * Split 32 bit address space between prefetchable and - * non-prefetchable windows - */ - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - STACK_RES *res = &stack_info.res[s]; - uint64_t length = (res->PciResourceMem32Limit - - res->PciResourceMem32Base + 1)/2; - res->PciResourceMem64Limit = res->PciResourceMem32Limit; - res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); - res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; - } - } - - /* assign resources */ - assign_stack_resources(&stack_info, dev, NULL); - - DEV_FUNC_EXIT(dev); -} - -static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) -{ - if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && - !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { - res->flags &= ~IORESOURCE_ASSIGNED; - } -} - -static void xeonsp_pci_domain_set_resources(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - - print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); - - /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ - xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); - - /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ - xeonsp_pci_domain_read_resources(dev); - - struct bus *link = dev->link_list; - while (link != NULL) { - assign_resources(link); - link = link->next; - } - - print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); - - DEV_FUNC_EXIT(dev); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &xeonsp_pci_domain_set_resources, @@ -498,54 +27,6 @@ #endif }; -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ -static void attach_iio_stacks(struct device *dev) -{ - struct bus *iiostack_bus; - struct device dummy; - struct iiostack_resource stack_info = {0}; - - DEV_FUNC_ENTER(dev); - - get_iiostack_info(&stack_info); - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - /* only non zero bus no. needs to be enumerated */ - if (stack_info.res[s].BusBase == 0) - continue; - - iiostack_bus = malloc(sizeof(struct bus)); - if (iiostack_bus == NULL) - die("%s: out of memory.\n", __func__); - memset(iiostack_bus, 0, sizeof(*iiostack_bus)); - memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); - iiostack_bus->secondary = stack_info.res[s].BusBase; - iiostack_bus->subordinate = stack_info.res[s].BusBase; - iiostack_bus->dev = NULL; - iiostack_bus->children = NULL; - iiostack_bus->next = NULL; - iiostack_bus->link_num = 1; - - dummy.bus = iiostack_bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = 0; - uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (id == 0xffffffff) - printk(BIOS_WARNING, "IIO Stack device %s not visible\n", - dev_path(&dummy)); - - if (dev->link_list == NULL) { - dev->link_list = iiostack_bus; - } else { - struct bus *nlink = dev->link_list; - while (nlink->next != NULL) - nlink = nlink->next; - nlink->next = iiostack_bus; - } - } - - DEV_FUNC_EXIT(dev); -} - static void soc_enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -570,10 +51,6 @@ set_bios_init_completion(); } -static void soc_silicon_init_params(FSPS_UPD *silupd) -{ -} - void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { const struct microcode *microcode_file; @@ -590,7 +67,6 @@ (uint32_t)microcode_len; } - soc_silicon_init_params(silupd); mainboard_silicon_init_params(silupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c Gerrit-Change-Number: 46478 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource
by Marc Jones (Code Review) 30 Oct '20

30 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46308 ) Change subject: soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource ...................................................................... soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource Use the simpler pci_domain_read_resource for the stacks. This makes it the same as the cpx function and easire to merge later. Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/chip.c 1 file changed, 14 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46308/1 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 529e07a..a19a364 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -404,44 +404,6 @@ } } -static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data) -{ - STACK_RES *stack = (STACK_RES *) data; - if (!(res->flags & IORESOURCE_FIXED)) - return; - - uint64_t base, limit; - if (res->flags & IORESOURCE_IO) { - base = stack->PciResourceIoBase; - limit = stack->PciResourceIoLimit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - base = stack->PciResourceMem64Base; - limit = stack->PciResourceMem64Limit; - } else { - base = stack->PciResourceMem32Base; - limit = stack->PciResourceMem32Limit; - } - - if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */ - return; - - if (res->limit > limit) /* resource end is out of limit */ - limit = res->base - 1; - else - base = res->base + res->size; - - if (res->flags & IORESOURCE_IO) { - stack->PciResourceIoBase = base; - stack->PciResourceIoLimit = limit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - stack->PciResourceMem64Base = base; - stack->PciResourceMem64Limit = limit; - } else { - stack->PciResourceMem32Base = base; - stack->PciResourceMem32Limit = limit; - } -} - static void xeonsp_pci_domain_read_resources(struct device *dev) { struct bus *link; @@ -463,18 +425,21 @@ for (link = dev->link_list; link; link = link->next) xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - /* - * 1. group devices, resources for each stack - * 2. order resources in descending order of requested resource allocation sizes - */ struct iiostack_resource stack_info = {0}; - get_iiostack_info(&stack_info); - - /* constrain stack window */ - for (link = dev->link_list; link; link = link->next) { - STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary); - assert(stack != 0); - xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack); + uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); + if (!pci64bit_alloc_flag) { + /* + * Split 32 bit address space between prefetchable and + * non-prefetchable windows + */ + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + STACK_RES *res = &stack_info.res[s]; + uint64_t length = (res->PciResourceMem32Limit - + res->PciResourceMem32Base + 1)/2; + res->PciResourceMem64Limit = res->PciResourceMem32Limit; + res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); + res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; + } } /* assign resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827 Gerrit-Change-Number: 46308 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/xeon_sp/skx: Add resource allocator helpers
by Marc Jones (Code Review) 30 Oct '20

30 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46306 ) Change subject: soc/intel/xeon_sp/skx: Add resource allocator helpers ...................................................................... soc/intel/xeon_sp/skx: Add resource allocator helpers Add and use resource allocator helper functions. This clean up matches CPX and will help with merging in the future. Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/chip.c 1 file changed, 90 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/46306/1 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index faa455a..529e07a 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -22,6 +22,66 @@ struct stack_dev_resource *next; }; +typedef enum { + RES_TYPE_IO = 0, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM, + MAX_RES_TYPES +} ResType; + +static ResType get_res_type(uint64_t flags) +{ + if (flags & IORESOURCE_IO) + return RES_TYPE_IO; + if (flags & IORESOURCE_MEM) { + if (flags & IORESOURCE_PREFETCH) { + printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); + return RES_TYPE_PREF_MEM; + } + /* both 64-bit and 32-bit use below 4GB address space */ + return RES_TYPE_NONPREF_MEM; + } + printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); + die("Invalida resource type"); +} + +static bool need_assignment(uint64_t flags) +{ + if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED)) + return false; + else + return true; +} + +static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) +{ + if (res_type == RES_TYPE_IO) { + assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); + return stack->PciResourceIoBase; + } + if (res_type == RES_TYPE_NONPREF_MEM) { + assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); + return stack->PciResourceMem32Base; + } + assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); + return stack->PciResourceMem64Base; +} + +static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) +{ + if (res_type == RES_TYPE_IO) { + assert(base <= (stack->PciResourceIoLimit + 1)); + stack->PciResourceIoBase = base; + } else if (res_type == RES_TYPE_NONPREF_MEM) { + assert(base <= (stack->PciResourceMem32Limit + 1)); + stack->PciResourceMem32Base = base; + } else { + assert(base <= (stack->PciResourceMem64Limit + 1)); + stack->PciResourceMem64Base = base; + } +} + static void assign_stack_resources(struct iiostack_resource *stack_list, struct device *dev, struct resource *bridge); @@ -166,19 +226,13 @@ } } -static void reserve_dev_resources(STACK_RES *stack, unsigned long res_type, +static void reserve_dev_resources(STACK_RES *stack, ResType res_type, struct stack_dev_resource *res_root, struct resource *bridge) { uint8_t align; uint64_t orig_base, base; - if (res_type & IORESOURCE_IO) - orig_base = stack->PciResourceIoBase; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - orig_base = stack->PciResourceMem64Base; - else - orig_base = stack->PciResourceMem32Base; + orig_base = get_resource_base(stack, res_type); align = 0; base = orig_base; @@ -226,14 +280,7 @@ base = bridge->limit + 1; } - /* update new limits */ - if (res_type & IORESOURCE_IO) - stack->PciResourceIoBase = base; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - stack->PciResourceMem64Base = base; - else - stack->PciResourceMem32Base = base; + set_resource_base(stack, res_type, base); } static void reclaim_resource_mem(struct stack_dev_resource *res_root) @@ -263,15 +310,14 @@ for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64)) != - (res->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) + (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) continue; assign_stack_resources(stack_list, dev, res); + if (!bridge) continue; + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ if (!(bridge->flags & IORESOURCE_ASSIGNED)) { bridge->base = res->base; @@ -307,36 +353,42 @@ assign_bridge_resources(stack_list, curdev, bridge); /* Pick non-bridged resources for resource allocation for each resource type */ - unsigned long flags[5] = {IORESOURCE_IO, IORESOURCE_MEM, - (IORESOURCE_PCI64|IORESOURCE_MEM), (IORESOURCE_MEM|IORESOURCE_PREFETCH), - (IORESOURCE_PCI64|IORESOURCE_MEM|IORESOURCE_PREFETCH)}; - uint8_t no_res_types = 5; + ResType res_types[MAX_RES_TYPES] = { + RES_TYPE_IO, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM + }; + + uint8_t no_res_types = MAX_RES_TYPES; + + /* if it is a bridge, only process matching brigge resource type */ if (bridge) { - flags[0] = bridge->flags & - (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); - if ((bridge->flags & IORESOURCE_MEM) && - (bridge->flags & IORESOURCE_PREFETCH)) - flags[0] |= IORESOURCE_PCI64; + res_types[0] = get_res_type(bridge->flags); no_res_types = 1; } + printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, + no_res_types); + /* Process each resource type */ for (int rt = 0; rt < no_res_types; ++rt) { struct stack_dev_resource *res_root = NULL; - + printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); for (curdev = bus->children; curdev; curdev = curdev->sibling) { struct resource *res; + printk(BIOS_DEBUG, "%s:%d dev: %s\n", + __func__, __LINE__, dev_path(curdev)); if (!curdev->enabled) continue; for (res = curdev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_BRIDGE) || (res->flags & - (IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_ASSIGNED) - ) || ((res->flags & (IORESOURCE_IO | - IORESOURCE_MEM | IORESOURCE_PCI64 - | IORESOURCE_PREFETCH)) - != flags[rt]) || res->size == 0) + printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", + __func__, __LINE__, + dev_path(curdev), res->flags); + if (res->size == 0 || + get_res_type(res->flags) != res_types[rt] || + (res->flags & IORESOURCE_BRIDGE) || + !need_assignment(res->flags)) continue; else add_res_to_stack(&res_root, curdev, res); @@ -345,7 +397,7 @@ /* Allocate resources and update bridge range */ if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, flags[rt], res_root, bridge); + reserve_dev_resources(stack, res_types[rt], res_root, bridge); reclaim_resource_mem(res_root); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb Gerrit-Change-Number: 46306 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[4.11_branch]: ocp/monolake: Simplify mainboard dsdt.asl
by Marc Jones (Code Review) 30 Oct '20

30 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46985 ) Change subject: ocp/monolake: Simplify mainboard dsdt.asl ...................................................................... ocp/monolake: Simplify mainboard dsdt.asl Include the soc uncore.asl for the uncore irq routing. Generates the same asl. Change-Id: I2062520a06626f86fb0d78e8b23533f987b37ca0 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/monolake/dsdt.asl 1 file changed, 1 insertion(+), 250 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46985/1 diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..0d9e90d 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -38,256 +38,7 @@ #include <acpi/pcie1.asl> } - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - }) - - Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, - }) - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } - } + #include <acpi/uncore.asl> } #include "acpi/mainboard.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/46985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I2062520a06626f86fb0d78e8b23533f987b37ca0 Gerrit-Change-Number: 46985 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/volteer: Update gpio and devicetree
by Chen Wisley (Code Review) 30 Oct '20

30 Oct '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46771 ) Change subject: mb/google/volteer: Update gpio and devicetree ...................................................................... mb/google/volteer: Update gpio and devicetree Update gpio and devicetree BUG=170604353 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I2765dc63e447329ef98387ab0e7907c899259152 --- M src/mainboard/google/volteer/variants/elemi/Makefile.inc A src/mainboard/google/volteer/variants/elemi/gpio.c M src/mainboard/google/volteer/variants/elemi/overridetree.cb 3 files changed, 356 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46771/1 diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc index 9064208..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c new file mode 100644 index 0000000..371a22a --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBCLK ==> EMMC_CLKREQ_ODL*/ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : EMMC_PE_WAKE_ODL*/ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : EMMC_PERST_L*/ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_NC(GPP_C5, DN_20K), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 32204c5..1d7c952 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,6 +1,133 @@ chip soc/intel/tigerlake - device domain 0 on - end + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2765dc63e447329ef98387ab0e7907c899259152 Gerrit-Change-Number: 46771 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/broadwell: Relocate CPU .c files
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41927 ) Change subject: soc/intel/broadwell: Relocate CPU .c files ...................................................................... soc/intel/broadwell: Relocate CPU .c files Haswell and Broadwell are rather similar, and could share some code. However, Haswell is split into cpu/northbridge/southbridge folders, whereas all of Broadwell is crammed into the soc namespace. We will split Broadwell and then fuse it with Haswell in multiple commits. To begin with, move Broadwell source code files into a folder under the corresponding cpu scope, without changing any of their contents. Note that headers and Kconfig still reside inside the soc namespace. This is temporary and will be accounted for in subsequent commits. Change-Id: Ic2f719ea7585ec724c52950e76e5f52bdc1d6c43 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Makefile.inc A src/cpu/intel/broadwell/acpi.c R src/cpu/intel/broadwell/bootblock.c R src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/chip.c R src/cpu/intel/broadwell/cpu.c R src/cpu/intel/broadwell/cpu_info.c R src/cpu/intel/broadwell/romstage.c R src/cpu/intel/broadwell/smmrelocate.c R src/cpu/intel/broadwell/tsc_freq.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/Makefile.inc 13 files changed, 667 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41927/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19..21dc291 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc new file mode 100644 index 0000000..453b879 --- /dev/null +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -0,0 +1,38 @@ +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/intel/common + +bootblock-y += bootblock.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S + +romstage-y += ../../../cpu/intel/car/romstage.c +romstage-y += broadwell_early_init.c + +ramstage-y += acpi.c + +ramstage-y += chip.c + +ramstage-y += cpu.c +ramstage-y += cpu_info.c +smm-y += cpu_info.c + +romstage-y += romstage.c + +ramstage-y += smmrelocate.c + +bootblock-y += tsc_freq.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-y += tsc_freq.c +postcar-y += tsc_freq.c +verstage-y += tsc_freq.c + +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S + +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c new file mode 100644 index 0000000..316b85a --- /dev/null +++ b/src/cpu/intel/broadwell/acpi.c @@ -0,0 +1,628 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <device/pci_ops.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cpu/intel/turbo.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/systemagent.h> +#include <soc/intel/broadwell/chip.h> +#include <intelblocks/cpulib.h> + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +static int cstate_set_non_s0ix[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT +}; + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG(CHROMEOS) + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); +#if CONFIG(EC_GOOGLE_CHROMEEC) + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static void generate_C_state_entries(void) +{ + acpi_cstate_t map[3]; + int *set; + int i; + + config_t *config = config_of_soc(); + + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix; + + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CPU_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; + + /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar + && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* VTVC0BAR has to be set, enabled, and in 32-bit space */ + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci >= 20) + flags |= MP_IRQ_POLARITY_LOW; + else + flags |= MP_IRQ_POLARITY_HIGH; + + /* SCI */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); + + return current; +} diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/cpu/intel/broadwell/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/cpu.c rename to src/cpu/intel/broadwell/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/cpu/intel/broadwell/broadwell_early_init.c similarity index 100% rename from src/soc/intel/broadwell/romstage/cpu.c rename to src/cpu/intel/broadwell/broadwell_early_init.c diff --git a/src/soc/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c similarity index 100% rename from src/soc/intel/broadwell/chip.c rename to src/cpu/intel/broadwell/chip.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c similarity index 100% rename from src/soc/intel/broadwell/cpu.c rename to src/cpu/intel/broadwell/cpu.c diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c similarity index 100% rename from src/soc/intel/broadwell/cpu_info.c rename to src/cpu/intel/broadwell/cpu_info.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/cpu/intel/broadwell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/romstage.c rename to src/cpu/intel/broadwell/romstage.c diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c similarity index 100% rename from src/soc/intel/broadwell/smmrelocate.c rename to src/cpu/intel/broadwell/smmrelocate.c diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/cpu/intel/broadwell/tsc_freq.c similarity index 100% rename from src/soc/intel/broadwell/tsc_freq.c rename to src/cpu/intel/broadwell/tsc_freq.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index be854b2..7e502ec 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,27 +1,11 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/intel/common -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c -bootblock-y += ../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../cpu/x86/early_reset.S -ramstage-y += acpi.c ramstage-y += adsp.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += cpu_info.c -smm-y += cpu_info.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c ramstage-y += gpio.c @@ -55,14 +39,7 @@ ramstage-y += smbus.c ramstage-y += smi.c smm-y += smihandler.c -ramstage-y += smmrelocate.c ramstage-y += systemagent.c -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c bootblock-y += usb_debug.c romstage-y += usb_debug.c ramstage-y += usb_debug.c @@ -70,12 +47,8 @@ ramstage-y += xhci.c smm-y += xhci.c -postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S - ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin - CPPFLAGS_common += -Isrc/soc/intel/broadwell/include # If an MRC file is an ELF file determine the entry address and first loadable diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index a53cd95..fb6c56a 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,10 +1,7 @@ -romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c -romstage-y += romstage.c romstage-y += smbus.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f719ea7585ec724c52950e76e5f52bdc1d6c43 Gerrit-Change-Number: 41927 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020