coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#31). Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/block/acpi: add code for CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. This way all SoCs using the common code get the CPPC entries added. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46465 to look at the new patch set (#20). Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/soc/intel/skylake/acpi.c 2 files changed, 22 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46465/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Karthik Ramasubramanian (Code Review) 31 Oct '20

31 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... Patch Set 2: (1 comment) > Patch Set 2: > > Just to be clear, this is an alternative to the SMI GPIO control, correct? Yes, the only concern is the OFF method is not getting invoked during shutdown. So we still need the SMI to ensure the sequence during the shutdown. https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/usb_a… File src/drivers/usb/acpi/usb_acpi.c: https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/usb_a… PS2, Line 65: * Should we apply Power Resource only for Internal ports. * > Is this a question? Yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Oct 2020 23:55:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Remove RIPTO support for camera
by Daniel Kang (Code Review) 30 Oct '20

30 Oct '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46826 ) Change subject: mb/google/volteer: Remove RIPTO support for camera ...................................................................... mb/google/volteer: Remove RIPTO support for camera GPIO D4 was used for camera reset for both front and rear cameras (RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions, GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L). Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right RCAM_RST_L per volteer version. However, we don't support RIPTO anymore. Also using flags for different volteer version support can be error-prone. Removing RIPTO support. BUG=b:171726823 BRANCH=none TEST=Build and boot volteer proto2 or later version. Camera should work without an issue. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46826/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index a90a62e..bda0d11 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -156,11 +156,7 @@ MCON(3,1) /* Clock 3, 19.2MHz */ /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif /* Pull SNRPWR_EN high */ STXS(GPP_H14) @@ -175,11 +171,7 @@ REFC = REFC + 1 /* Pull RST high */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) STXS(GPP_F15) -#else - STXS(GPP_D4) -#endif Sleep(1) /* t2 */ @@ -192,11 +184,7 @@ MCOF(3) /* Clock 3 */ /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif If ((REFC == 1)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91 Gerrit-Change-Number: 46826 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: Enable battery charging thresholds
by Jeremy Soller (Code Review) 30 Oct '20

30 Oct '20

Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45533 ) Change subject: mb/system76/lemp9: Enable battery charging thresholds ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Gerrit-Change-Number: 45533 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Oct 2020 22:29:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/system76/ec: Add battery charging thresholds
by Jeremy Soller (Code Review) 30 Oct '20

30 Oct '20

Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45532 ) Change subject: ec/system76/ec: Add battery charging thresholds ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d656291c096f320d469274677e9fe6c74819d25 Gerrit-Change-Number: 45532 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Oct 2020 22:29:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/sipi_vector.S: Use correct suffix for bts
by Jacob Garber (Code Review) 30 Oct '20

30 Oct '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46928 ) Change subject: cpu/x86/sipi_vector.S: Use correct suffix for bts ...................................................................... cpu/x86/sipi_vector.S: Use correct suffix for bts The assembler is warning that the bts instruction is ambiguous, so use the correct suffix btsl. See also commit 693315160e (cpu/x86/sipi_vector.S: Use correct op suffix) Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I2eded0af1258e90926009544683b23961d99887b --- M src/cpu/x86/sipi_vector.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46928/1 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..054f30d 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -121,7 +121,7 @@ /* Protect microcode loading. */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: -- To view, visit https://review.coreboot.org/c/coreboot/+/46928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eded0af1258e90926009544683b23961d99887b Gerrit-Change-Number: 46928 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86: Add a fake SoC along with a board for build testing
by Nico Huber (Code Review) 30 Oct '20

30 Oct '20

Hello Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45710 to review the following change. Change subject: x86: Add a fake SoC along with a board for build testing ...................................................................... x86: Add a fake SoC along with a board for build testing This fake SoC code should serve as a minimal example how a buildable code base can look like. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the fake code itself is build-tested, it should advance with coreboot and can't rot like documentation might. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A src/mainboard/fake/Kconfig A src/mainboard/fake/Kconfig.name A src/mainboard/fake/x86/Kconfig A src/mainboard/fake/x86/Kconfig.name A src/mainboard/fake/x86/board_info.txt A src/mainboard/fake/x86/devicetree.cb A src/soc/fake/Kconfig A src/soc/fake/x86/Kconfig A src/soc/fake/x86/Makefile.inc A src/soc/fake/x86/cache_as_ram.S A src/soc/fake/x86/chip.c A src/soc/fake/x86/exit_car.S A src/soc/fake/x86/romstage.c A src/soc/fake/x86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45710/1 diff --git a/src/mainboard/fake/Kconfig b/src/mainboard/fake/Kconfig new file mode 100644 index 0000000..2c0431a --- /dev/null +++ b/src/mainboard/fake/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_FAKE + +choice + prompt "Mainboard model" + +source "src/mainboard/fake/*/Kconfig.name" + +endchoice + +source "src/mainboard/fake/*/Kconfig" + +config MAINBOARD_VENDOR + default "Fake" + +endif # VENDOR_FAKE diff --git a/src/mainboard/fake/Kconfig.name b/src/mainboard/fake/Kconfig.name new file mode 100644 index 0000000..3beb2c0a --- /dev/null +++ b/src/mainboard/fake/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FAKE + bool "Fake boards for build testing only" diff --git a/src/mainboard/fake/x86/Kconfig b/src/mainboard/fake/x86/Kconfig new file mode 100644 index 0000000..db0746b --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig @@ -0,0 +1,15 @@ +if MAINBOARD_FAKE_X86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_FAKE_X86 + select MISSING_BOARD_RESET + select BOARD_ROMSIZE_KB_256 # MTRR code minimum + +config MAINBOARD_DIR + default "fake/x86" + +config MAINBOARD_PART_NUMBER + default "Fake86" + +endif diff --git a/src/mainboard/fake/x86/Kconfig.name b/src/mainboard/fake/x86/Kconfig.name new file mode 100644 index 0000000..a579d03 --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig.name @@ -0,0 +1,9 @@ +config MAINBOARD_FAKE_X86 + bool "x86 fake board" + help + This fake mainboard along with the fake/x86 SoC should serve + as a minimal example how a buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. diff --git a/src/mainboard/fake/x86/board_info.txt b/src/mainboard/fake/x86/board_info.txt new file mode 100644 index 0000000..c778859 --- /dev/null +++ b/src/mainboard/fake/x86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/fake/x86/devicetree.cb b/src/mainboard/fake/x86/devicetree.cb new file mode 100644 index 0000000..38e82bd --- /dev/null +++ b/src/mainboard/fake/x86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/fake/x86 + + device domain 0 on + end + +end diff --git a/src/soc/fake/Kconfig b/src/soc/fake/Kconfig new file mode 100644 index 0000000..b498e7c --- /dev/null +++ b/src/soc/fake/Kconfig @@ -0,0 +1 @@ +source "src/soc/fake/*/Kconfig" diff --git a/src/soc/fake/x86/Kconfig b/src/soc/fake/x86/Kconfig new file mode 100644 index 0000000..686a8d5 --- /dev/null +++ b/src/soc/fake/x86/Kconfig @@ -0,0 +1,26 @@ +config SOC_FAKE_X86 + bool + help + This fake SoC code should serve as a minimal example how a + buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. + +if SOC_FAKE_X86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/fake/x86/Makefile.inc b/src/soc/fake/x86/Makefile.inc new file mode 100644 index 0000000..0780607 --- /dev/null +++ b/src/soc/fake/x86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_FAKE_X86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/fake/x86/cache_as_ram.S b/src/soc/fake/x86/cache_as_ram.S new file mode 100644 index 0000000..a350143 --- /dev/null +++ b/src/soc/fake/x86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/fake/x86/chip.c b/src/soc/fake/x86/chip.c new file mode 100644 index 0000000..a5ec309 --- /dev/null +++ b/src/soc/fake/x86/chip.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations soc_fake_x86_ops = { NULL }; diff --git a/src/soc/fake/x86/exit_car.S b/src/soc/fake/x86/exit_car.S new file mode 100644 index 0000000..0f1b227 --- /dev/null +++ b/src/soc/fake/x86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/fake/x86/romstage.c b/src/soc/fake/x86/romstage.c new file mode 100644 index 0000000..91074b2 --- /dev/null +++ b/src/soc/fake/x86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/fake/x86/timer.c b/src/soc/fake/x86/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/fake/x86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Gerrit-Change-Number: 45710 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [Do not merge] Separate power resource for VCM
by Daniel Kang (Code Review) 30 Oct '20

30 Oct '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45159 ) Change subject: [Do not merge] Separate power resource for VCM ...................................................................... [Do not merge] Separate power resource for VCM WIP patch for discussion. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45159/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index dad762a..ad0b782 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -334,6 +334,54 @@ }) } + PowerResource (VCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* VCPR_ON_: VCM Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull PWREN high */ + STXS(GPP_H20) + Sleep(2) /* reset pulse width */ + + /* Pull RST high */ + STXS(GPP_F15) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* VCPR_OFF: VCM Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull PWREN low */ + CTXS(GPP_H20) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (VCM0) { Name (_HID, "PRP0001") /* _HID: Hardware ID */ @@ -356,11 +404,11 @@ }) Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { - RCPR + VCPR }) Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { - RCPR + VCPR }) Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { -- To view, visit https://review.coreboot.org/c/coreboot/+/45159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 Gerrit-Change-Number: 45159 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
by EricR Lai (Code Review) 30 Oct '20

30 Oct '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46868 ) Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku ...................................................................... mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/mainboard/google/octopus/variants/fleex/variant.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 679b101..cf1792b 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -84,6 +84,8 @@ }, }" + register "disable_xhci_lfps_pm" = "0" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index 522faa9..ab75602 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> #include <sar.h> +#include <soc/intel/apollolake/chip.h> #define MIN_LTE_SKU 4 @@ -31,3 +32,13 @@ return filename; } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { + if (is_lte_sku) + cfg->disable_xhci_lfps_pm = 1; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b Gerrit-Change-Number: 46868 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020