coreboot-gerrit October 2020

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Change in coreboot[master]: sb/intel/lynxpoint: Drop unnecessary `UL` suffix
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46719 ) Change subject: sb/intel/lynxpoint: Drop unnecessary `UL` suffix ...................................................................... sb/intel/lynxpoint: Drop unnecessary `UL` suffix With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change. Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/smihandler.c 7 files changed, 29 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46719/1 diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index cf360ff..68958f0 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -33,7 +33,7 @@ u16 reg16; u32 reg32; - if (RCBA32(0x2030) & (1UL << 31)) { + if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); @@ -54,9 +54,9 @@ if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) - reg32 &= ~(1UL << 31); + reg32 &= ~(1 << 31); else - reg32 |= (1UL << 31); + reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); } @@ -79,7 +79,7 @@ pci_write_config32(dev, 0xc4, reg32); if (!pch_is_lp()) - pci_and_config32(dev, 0xd0, ~(1UL << 31)); + pci_and_config32(dev, 0xd0, ~(1 << 31)); // Select Azalia mode pci_or_config8(dev, 0x40, 1); // Audio Control diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index fbad7d0..d0bfab6 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -40,9 +40,9 @@ #define GPI_LEVEL (1 << 30) #define GPO_LEVEL_SHIFT 31 -#define GPO_LEVEL_MASK (1UL << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_LOW (0UL << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_HIGH (1UL << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT) /* conf1 */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 29cd53f..9018a1c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -338,9 +338,9 @@ pci_or_config32(dev, 0xac, 1 << 21); pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); - pch_iobp_update(0xED000118, ~0UL, 0x00c00000); - pch_iobp_update(0xED000120, ~0UL, 0x00240000); - pch_iobp_update(0xCA000000, ~0UL, 0x00000009); + pch_iobp_update(0xED000118, ~0, 0x00c00000); + pch_iobp_update(0xED000120, ~0, 0x00240000); + pch_iobp_update(0xCA000000, ~0, 0x00000009); /* Set RCBA CIR28 0x3A84 based on SATA port enables */ data = 0x00001005; @@ -392,7 +392,7 @@ u16 reg16; /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_AND_OR(0x2234, ~0, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 11) | (1 << 12) | (1 << 14); reg16 |= (1 << 2); // PCI CLKRUN# Enable @@ -401,7 +401,7 @@ reg32 = RCBA32(CG); reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1UL << 31); // LPC Dynamic + reg32 |= (1 << 31); // LPC Dynamic reg32 |= (1 << 16); // PCIe Dynamic reg32 |= (1 << 27); // HPET Dynamic reg32 |= (1 << 28); // GPIO Dynamic @@ -417,7 +417,7 @@ u16 reg16; /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_AND_OR(0x2234, ~0, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~((1 << 11) | (1 << 14)); reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); @@ -463,8 +463,8 @@ RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic - pch_iobp_update(0xCF000000, ~0UL, 0x00007001); - pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 + pch_iobp_update(0xCF000000, ~0, 0x00007001); + pch_iobp_update(0xCE00C000, ~1, 0x00000000); // bit0=0 in BWG 1.4.0 } static void pch_set_acpi_mode(void) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index adc011b..1a338b1 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -97,31 +97,31 @@ break; case PCI_DEVFN(21, 0): /* DMA */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -137,7 +137,7 @@ break; case PCI_DEVFN(23, 0): /* SDIO */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ RCBA32_OR(BUC, PCH_DISABLE_GBE); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1ecad62..702d890 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -168,7 +168,7 @@ #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define PMIR 0xac -#define PMIR_CF9LOCK (1UL << 31) +#define PMIR_CF9LOCK (1 << 31) #define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ @@ -316,7 +316,7 @@ #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ @@ -409,7 +409,7 @@ #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 308d3c3..510440b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -122,7 +122,7 @@ reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ if (pch_is_lp()) { - reg32 &= ~((1UL << 31) | (1 << 30)); + reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } @@ -283,7 +283,7 @@ reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); - reg32 |= (1UL << 31) | (1 << 30) | (1 << 29); + reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9a5e5c0..8b791f7 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -348,7 +348,7 @@ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); + disable_pm1_control(-1); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862 Gerrit-Change-Number: 46719 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use common code to generate HPET table
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46977 ) Change subject: sb/intel/lynxpoint: Use common code to generate HPET table ...................................................................... sb/intel/lynxpoint: Use common code to generate HPET table There's no need to reinvent the wheel. Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 5 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46977/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5abb286..7ba86b8 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -51,6 +51,10 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. +config HPET_MIN_TICKS + hex + default 0x80 + config FINALIZE_USB_ROUTE_XHCI bool "Route all ports to XHCI controller in finalize step" default y diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index ce1b109..e699c5d 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -9,37 +9,6 @@ #include "pch.h" #include "nvs.h" -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *)hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_ADDR & 0xffffffff; - addr->addrh = (unsigned long long)HPET_ADDR >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); -} - static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { char sio_name[5] = {}; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7eef5ff..fd5297f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -761,7 +761,7 @@ hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = acpi_align_current(current); - acpi_create_intel_hpet(hpet); + acpi_create_hpet(hpet); acpi_add_table(rsdp, hpet); current = acpi_align_current(current); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 702d890..66cd05e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -120,7 +120,6 @@ void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); void pch_log_state(void); -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc Gerrit-Change-Number: 46977 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Peichao Wang (Code Review) 31 Oct '20

31 Oct '20

Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 31 Oct 2020 07:15:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Alec Wang (Code Review) 31 Oct '20

31 Oct '20

Alec Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… PS9, Line 11: PAD_CFG_GPO(GPP_A10, 0, PLTRST), > power_enable need to pull up. Done https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… PS9, Line 45: PAD_CFG_GPO(GPP_H17, 0, PLTRST), > RESET need to pull up. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Comment-Date: Sat, 31 Oct 2020 06:54:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Alec Wang (Code Review) 31 Oct '20

31 Oct '20

Alec Wang has uploaded a new patch set (#10) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... mb/google/dedede/var/boten: Add LTE power on/off sequence LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/boten/Makefile.inc M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb A src/mainboard/google/dedede/variants/boten/variant.c 4 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44588/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Peichao Wang (Code Review) 31 Oct '20

31 Oct '20

Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… PS9, Line 11: PAD_CFG_GPO(GPP_A10, 0, PLTRST), power_enable need to pull up. https://review.coreboot.org/c/coreboot/+/44588/9/src/mainboard/google/deded… PS9, Line 45: PAD_CFG_GPO(GPP_H17, 0, PLTRST), RESET need to pull up. -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 9 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Comment-Date: Sat, 31 Oct 2020 05:34:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46464 ) Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... cpu/intel/common: correct MSR for the Nominal Performance in CPPC The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 2 files changed, 11 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 3ea8f36..c5f43ef 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -131,13 +131,6 @@ config->regs[CPPC_HIGHEST_PERF] = msr; /* - * Nominal Performance -> Guaranteed Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_NOMINAL_PERF] = msr; - - /* * Lowest Nonlinear Performance -> Most Efficient Performance: * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, */ @@ -158,6 +151,15 @@ msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; + msr.addrl = MSR_PLATFORM_INFO; + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_NOMINAL_PERF] = msr; + msr.addrl = IA32_HWP_REQUEST; /* diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index a2165f3..da0f0bb 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -12,4 +12,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) +#define MSR_PLATFORM_INFO 0xce + #endif /* CPU_INTEL_MSR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… PS18, Line 377: 2 > did this a bit different, also see CB:46986 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 31 Oct 2020 00:04:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 31: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 372: /* version 2 */ > or use a #define that's already done ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 31 Oct 2020 00:04:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 31 Oct '20

31 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 31: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/30/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/30/src/soc/intel/common/bloc… PS30, Line 440: : if (cpuid_eax(6) & CPUID_6_EAX_ISST) > nit: cpuid is a serializing instruction, and its values won't change, you could stuff this in a vari […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 31 Oct 2020 00:03:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2020