coreboot-gerrit October 2020

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Angel Pons (Code Review) 01 Nov '20

01 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Oct 2020 23:38:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Nico Huber (Code Review) 31 Oct '20

31 Oct '20

Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Thomas Heijligen, Angel Pons, Julius Werner, Arthur Heymans, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34170 to look at the new patch set (#6). Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 116 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34170/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Oct 2020 21:46:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: docs/librem_mini: update CPU, known issues section
by Matt DeVillier (Code Review) 31 Oct '20

31 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46983 ) Change subject: docs/librem_mini: update CPU, known issues section ...................................................................... docs/librem_mini: update CPU, known issues section Both 8565U and 8665U CPUs are used in the Librem Mini. SATA issue updated based on addition of HSIO PHY tuning params and resulting changes. Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M Documentation/mainboard/purism/librem_mini.md 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46983/1 diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md index be9a3e5..192805f 100644 --- a/Documentation/mainboard/purism/librem_mini.md +++ b/Documentation/mainboard/purism/librem_mini.md @@ -4,7 +4,7 @@ ```eval_rst +------------------+--------------------------------------------------+ -| CPU | Intel Core i7-8565U | +| CPU | Intel Core i7-8565U/8665U | +------------------+--------------------------------------------------+ | PCH | Whiskey Lake / Cannon Point LP | +------------------+--------------------------------------------------+ @@ -91,10 +91,11 @@ ## Known issues * SeaBIOS can be finicky with detecting USB devices - * Booting can sometimes hang when a bootsplash image is used with SeaBIOS - and VGA option ROM display init, related to display mode changing - * Issues with some SATA devices have been mitigated by limiting the SATA speed to 3Gbps - until the correct HSIO PHY settings can be determined. + * Mode switching with VGA option ROM display init can be slow and sometimes hang + * Some SATA devices on the 2.5" interface can have issues operating at 6Gbps, + despite the HSIO PHY settings being set optimally. These devices may show + errors in dmesg and drop down to 3Gbps, but should not fail to boot. + The same issue is present on the AMI vendor firmware. ## Working -- To view, visit https://review.coreboot.org/c/coreboot/+/46983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8 Gerrit-Change-Number: 46983 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Nico Huber (Code Review) 31 Oct '20

31 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 106: switch (cpuid_model()) { : case 0x4e: /* SKL-U/Y */ : case 0x5e: /* SKL-S/H */ : case 0x8e: /* KBL-U/Y */ : case 0x9e: /* KBL-S/H */ : nominal = 24000000; : break; : case 0x5c: /* APL */ : nominal = 19200000; : break; : default: : return -1; : } : } : : return nominal * num / denom / 1000; : } : : /** : * @brief Returns three times the bus clock in kHz : * : * The result of calculations with the returned value shall be divided by 3. : * This helps to avoid rounding errors. : */ : static int get_bus_khz_x3(void) : { : if (cpuid_family() != 6) : return -1; : : switch (cpuid_model()) { : case 0x25: /* Nehalem */ : return 400 * 1000; /* 133 MHz */ : case 0x2a: /* SandyBridge */ : case 0x3a: /* IvyBridge */ : case 0x3c: /* Haswell */ : case 0x3d: /* Broadwell */ : case 0x45: /* Haswell-ULT */ : case 0x46: /* Haswell-GT3e */ : return 300 * 1000; /* 100 MHz */ : default: : return -1; : } : } > I like that! Done https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 172: /* > not a requirement, it just hurt my eyes :P (guess it's simply personal preference to have a newline […] Ack https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 176: _rdmsr(MSR_PLATFORM_INFO) >> 8 > reminds me I first thought of replying "to worsen readability?" but thought it would be a tad bit to […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Oct 2020 21:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Nico Huber (Code Review) 31 Oct '20

31 Oct '20

Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Thomas Heijligen, Angel Pons, Julius Werner, Arthur Heymans, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34170 to look at the new patch set (#5). Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 115 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34170/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: .gitignore: Ignore .test/.dependencies globally
by Patrick Georgi (Code Review) 31 Oct '20

31 Oct '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47012 ) Change subject: .gitignore: Ignore .test/.dependencies globally ...................................................................... .gitignore: Ignore .test/.dependencies globally These were originally ignored only inside util/ but these files shouldn't be tracked anywhere. Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M .gitignore M util/amdfwtool/.gitignore M util/archive/.gitignore M util/autoport/.gitignore M util/bincfg/.gitignore M util/bucts/.gitignore M util/cbfstool/.gitignore M util/cbmem/.gitignore M util/ectool/.gitignore M util/futility/.gitignore M util/genprof/.gitignore M util/ifdtool/.gitignore M util/intelmetool/.gitignore M util/intelp2m/.gitignore M util/inteltool/.gitignore M util/intelvbttool/.gitignore M util/kbc1126/.gitignore M util/msrtool/.gitignore M util/nvramtool/.gitignore M util/pmh7tool/.gitignore M util/spd_tools/.gitignore M util/superiotool/.gitignore M util/vgabios/.gitignore 23 files changed, 2 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47012/1 diff --git a/.gitignore b/.gitignore index a607772..11a6173 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,8 @@ *.pyc *.sw[po] /*.rom +.test +.dependencies # Development friendly files tags diff --git a/util/amdfwtool/.gitignore b/util/amdfwtool/.gitignore index 221a616..cac1859 100644 --- a/util/amdfwtool/.gitignore +++ b/util/amdfwtool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test amdfwtool diff --git a/util/archive/.gitignore b/util/archive/.gitignore index ea0035f..f1d43c6 100644 --- a/util/archive/.gitignore +++ b/util/archive/.gitignore @@ -1,3 +1 @@ -.dependencies -.test archive diff --git a/util/autoport/.gitignore b/util/autoport/.gitignore index dc8599e..0069f99 100644 --- a/util/autoport/.gitignore +++ b/util/autoport/.gitignore @@ -1,3 +1 @@ -.dependencies -.test autoport diff --git a/util/bincfg/.gitignore b/util/bincfg/.gitignore index ee1b394..20a7c59 100644 --- a/util/bincfg/.gitignore +++ b/util/bincfg/.gitignore @@ -1,3 +1 @@ -.dependencies -.test bincfg diff --git a/util/bucts/.gitignore b/util/bucts/.gitignore index c5a4708..f207389 100644 --- a/util/bucts/.gitignore +++ b/util/bucts/.gitignore @@ -1,3 +1 @@ -.dependencies -.test bucts diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore index 28fb4b2..560d7ea 100644 --- a/util/cbfstool/.gitignore +++ b/util/cbfstool/.gitignore @@ -1,5 +1,3 @@ -.dependencies -.test cbfs-compression-tool cbfstool fmaptool diff --git a/util/cbmem/.gitignore b/util/cbmem/.gitignore index 4905bd3..5bc3336 100644 --- a/util/cbmem/.gitignore +++ b/util/cbmem/.gitignore @@ -1,3 +1 @@ -.dependencies -.test cbmem diff --git a/util/ectool/.gitignore b/util/ectool/.gitignore index 67d81e4..4ceecac 100644 --- a/util/ectool/.gitignore +++ b/util/ectool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test ectool diff --git a/util/futility/.gitignore b/util/futility/.gitignore index aa3b0c7..1a1d4ab 100644 --- a/util/futility/.gitignore +++ b/util/futility/.gitignore @@ -1,3 +1 @@ -.dependencies -.test futility diff --git a/util/genprof/.gitignore b/util/genprof/.gitignore index 14ffbb6..612ef67 100644 --- a/util/genprof/.gitignore +++ b/util/genprof/.gitignore @@ -1,3 +1 @@ -.dependencies -.test genprof diff --git a/util/ifdtool/.gitignore b/util/ifdtool/.gitignore index 6cdb423..ee8e831 100644 --- a/util/ifdtool/.gitignore +++ b/util/ifdtool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test ifdtool diff --git a/util/intelmetool/.gitignore b/util/intelmetool/.gitignore index 5de15c0..ea65fca 100644 --- a/util/intelmetool/.gitignore +++ b/util/intelmetool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test intelmetool diff --git a/util/intelp2m/.gitignore b/util/intelp2m/.gitignore index 0696ea0..c9737920 100644 --- a/util/intelp2m/.gitignore +++ b/util/intelp2m/.gitignore @@ -1,4 +1,2 @@ -.dependencies -.test intelp2m generate/gpio.h diff --git a/util/inteltool/.gitignore b/util/inteltool/.gitignore index 767fbcc..f2b363a 100644 --- a/util/inteltool/.gitignore +++ b/util/inteltool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test inteltool diff --git a/util/intelvbttool/.gitignore b/util/intelvbttool/.gitignore index d4d9279..61545cd 100644 --- a/util/intelvbttool/.gitignore +++ b/util/intelvbttool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test intelvbttool diff --git a/util/kbc1126/.gitignore b/util/kbc1126/.gitignore index 9ded0a5..862c228 100644 --- a/util/kbc1126/.gitignore +++ b/util/kbc1126/.gitignore @@ -1,4 +1,2 @@ -.dependencies -.test kbc1126_ec_dump kbc1126_ec_insert diff --git a/util/msrtool/.gitignore b/util/msrtool/.gitignore index 13137c6..564b06c 100644 --- a/util/msrtool/.gitignore +++ b/util/msrtool/.gitignore @@ -1,5 +1,3 @@ -.dependencies -.test msrtool Makefile Makefile.deps diff --git a/util/nvramtool/.gitignore b/util/nvramtool/.gitignore index ab07341..fc4630e 100644 --- a/util/nvramtool/.gitignore +++ b/util/nvramtool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test nvramtool diff --git a/util/pmh7tool/.gitignore b/util/pmh7tool/.gitignore index 4b8dbc5..2f9e824 100644 --- a/util/pmh7tool/.gitignore +++ b/util/pmh7tool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test pmh7tool diff --git a/util/spd_tools/.gitignore b/util/spd_tools/.gitignore index 5cd5413..cafb853 100644 --- a/util/spd_tools/.gitignore +++ b/util/spd_tools/.gitignore @@ -1,4 +1,2 @@ -.dependencies -.test */gen_spd */gen_part_id diff --git a/util/superiotool/.gitignore b/util/superiotool/.gitignore index 566cd84..63af84d 100644 --- a/util/superiotool/.gitignore +++ b/util/superiotool/.gitignore @@ -1,3 +1 @@ -.dependencies -.test superiotool diff --git a/util/vgabios/.gitignore b/util/vgabios/.gitignore index e19a8a5..b3bf197 100644 --- a/util/vgabios/.gitignore +++ b/util/vgabios/.gitignore @@ -1,3 +1 @@ -.dependencies -.test testbios -- To view, visit https://review.coreboot.org/c/coreboot/+/47012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Gerrit-Change-Number: 47012 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Remove CONFIG_MAINBOARD_PART_NUMBER from doxyplatform
by Martin Roth (Code Review) 31 Oct '20

31 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46287 ) Change subject: Makefile: Remove CONFIG_MAINBOARD_PART_NUMBER from doxyplatform ...................................................................... Makefile: Remove CONFIG_MAINBOARD_PART_NUMBER from doxyplatform The CONFIG_MAINBOARD_PART_NUMBER string can have characters in it that don't work in the doxyplatform make script under sh, so remove it and just use the CONFIG_MAINBOARD_DIR value instead. The spaces in the "QEMU x86 i440fx/piix4" platform are one example of this. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I10bc6a8a245a34e89c859ff46835bde35aaa4286 --- M Makefile 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46287/1 diff --git a/Makefile b/Makefile index 2705c66..4f7f45d 100644 --- a/Makefile +++ b/Makefile @@ -440,10 +440,10 @@ doxyplatform doxygen_platform: $(obj)/project_filelist.txt echo echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)" - export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_VENDOR)/$(CONFIG_MAINBOARD_PART_NUMBER)"; \ + export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_DIR)"; \ mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \ export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \ - export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) ($(CONFIG_MAINBOARD_PART_NUMBER)) version $(KERNELVERSION)"; \ + export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) version $(KERNELVERSION)"; \ $(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform doxyclean: doxygen-clean -- To view, visit https://review.coreboot.org/c/coreboot/+/46287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10bc6a8a245a34e89c859ff46835bde35aaa4286 Gerrit-Change-Number: 46287 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: rename virtual wire mode initialization function
by Felix Held (Code Review) 31 Oct '20

31 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47020 ) Change subject: cpu/x86/lapic: rename virtual wire mode initialization function ...................................................................... cpu/x86/lapic: rename virtual wire mode initialization function Clarify what the function does by renaming it from do_lapic_init() to lapic_virtual_wire_mode_init(). Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/47020/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 04ce226..988d664 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -3,7 +3,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> -void do_lapic_init(void) +void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 5ab5755..f4291ab 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -73,7 +73,7 @@ # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -void do_lapic_init(void); +void lapic_virtual_wire_mode_init(void); /* See if I need to initialize the local APIC */ static inline int need_lapic_init(void) @@ -84,7 +84,7 @@ static inline void setup_lapic(void) { if (need_lapic_init()) - do_lapic_init(); + lapic_virtual_wire_mode_init(); else disable_lapic(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac Gerrit-Change-Number: 47020 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46720 ) Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ...................................................................... {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e..e0e1e1c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@ /* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42..b95b3fe 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@ MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d..0bca230 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd71..2d19ccd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; -- To view, visit https://review.coreboot.org/c/coreboot/+/46720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Gerrit-Change-Number: 46720 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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