coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46642 ) Change subject: soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device ...................................................................... soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device In order to support the common PMC functions this device needs to be able to be located with the common lookup macro. BUG=b:160996445 TEST=build intel/harcuvar board Change-Id: If04a82582c07c15bf841d0baa84e31561d211502 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/denverton_ns/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46642/1 diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index ba251a8..b6bac0b 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -138,6 +138,7 @@ #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/46642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If04a82582c07c15bf841d0baa84e31561d211502 Gerrit-Change-Number: 46642 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/octopus/var/fleex: Add variant into smm stage
by EricR Lai (Code Review) 02 Nov '20

02 Nov '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46847 ) Change subject: mb/google/octopus/var/fleex: Add variant into smm stage ...................................................................... mb/google/octopus/var/fleex: Add variant into smm stage variant_smi_sleep is called in smm stage so we need add variant.c into smm stage. Otherwise it will call the dummy one. BUG=b:168075958 BRANCH=octopus TEST=build image passed. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f --- M src/mainboard/google/octopus/variants/fleex/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46847/1 diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index 51c9d39..2835934 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f Gerrit-Change-Number: 46847 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
by Patrick Rudolph (Code Review) 02 Nov '20

02 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44673 ) Change subject: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode ...................................................................... cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode * Use heap for linker script calculated constant to fix relocation symbols in mixed assembly code. * Work around a strange bug that causes the CPU to halt when accessing MMX registers in long mode Tested on HPZ220: * Still boots in x86_32. Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 40 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44673/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b24f101..481cbee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -9,6 +9,27 @@ .global bootblock_pre_c_entry +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#ifdef __x86_64__ +rom_mtrr_mask: +.quad _rom_mtrr_mask + +rom_mtrr_base: +.quad _rom_mtrr_base + +car_mtrr_mask: +.quad _car_mtrr_mask +#else +rom_mtrr_mask: +.long _rom_mtrr_mask + +rom_mtrr_base: +.long _rom_mtrr_base + +car_mtrr_mask: +.long _car_mtrr_mask +#endif + .code32 _cache_as_ram_setup: @@ -83,7 +104,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -96,20 +116,20 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -208,17 +228,24 @@ the pushes below. */ andl $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ +#ifdef __x86_64__ + /* + * BUG: On some x86 platforms acessing MMX register in long mode + * causes a crash. Retrieve them here and then switch to long mode. + */ + movd %mm2, %eax + push %eax + movd %mm1, %eax /* tsc */ + push %eax + movd %mm0, %eax + push %eax + xorl %eax, %eax + push %eax /* BIST */ + #include <cpu/x86/64bit/entry64.inc> -#ifdef __x86_64__ - - movd %mm2, %rdi - shld %rdi, 32 - movd %mm1, %rsi - or %rsi, %rdi /* tsc */ - - movd %mm0, %rsi /* BIST */ + pop %rsi /* BIST */ + pop %rdi /* tsc */ #else subl $4, %esp /* push TSC and BIST to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Gerrit-Change-Number: 44673 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mb/google/dedede/var/metaknight: Generate SPD ID for supported parts
by Tim Chen (Code Review) 02 Nov '20

02 Nov '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46810 to review the following change. Change subject: mb/google/dedede/var/metaknight: Generate SPD ID for supported parts ...................................................................... mb/google/dedede/var/metaknight: Generate SPD ID for supported parts Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=b:169813211 TEST=Build the metaknight board. Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993 --- M src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc M src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt 3 files changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46810/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc index b0ca222..285df73 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt index fa24790..100c322 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -1 +1,6 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt index 59381dc..f05a5af 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -1,6 +1,5 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/46810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993 Gerrit-Change-Number: 46810 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/volteer/var/terrador: Enable SaGv support
by David Wu (Code Review) 02 Nov '20

02 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46841 ) Change subject: mb/google/volteer/var/terrador: Enable SaGv support ...................................................................... mb/google/volteer/var/terrador: Enable SaGv support Enable SaGv for terrador. BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46841/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79..ea817eb 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,8 +14,6 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/46841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Gerrit-Change-Number: 46841 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: libpayload/x86: Add enumeration of Intel family 6 models
by Nico Huber (Code Review) 02 Nov '20

02 Nov '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47059 ) Change subject: libpayload/x86: Add enumeration of Intel family 6 models ...................................................................... libpayload/x86: Add enumeration of Intel family 6 models The list is incomplete and only contains what we need in the follow-up commit. It can be extended at will. Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/include/x86/arch/cpuid.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47059/1 diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index c77be9c..b1aa0a8 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -64,4 +64,19 @@ return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; } +enum intel_fam6_model { + NEHALEM = 0x25, + SANDYBRIDGE = 0x2a, + IVYBRIDGE = 0x3a, + HASWELL = 0x3c, + BROADWELL = 0x3d, + HASWELL_U = 0x45, + HASWELL_GT3E = 0x46, + APOLLOLAKE = 0x5c, + SKYLAKE_U_Y = 0x4e, + SKYLAKE_S_H = 0x5e, + KABYLAKE_U_Y = 0x8e, + KABYLAKE_S_H = 0x9e, +}; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9 Gerrit-Change-Number: 47059 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: ec/system76/ec: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 02 Nov '20

02 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46107 ) Change subject: ec/system76/ec: Convert to ASL 2.0 syntax ...................................................................... ec/system76/ec: Convert to ASL 2.0 syntax Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/system76/ec/acpi/ec.asl M src/ec/system76/ec/acpi/hid.asl 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46107/1 diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index 5989f6d..98abc66 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -35,7 +35,7 @@ Method (_REG, 2, Serialized) // _REG: Region Availability { Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) - If (((Arg0 == 0x03) && (Arg1 == One))) { + If ((Arg0 == 0x03) && (Arg1 == One)) { // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys ECOS = 1 diff --git a/src/ec/system76/ec/acpi/hid.asl b/src/ec/system76/ec/acpi/hid.asl index ce8fd3f..6610c2e 100644 --- a/src/ec/system76/ec/acpi/hid.asl +++ b/src/ec/system76/ec/acpi/hid.asl @@ -30,13 +30,13 @@ Notify (HIDD, 0xC0) Local0 = Zero - While (((Local0 < 0xFA) && HBSY)) + While ((Local0 < 0xFA) && HBSY) { Sleep (0x04) Local0++ } - If ((HBSY == One)) + If (HBSY == One) { HBSY = Zero HIDX = Zero -- To view, visit https://review.coreboot.org/c/coreboot/+/46107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e Gerrit-Change-Number: 46107 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: volteer: Create voema variant
by David Wu (Code Review) 02 Nov '20

02 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47007 ) Change subject: volteer: Create voema variant ...................................................................... volteer: Create voema variant Create the voema variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171755775 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOEMA Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voema/include/variant/ec.h A src/mainboard/google/volteer/variants/voema/include/variant/gpio.h A src/mainboard/google/volteer/variants/voema/memory/Makefile.inc A src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/voema/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47007/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5..8fd119e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -94,6 +94,7 @@ default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI + default "Voema" if BOARD_GOOGLE_VOEMA config MAX_CPUS int @@ -132,6 +133,7 @@ default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI + default "voema" if BOARD_GOOGLE_VOEMA config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..9e48a2f 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -71,3 +71,7 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt new file mode 100644 index 0000000..f51b3af --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 Gerrit-Change-Number: 47007 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Add G2Touch touchscreen support
by Kenneth Chan (Code Review) 02 Nov '20

02 Nov '20

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46675 ) Change subject: mb/google/octopus/variants/dood: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/dood: Add G2Touch touchscreen support Add G2Touch touchscreen support for dood. BUG=b:171526389 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 --- M src/mainboard/google/octopus/variants/dood/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46675/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index e1f12cf..6e767dd 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -144,6 +144,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 Gerrit-Change-Number: 46675 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/smm: Pass smm.ld trought src-to-obj
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44321 ) Change subject: cpu/x86/smm: Pass smm.ld trought src-to-obj ...................................................................... cpu/x86/smm: Pass smm.ld trought src-to-obj This allows for ccopts symbols and preprocessor to be used inside the smm.ld linker script. Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44321/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a..bbd96c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -16,7 +16,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $^) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,8 +72,10 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Gerrit-Change-Number: 44321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020