coreboot-gerrit October 2020

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Change in coreboot[master]: mb/purism/librem_whl: rename to librem_cnl
by Matt DeVillier (Code Review) 03 Nov '20

03 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47050 ) Change subject: mb/purism/librem_whl: rename to librem_cnl ...................................................................... mb/purism/librem_whl: rename to librem_cnl Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake, rename the baseboard so that boards using other 'cannonlake family' SoCs (e.g., Cometlake) can be added with minimal confusion. Rename the mainboard dir and baseboard name, and adjust any references to them. Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- R src/mainboard/purism/librem_cnl/Kconfig A src/mainboard/purism/librem_cnl/Kconfig.name R src/mainboard/purism/librem_cnl/Makefile.inc R src/mainboard/purism/librem_cnl/acpi/mainboard.asl R src/mainboard/purism/librem_cnl/board_info.txt R src/mainboard/purism/librem_cnl/devicetree.cb R src/mainboard/purism/librem_cnl/dsdt.asl R src/mainboard/purism/librem_cnl/ramstage.c R src/mainboard/purism/librem_cnl/romstage.c R src/mainboard/purism/librem_cnl/variants/librem_mini/data.vbt R src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c R src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c R src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h D src/mainboard/purism/librem_whl/Kconfig.name 14 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47050/1 diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig similarity index 90% rename from src/mainboard/purism/librem_whl/Kconfig rename to src/mainboard/purism/librem_cnl/Kconfig index bc25fb5..38be380 100644 --- a/src/mainboard/purism/librem_whl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -1,4 +1,4 @@ -config BOARD_PURISM_BASEBOARD_LIBREM_WHL +config BOARD_PURISM_BASEBOARD_LIBREM_CNL def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL @@ -13,11 +13,11 @@ select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER -if BOARD_PURISM_BASEBOARD_LIBREM_WHL +if BOARD_PURISM_BASEBOARD_LIBREM_CNL config MAINBOARD_DIR string - default "purism/librem_whl" + default "purism/librem_cnl" config MAINBOARD_FAMILY string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name new file mode 100644 index 0000000..326165ba --- /dev/null +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PURISM_LIBREM_MINI + bool "Librem Mini" + select BOARD_PURISM_BASEBOARD_LIBREM_CNL diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc similarity index 100% rename from src/mainboard/purism/librem_whl/Makefile.inc rename to src/mainboard/purism/librem_cnl/Makefile.inc diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_cnl/acpi/mainboard.asl similarity index 100% rename from src/mainboard/purism/librem_whl/acpi/mainboard.asl rename to src/mainboard/purism/librem_cnl/acpi/mainboard.asl diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt similarity index 84% rename from src/mainboard/purism/librem_whl/board_info.txt rename to src/mainboard/purism/librem_cnl/board_info.txt index e72dcdf2..ca61edd 100644 --- a/src/mainboard/purism/librem_whl/board_info.txt +++ b/src/mainboard/purism/librem_cnl/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Purism -Board name: librem_whl +Board name: librem_cnl Category: desktop Release year: 2020 ROM package: SOIC-8 diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb similarity index 100% rename from src/mainboard/purism/librem_whl/devicetree.cb rename to src/mainboard/purism/librem_cnl/devicetree.cb diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_cnl/dsdt.asl similarity index 100% rename from src/mainboard/purism/librem_whl/dsdt.asl rename to src/mainboard/purism/librem_cnl/dsdt.asl diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c similarity index 100% rename from src/mainboard/purism/librem_whl/ramstage.c rename to src/mainboard/purism/librem_cnl/ramstage.c diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c similarity index 100% rename from src/mainboard/purism/librem_whl/romstage.c rename to src/mainboard/purism/librem_cnl/romstage.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_cnl/variants/librem_mini/data.vbt similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt rename to src/mainboard/purism/librem_cnl/variants/librem_mini/data.vbt Binary files differ diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c rename to src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c rename to src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h rename to src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_whl/Kconfig.name deleted file mode 100644 index 41a4003..0000000 --- a/src/mainboard/purism/librem_whl/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -config BOARD_PURISM_LIBREM_MINI - bool "Librem Mini" - select BOARD_PURISM_BASEBOARD_LIBREM_WHL -- To view, visit https://review.coreboot.org/c/coreboot/+/47050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Gerrit-Change-Number: 47050 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus
by Marc Jones (Code Review) 03 Nov '20

03 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47060 ) Change subject: soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus ...................................................................... soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus Fix the asl to use CONFIG_MAX_CPUS to create entries for multiple cpu uncores. Don't add the RTxx resource entries multiple times. The function is called for each CPUs. Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47060/1 diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index dca5569..4b2b65b 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -69,7 +69,7 @@ MAKE_IIO_DEV(02, 20) MAKE_IIO_DEV(03, 28) -#if MAX_SOCKET > 1 +#if (CONFIG_MAX_SOCKET > 1) MAKE_IIO_DEV(06, 40) MAKE_IIO_DEV(07, 50) MAKE_IIO_DEV(08, 60) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index d60684b..f055913 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -60,6 +60,10 @@ { struct iiostack_resource stack_info = {0}; + /* Only add RTxx entries once. */ + if (dev->bus->secondary != 0) + return; + get_iiostack_info(&stack_info); acpigen_write_scope("\\_SB"); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index df2550c..0182b18 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -6,6 +6,7 @@ #include <assert.h> #include <cbmem.h> #include <cpu/intel/turbo.h> +#include <device/device.h> #include <device/mmio.h> #include <device/pci.h> #include <intelblocks/acpi.h> @@ -97,13 +98,17 @@ } -void uncore_inject_dsdt(const struct device *device) +void uncore_inject_dsdt(const struct device *dev) { size_t hob_size; const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); assert(hob != NULL && hob_size != 0); + /* Only add RTxx entries once. */ + if (dev->bus->secondary != 0) + return; + acpigen_write_scope("\\_SB"); for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { IIO_RESOURCE_INSTANCE iio_resource = -- To view, visit https://review.coreboot.org/c/coreboot/+/47060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef Gerrit-Change-Number: 47060 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/xeon_sp; Use soc specific stack-port function
by Marc Jones (Code Review) 03 Nov '20

03 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46971 ) Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ...................................................................... soc/intel/xeon_sp; Use soc specific stack-port function Separate the get_stack_for_port into soc specific functions. This removes a #if in common code. Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 5 files changed, 51 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46971/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index f0c2575..5f4a6f9 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -26,5 +26,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); +int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index bc4a1e1..de6d852 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -319,3 +319,25 @@ /* And finally, take care of the SBSP */ set_bios_init_completion_for_package(sbsp_socket_id); } +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 5955fa0..f6bf6ed 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -143,48 +143,6 @@ } /* - * EX: CPX-SP - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACKZ stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int port) -{ -#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else - return -1; -#endif /* SOC_INTEL_COOPERLAKE_SP */ - -#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -#endif /* SOC_INTEL_SKYLAKE_SP */ -} - -/* * This function adds PCIe bridge device entry in DMAR table. If it is called * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ @@ -193,7 +151,7 @@ bool is_atsr, bool *first) { - if (get_stack_for_port(port) != stack) + if (soc_get_stack_for_port(port) != stack) return 0; const uint32_t bus = iio_resource.StackRes[stack].BusBase; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 2566830..cce542a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -27,5 +27,6 @@ void set_bios_init_completion(void); unsigned int soc_get_num_cpus(void); +int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7dd954f..5c9c3ad 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -394,4 +394,30 @@ } } +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else if (port >= PORT_4A && port <= PORT_4D) + return PSTACK3; // MCP0 + else if (port >= PORT_5A && port <= PORT_5D) + return PSTACK4; // MCP1 + else + return -1; +} #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Gerrit-Change-Number: 46971 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/common/block/systemagent/memmap.c: Align cached region
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45930 ) Change subject: soc/intel/common/block/systemagent/memmap.c: Align cached region ...................................................................... soc/intel/common/block/systemagent/memmap.c: Align cached region When asked to place cbmem_top(), FSP does not seem to care about alignment. It can return an address that is MTRR poison, which will exhaust all variable MTRRs when trying to set up caching for CBMEM. This will make memory-mapped flash and TSEG caching fail as well. Safeguard against this by aligning the region to cache to half of its size, and move it upwards to compensate. It is assumed that caching memory above the provided bootloader TOLUM address is inconsequential. TEST=Boot out-of-tree Skylake board, observe no MTRR exhaustion error messages in console. The boot process also feels more fluid. Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/systemagent/memmap.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45930/1 diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 985f2c4..c59d93e 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -6,6 +6,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <intelblocks/systemagent.h> +#include <types.h> /* * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs): @@ -55,18 +56,18 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; + /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ + uintptr_t top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); /* * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is + * Instruct postcar to cache 16 megs around cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/45930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353 Gerrit-Change-Number: 45930 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: include/list.h: Add support for GCC9+
by Patrick Rudolph (Code Review) 03 Nov '20

03 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44573 ) Change subject: include/list.h: Add support for GCC9+ ...................................................................... include/list.h: Add support for GCC9+ When getting the address of a structure's member that is not on offset 0, GCC9+ assumes that the address never can be NULL. However the code relied on the fact that it can be NULL by letting the pointer intentionally overflow. Manually calculate the address using uintptr_t. This allows to gracefully terminate the list_for_each MACRO instead of crashing at the end of the list. Tested on qemu-system-arm: coreboot no longer crashed in the devicetree parser and is able to boot Linux 5.5. Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/include/list.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44573/1 diff --git a/src/include/list.h b/src/include/list.h index 3944878..6f0b54d 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -16,10 +16,10 @@ // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); -#define list_for_each(ptr, head, member) \ - for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ - &((ptr)->member); \ - (ptr) = container_of((ptr)->member.next, \ +#define list_for_each(ptr, head, member) \ + for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ + (uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \ + (ptr) = container_of((ptr)->member.next, \ typeof(*(ptr)), member)) #endif /* __LIST_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7 Gerrit-Change-Number: 44573 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 12

Change in coreboot[master]: util/cbfstool: Add Alignment for CBnT
by Christian Walter (Code Review) 03 Nov '20

03 Nov '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45652 ) Change subject: util/cbfstool: Add Alignment for CBnT ...................................................................... util/cbfstool: Add Alignment for CBnT Change-Id: Ibd94539a6025e7c3912730a6d90454379d85fb59 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M util/cbfstool/cbfstool.c M util/cbfstool/fit.c 2 files changed, 27 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45652/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d2df1cc..ce72835 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -70,6 +70,7 @@ bool machine_parseable; bool unprocessed; bool ibb; + bool cbnt; enum comp_algo compression; int precompression; enum vb2_hash_algorithm hash; @@ -551,6 +552,18 @@ len_align = 16; } + if (param.cbnt) { + ERROR("MARKING ENTRY AS CBNT\n"); + /* Mark as Initial Boot Block */ + struct cbfs_file_attribute *attrs = cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_IBB, + sizeof(struct cbfs_file_attribute)); + if (attrs == NULL) + return -1; + /* For Intel CBNT minimum align is 64 */ + len_align = 64; + } + if (param.padding) { const uint32_t hs = sizeof(struct cbfs_file_attribute); uint32_t size = MAX(hs, param.padding); @@ -1290,6 +1303,7 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_CBNT = 257, LONGOPT_END, }; @@ -1333,6 +1347,7 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"cbnt", no_argument, 0, LONGOPT_CBNT }, {NULL, 0, 0, 0 } }; @@ -1406,7 +1421,7 @@ " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) [--ibb] " + " [-j topswap-size] (Intel CPUs only) [--ibb] [--cbnt] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1417,7 +1432,7 @@ " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" " [-a alignment] [-P page-size] [-Q|--pow2page] \\\n" - " [-y|--xip] [--ibb] " + " [-y|--xip] [--ibb] [--cbnt] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1750,6 +1765,9 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_CBNT: + param.cbnt = true; + break; case 'h': case '?': usage(argv[0]); diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index e7aa8d7..b04cf90 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -463,9 +463,10 @@ uint32_t boot_policy_size) { entry->address = boot_policy_addr; - /* Boot Policy Manifest size is not multiple of 16 bytes */ - fit_entry_update_size(entry, boot_policy_size << 4); entry->type_checksum_valid = FIT_TYPE_BOOT_POLICY; + /* Boot Policy Manifest size is not multiple of 16 bytes */ + fit_entry_update_size(entry, boot_policy_size); + entry->size_reserved = boot_policy_size; entry->version = FIT_TXT_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); @@ -482,9 +483,11 @@ uint32_t key_manifest_size) { entry->address = key_manifest_addr; - /* Key Manifest size is not multiple of 16 bytes */ - fit_entry_update_size(entry, key_manifest_size << 4); + entry->type_checksum_valid = FIT_TYPE_KEY_MANIFEST; + /* Key Manifest size is not multiple of 16 bytes */ + fit_entry_update_size(entry, key_manifest_size); + entry->size_reserved = key_manifest_size; entry->version = FIT_TXT_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd94539a6025e7c3912730a6d90454379d85fb59 Gerrit-Change-Number: 45652 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: configs: Add a weird config for Portwell M107
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45974 ) Change subject: configs: Add a weird config for Portwell M107 ...................................................................... configs: Add a weird config for Portwell M107 This is not meant for actual use, but to build-test several options. Please do not try to use it on real hardware. Or maybe do try. Change-Id: Ife40d055e4c9b295c54cfc6a27af06e9358f7761 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45974/1 diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi new file mode 100644 index 0000000..448193d --- /dev/null +++ b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi @@ -0,0 +1,38 @@ +# Not meant for actual use. Exercises, among other things: +# + SMMSTORE +# + OXPCIE support +# + FSP MP init +# + EM100Pro SPI console +# + Debug options +CONFIG_VENDOR_PORTWELL=y +CONFIG_CONSOLE_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_ENABLE_BUILTIN_COM1=y +CONFIG_ONBOARD_MEM_KINGSTON=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y +CONFIG_SOC_INTEL_DEBUG_CONSENT=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_SOFTWARE_I2C=y +CONFIG_SMMSTORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_UART_OXPCIE=y +CONFIG_DRIVERS_GENESYSLOGIC_GL9755=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DISPLAY_VBT=y +CONFIG_DISPLAY_FSP_ENTRY_POINTS=y +CONFIG_DISPLAY_UPD_DATA=y +CONFIG_EM100PRO_SPI_CONSOLE=y +CONFIG_DISPLAY_MTRRS=y +CONFIG_GDB_STUB=y +CONFIG_GDB_WAIT=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_REALMODE_DEBUG=y +CONFIG_DEBUG_BOOT_STATE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/45974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife40d055e4c9b295c54cfc6a27af06e9358f7761 Gerrit-Change-Number: 45974 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: [TESTONLY] smm loader v2 fixups for B85M Pro4
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44174 ) Change subject: [TESTONLY] smm loader v2 fixups for B85M Pro4 ...................................................................... [TESTONLY] smm loader v2 fixups for B85M Pro4 Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h M src/mainboard/asrock/b85m_pro4/Kconfig 4 files changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44174/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..375c94e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -726,8 +726,18 @@ * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ - perm_smbase = mp_state.perm_smbase; - perm_smbase -= cpu * runtime->save_state_size; + if (CONFIG(X86_SMM_LOADER_VERSION2)) { + perm_smbase = smm_get_cpu_smbase(cpu); + mp_state.perm_smbase = perm_smbase; + + if (!perm_smbase) { + printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); + return; + } + } else { + perm_smbase = mp_state.perm_smbase; + perm_smbase -= cpu * runtime->save_state_size; + } printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index c084f74..e6ccfdf 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -173,7 +173,7 @@ * input: cpu_num - cpu number which is used as an index into the * map to return the smbase */ -int smm_get_cpu_smbase(unsigned int cpu_num) +u32 smm_get_cpu_smbase(unsigned int cpu_num) { if (cpu_num < CONFIG_MAX_CPUS) { if (cpus[cpu_num].active) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7838223..084d150 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -149,21 +149,19 @@ struct smm_runtime *runtime; /* The following are only used by X86_SMM_LOADER_VERSION2 */ - #if CONFIG(X86_SMM_LOADER_VERSION2) +#if CONFIG(X86_SMM_LOADER_VERSION2) unsigned int smm_entry; unsigned int smm_main_entry_offset; unsigned int smram_start; unsigned int smram_end; - #endif +#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); -#if CONFIG(X86_SMM_LOADER_VERSION2) -int smm_get_cpu_smbase(unsigned int cpu_num); -#endif +u32 smm_get_cpu_smbase(unsigned int cpu_num); /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc65120..2afc334 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -17,6 +17,7 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 + select X86_SMM_LOADER_VERSION2 config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/44174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Gerrit-Change-Number: 44174 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order
by Subrata Banik (Code Review) 03 Nov '20

03 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47057 ) Change subject: soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order ...................................................................... soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47057/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index ade2fc1..b10d88c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -53,7 +54,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index f833178..89da0be 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -54,7 +55,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index e1d474e..67bbcb2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -41,6 +41,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 9ee119f..201afec 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -53,7 +54,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 5967a69..9aa40ed 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -56,7 +57,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/47057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9 Gerrit-Change-Number: 47057 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45275 ) Change subject: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax ...................................................................... sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/usb.asl 2 files changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45275/1 diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 16db175..7c4ef34 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -40,7 +40,6 @@ } } - // USB Controller 0:1d.1 Device (USB2) @@ -60,9 +59,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -80,7 +79,6 @@ } - // USB Controller 0:1d.2 Device (USB3) @@ -100,9 +98,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -120,7 +118,6 @@ } - // USB Controller 0:1d.3 Device (USB4) @@ -140,9 +137,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U4WE) + U4WE = 3 } Else { - Store (0, U4WE) + U4WE = 0 } } @@ -160,7 +157,6 @@ } - // EHCI Controller 0:1d.7 Device (EHC1) -- To view, visit https://review.coreboot.org/c/coreboot/+/45275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Gerrit-Change-Number: 45275 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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