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Change in coreboot[master]: mb/google/link: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46176 ) Change subject: mb/google/link: Convert to ASL 2.0 syntax ...................................................................... mb/google/link: Convert to ASL 2.0 syntax Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/link/acpi/platform.asl M src/mainboard/google/link/acpi/thermal.asl 2 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46176/1 diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 35893ee..12b1453 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -7,7 +7,7 @@ Method(_PTS,1) { /* Disable WWAN */ - Store (Zero, GP36) + GP36 = 0 } /* The _WAK method is called on system wakeup */ @@ -15,16 +15,16 @@ Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDS + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index 28fa490..7ea38ae 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -15,10 +15,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -32,33 +32,33 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from TIN9/PECI via EC - Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TIN9 // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } } @@ -77,10 +77,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -106,34 +106,34 @@ Method (_TMP, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -142,7 +142,7 @@ /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -155,19 +155,19 @@ PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 \_SB.PCI0.MCHC.STND () Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 \_SB.PCI0.MCHC.STDN () Notify (\_TZ.THRM, 0x81) } @@ -176,18 +176,18 @@ PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Gerrit-Change-Number: 46176 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/beltino: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46170 ) Change subject: mb/google/beltino: Convert to ASL 2.0 syntax ...................................................................... mb/google/beltino: Convert to ASL 2.0 syntax Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/acpi/mainboard.asl M src/mainboard/google/beltino/acpi/thermal.asl 2 files changed, 57 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46170/1 diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 3049dbe..10696ff 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -14,9 +14,9 @@ Method (_DSW, 3, NotSerialized) { - Store (NIC_WAKE_GPIO, Local0) + Local0 = NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -36,9 +36,9 @@ Method (_DSW, 3, NotSerialized) { - Store (WLAN_WAKE_GPIO, Local0) + Local0 = WLAN_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 1292af4..96acaeb 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -23,10 +23,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,66 +52,66 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available" - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -119,7 +119,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -127,7 +127,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -135,7 +135,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -143,7 +143,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { Return (CTOK (FAN4_THRESHOLD_ON)) @@ -159,25 +159,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -186,25 +184,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -213,25 +209,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -240,25 +234,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -267,25 +259,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Gerrit-Change-Number: 46170 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/baskingridge: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46182 ) Change subject: mb/intel/baskingridge: Convert to ASL 2.0 syntax ...................................................................... mb/intel/baskingridge: Convert to ASL 2.0 syntax Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/baskingridge/acpi/thermal.asl 1 file changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46182/1 diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index 487b741..c1bb116 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -20,10 +20,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,7 +52,7 @@ } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -60,7 +60,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -68,7 +68,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -76,7 +76,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -84,7 +84,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -100,20 +100,20 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -121,20 +121,20 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -142,20 +142,20 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -163,20 +163,20 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -184,20 +184,20 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Gerrit-Change-Number: 46182 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION
by Bao Zheng (Code Review) 04 Nov '20

04 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46062 to review the following change. Change subject: AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION ...................................................................... AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/zork/spd/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/fw.cfg M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/fw_cz.cfg M src/soc/amd/stoneyridge/fw_st.cfg M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/fw_avl.cfg M util/amdfwtool/data_parse.c 9 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46062/1 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 1042d91..d6ae475 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -6,7 +6,7 @@ APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATION)/APCB_magic.bin $(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ $(APCB_EDIT_TOOL) \ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 44145b2..5779072 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -122,7 +122,7 @@ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock @@ -172,9 +172,9 @@ APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') # type = 0x66 -PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin -PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin -PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +PSP_UCODE_FILE1=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(FIRMWARE_LOCATION)/UcodePatch_RV2_A0.bin ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index e746d1e..516af7b 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/picasso/PSP +FIRMWARE_LOCATION 3rdparty/amd_blobs/picasso/PSP # type file AMD_PUBKEY_FILE AmdPubKeyRV.bin diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 16b8326..096b1b8 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -102,9 +102,9 @@ ### 0 -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifneq ($(FIRMWARE_LOCATE),) +ifneq ($(FIRMWARE_LOCATION),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) FIRMWARE_TYPE=ST @@ -126,11 +126,11 @@ OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware_$(FIRMWARE_TYPE).csbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE).sbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin endif ifeq ($(FIRMWARE_TYPE),ST) @@ -203,7 +203,7 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -else # ifneq ($(FIRMWARE_LOCATE),) +else # ifneq ($(FIRMWARE_LOCATION),) warn_no_amdfw: printf "\n\t** WARNING **\n" @@ -214,6 +214,6 @@ files_added:: warn_no_amdfw -endif # ifneq ($(FIRMWARE_LOCATE),) +endif # ifneq ($(FIRMWARE_LOCATION),) endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/soc/amd/stoneyridge/fw_cz.cfg b/src/soc/amd/stoneyridge/fw_cz.cfg index acbf136..a6a22f7 100644 --- a/src/soc/amd/stoneyridge/fw_cz.cfg +++ b/src/soc/amd/stoneyridge/fw_cz.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/CZ +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/CZ #PSP AMD_PUBKEY_FILE AmdPubKeyCZ.bin PSPBTLDR_FILE PspBootLoader_prod_CZ.sbin diff --git a/src/soc/amd/stoneyridge/fw_st.cfg b/src/soc/amd/stoneyridge/fw_st.cfg index aa02668..01db8b9 100644 --- a/src/soc/amd/stoneyridge/fw_st.cfg +++ b/src/soc/amd/stoneyridge/fw_st.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/ST +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/ST #XHCI_FWM_FILE xhci.bin #PSP diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0c06ee2..9792bec 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -78,29 +78,29 @@ ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin endif -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -#SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -#SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -#SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin +#SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE).sbin +#SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin +#SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuScs$(FIRMWARE_TYPE).bin +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key endif diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg index 510d6ae..eb3fac3 100644 --- a/src/southbridge/amd/pi/hudson/fw_avl.cfg +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/blobs/southbridge/amd/avalon/PSP +FIRMWARE_LOCATION 3rdparty/blobs/southbridge/amd/avalon/PSP #PSP AMD_PUBKEY_FILE AmdPubKey.bin PSPBTLDR_FILE PspBootLoader.Bypass.sbin diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index d55b0cc..d1af9e1 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -312,7 +312,7 @@ entries_line_regex, &entries_line_expr); /* Get a line */ - /* Get FIRMWARE_LOCATE in the first loop */ + /* Get FIRMWARE_LOCATION in the first loop */ while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { /* get line */ /* blank comment */ @@ -328,7 +328,7 @@ /* no match */ continue; } - if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATION") == 0) { strcpy(dir, &(oneline[match[2].rm_so])); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Gerrit-Change-Number: 46062 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: amdfwtool: Change all error output to fprintf stderr
by Bao Zheng (Code Review) 04 Nov '20

04 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45895 to review the following change. Change subject: amdfwtool: Change all error output to fprintf stderr ...................................................................... amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/data_parse.c 2 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45895/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 03afc46..c87f1b4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -523,19 +523,19 @@ fd = open(src_file, O_RDONLY); if (fd < 0) { - printf("Error opening file: %s: %s\n", + fprintf(stderr, "Error opening file: %s: %s\n", src_file, strerror(errno)); return -1; } if (fstat(fd, &fd_stat)) { - printf("fstat error: %s\n", strerror(errno)); + fprintf(stderr, "fstat error: %s\n", strerror(errno)); close(fd); return -2; } if ((size_t)fd_stat.st_size > room) { - printf("Error: %s will not fit. Exiting.\n", src_file); + fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; } @@ -543,7 +543,7 @@ bytes = read(fd, dest, (size_t)fd_stat.st_size); close(fd); if (bytes != (ssize_t)fd_stat.st_size) { - printf("Error while reading %s\n", src_file); + fprintf(stderr, "Error while reading %s\n", src_file); return -4; } @@ -746,7 +746,7 @@ } if (count > MAX_PSP_ENTRIES) { - printf("Error: PSP entries exceed max allowed items\n"); + fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); free(ctx->rom); exit(1); } @@ -862,7 +862,7 @@ if (!fw_table[i].size && !fw_table[i].src) continue; /* APOB_NV not used */ if (fw_table[i].src && !fw_table[i].size) { - printf("Error: APOB NV address provided, but no size\n"); + fprintf(stderr, "Error: APOB NV address provided, but no size\n"); free(ctx->rom); exit(1); } @@ -874,7 +874,7 @@ /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { - printf("Error: APOB destination not provided\n"); + fprintf(stderr, "Error: APOB destination not provided\n"); free(ctx->rom); exit(1); } @@ -884,12 +884,12 @@ */ if (fw_table[i].type == AMD_BIOS_BIN) { if (!fw_table[i].dest || !fw_table[i].size) { - printf("Error: BIOS binary destination and uncompressed size are required\n"); + fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); free(ctx->rom); exit(1); } if (!fw_table[i].filename && !fw_table[i].src) { - printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); + fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); free(ctx->rom); exit(1); } @@ -1006,7 +1006,7 @@ } if (count > MAX_BIOS_ENTRIES) { - printf("Error: BIOS entries (%d) exceeds max allowed items " + fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " "(%d)\n", count, MAX_BIOS_ENTRIES); free(ctx->rom); exit(1); @@ -1166,7 +1166,7 @@ uint8_t efs_spi_micron_flag) { if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { - printf("Error: EFS read mode and SPI speed must be set\n"); + fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; } switch (soc_id) { @@ -1188,7 +1188,7 @@ amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; @@ -1208,13 +1208,13 @@ amd_romsig->micron_detect_f17_mod_30_3f = 0x55; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; case PLATFORM_UNKNOWN: default: - printf("Error: Invalid SOC name.\n\n"); + fprintf(stderr, "Error: Invalid SOC name.\n\n"); return 1; } return 0; @@ -1384,7 +1384,7 @@ case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) { - printf("Error: Invalid SOC name specified\n\n"); + fprintf(stderr, "Error: Invalid SOC name specified\n\n"); retval = 1; } sub = instance = 0; @@ -1407,7 +1407,7 @@ case 'f': ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: ROM size specified" + fprintf(stderr, "Error: ROM size specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1415,7 +1415,7 @@ case 'l': dir_location = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: Directory Location specified" + fprintf(stderr, "Error: Directory Location specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1468,18 +1468,18 @@ register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); if (!output) { - printf("Error: Output value is not specified.\n\n"); + fprintf(stderr, "Error: Output value is not specified.\n\n"); retval = 1; } if (ctx.rom_size % 1024 != 0) { - printf("Error: ROM Size (%d bytes) should be a multiple of" + fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); retval = 1; } if (ctx.rom_size < MIN_ROM_KB * 1024) { - printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n", + fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", ctx.rom_size / 1024, MIN_ROM_KB); retval = 1; } @@ -1493,14 +1493,14 @@ rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; if (dir_location && (dir_location < rom_base_address)) { - printf("Error: Directory location outside of ROM.\n\n"); + fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); return 1; } if (any_location) { if (dir_location & 0x3f) { - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 64-byte aligned\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 64-byte aligned\n"); return 1; } } else { @@ -1514,16 +1514,16 @@ case 0xFF020000: /* Fall through */ break; default: - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); + fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); return 1; } } ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { - printf("Error: Failed to allocate memory\n"); + fprintf(stderr, "Error: Failed to allocate memory\n"); return 1; } memset(ctx.rom, 0xFF, ctx.rom_size); @@ -1545,11 +1545,11 @@ retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); if (retval) { - printf("ERROR: Failed to initialize EFS table!\n"); + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); return retval; } } else { - printf("WARNING: No SOC name specified.\n"); + fprintf(stderr, "WARNING: No SOC name specified.\n"); } integrate_firmwares(&ctx, amd_romsig, amd_fw_table); @@ -1623,7 +1623,7 @@ retval = 1; close(targetfd); } else { - printf("Error: could not open file: %s\n", output); + fprintf(stderr, "Error: could not open file: %s\n", output); retval = 1; } diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 7d27e52..98453ac 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -38,7 +38,7 @@ result = regcomp(reg, expr, cflags); if (result != 0) { regerror(result, reg, error_msg, ERROR_BUF_SIZE); - printf("%s\n", error_msg); + fprintf(stderr, "%s\n", error_msg); } } @@ -291,7 +291,7 @@ line[strlen(line) - 1] = '\0'; if (strlen(line) == ((size_t) (line_buf_size - 1))) { - printf("The line size in config file should be lower than %d bytes.\n", + fprintf(stderr, "The line size in config file should be lower than %d bytes.\n", MAX_LINE_SIZE); exit(1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Gerrit-Change-Number: 45895 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

5 39

Change in coreboot[master]: amdfwtool: Add an option to show debug message
by Bao Zheng (Code Review) 04 Nov '20

04 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46867 to review the following change. Change subject: amdfwtool: Add an option to show debug message ...................................................................... amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46867/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 561b511..a58cdb2 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -216,6 +216,7 @@ printf(" 0x2 Micron parts optional, this option is only\n"); printf(" supported with RN/LCN SOC\n"); printf("-c | --config <config file> Config file\n"); + printf("-d | --debug Print debug message\n"); printf("-D | --depend List out the firmware files\n"); } @@ -596,6 +597,27 @@ } } +/* For debugging */ +static void dump_psp_firmwares(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + if (index->filename) + printf(" filename=%s\n", index->filename); + } +} + +static void dump_bdt_firmwares(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + if (index->filename) + printf(" filename=%s\n", index->filename); + } +} + static void free_psp_firmware_filenames(amd_fw_entry *fw_table) { amd_fw_entry *index; @@ -1007,9 +1029,9 @@ LONGOPT_SPI_MICRON_FLAG = 258, }; -/* Unused values: BGJKNXYbdkmprstuwyz*/ +/* Unused values: BGJKNXYbkmprstuwyz*/ static const char *optstring = "x:i:g:AMn:T:SPLUW:I:a:Q:V:e:v:j:O:F:" - "H:o:f:l:hZ:qR:C:c:E:D"; + "H:o:f:l:hZ:qR:C:c:E:dD"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1052,6 +1074,7 @@ {"soc-name", required_argument, 0, 'C' }, {"config", required_argument, 0, 'c' }, + {"debug", no_argument, 0, 'd' }, {"help", no_argument, 0, 'h' }, {"depend", no_argument, 0, 'D' }, {NULL, 0, 0, 0 } @@ -1250,6 +1273,7 @@ int multi = 0; amd_cb_config cb_config; + int debug = 0; int list_deps = 0; cb_config.have_whitelist = 0; @@ -1425,6 +1449,9 @@ case 'c': config = optarg; break; + case 'd': + debug = 1; + break; case 'h': usage(); return 0; @@ -1450,6 +1477,12 @@ } fclose(config_handle); } + /* For debug. */ + if (debug == 1) { + dump_psp_firmwares(amd_psp_fw_table); + dump_bdt_firmwares(amd_bios_table); + } + if (!fuse_defined) register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); -- To view, visit https://review.coreboot.org/c/coreboot/+/46867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Gerrit-Change-Number: 46867 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/intel/emeraldlake2: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46184 ) Change subject: mb/intel/emeraldlake2: Convert to ASL 2.0 syntax ...................................................................... mb/intel/emeraldlake2: Convert to ASL 2.0 syntax Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/emeraldlake2/acpi/platform.asl M src/mainboard/intel/emeraldlake2/acpi/thermal.asl 2 files changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46184/1 diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index 9568641..9858fda 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -8,16 +8,16 @@ { // NVS has a flag to determine USB policy in S3 if (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 if (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl index 39d61b2..0a3bb49 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl @@ -21,10 +21,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,28 +50,28 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (\F2ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -79,7 +79,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -87,7 +87,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -95,7 +95,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -103,7 +103,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -119,20 +119,20 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -140,20 +140,20 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -161,20 +161,20 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -182,20 +182,20 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -203,20 +203,20 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165 Gerrit-Change-Number: 46184 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45555 ) Change subject: mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/ec.asl 1 file changed, 89 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45555/1 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae644..ac637d7 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -87,16 +87,16 @@ Method (_Q01, 0) { Notify (\_SB.CP00, 0x80) - If(ADP) { - Store(1, \_SB.AC.ACST) - TRAP(0xe3) - Store(1, PWRS) - TRAP(0x2b) + If (ADP) { + \_SB.AC.ACST = 1 + TRAP (0xe3) + PWRS = 1 + TRAP (0x2b) } Else { - Store(0, \_SB.AC.ACST) - Notify(\_SB.AC, 0x80) - Notify(\_SB.BAT0, 0x80) - Store(0, PWRS) + \_SB.AC.ACST = 0 + Notify (\_SB.AC, 0x80) + Notify (\_SB.BAT0, 0x80) + PWRS = 0 TRAP(0x2b) } @@ -107,7 +107,7 @@ Method (_Q02, 0) { - If(BAT) { + If (BAT) { Notify(\_SB.BAT0, 0x00) Notify(\_SB.AC, 0x80) } Else { @@ -132,7 +132,7 @@ { TRAP(0xe0) - If (LEqual(RTCF, 0x00)) { + If (RTCF == 0x00) { Notify(LID0, 0x80) } else { TRAP(0xc1) @@ -172,25 +172,25 @@ Method (_Q24, 0) { - Store(0x3f, HOTK) - If(IGDS) { + HOTK = 0x3f + If (IGDS) { Notify (\_SB.PCI0.GFX0, 0x82) } Else { - TRAP(0xE1) + TRAP (0xE1) } Notify (\_SB.ECO, 0x85) } Method (_Q25, 0) { - Store(0x40, HOTK) + HOTK = 0x40 TRAP(0xe1) Notify(\_SB.ECO, 0x86) } Method (_Q26, 0) { - Store(0x41, HOTK) + HOTK = 0x41 TRAP(0xe1) Notify(\_SB.ECO, 0x87) } @@ -212,7 +212,7 @@ Method (_Q2A, 0) { - Store(0x57, HOTK) + HOTK = 0x57 TRAP(0xe1) Notify(\_SB.ECO, 0x8b) } @@ -225,7 +225,7 @@ Method (_Q2C, 0) { - Store(0x59, HOTK) + HOTK = 0x59 TRAP(0xe1) } @@ -241,25 +241,25 @@ Method (_Q3A, 0) { - Store(1, BRTL) + BRTL = 1 Notify(\_SB.ECO, 0x93) } Method (_Q3B, 0) { - Store(0, BRTL) + BRTL = 0 Notify(\_SB.ECO, 0x93) } Method (_Q3C, 0) { - Store(1, SUN) + SUN = 1 Notify(\_SB.ECO, 0x92) } Method (_Q3D, 0) { - Store(0, SUN) + SUN = 0 Notify(\_SB.ECO, 0x92) } @@ -302,14 +302,14 @@ Method (_Q48, 0) { TRAP(0xd2) // Check AC Status - Store (1, ODDS) + ODDS = 1 Notify(\_SB.ECO, 0x90) } Method (_Q49, 0) { TRAP(0xd2) // Check AC Status - Store (0, ODDS) + ODDS = 0 Notify(\_SB.ECO, 0x90) } @@ -337,7 +337,7 @@ Method (_Q5C, 0) { - // Store(2, IGPS) + // IGPS = 2 Notify(\_SB.ECO, 0x94) } @@ -364,26 +364,26 @@ Method (GDPD, 0, Serialized) { // Set flag byte to zero - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x01)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x01) { + Local0 |= 0x01 } - If (And(BRTL, 0x02)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x02) { + Local0 |= 0x04 } - If (And(BRTL, 0x04)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x04) { + Local0 |= 0x02 } - If (And(BRTL, 0x30)) { - Or(Local0, 0x10, Local0) + If (BRTL & 0x30) { + Local0 |= 0x10 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x40, Local0) + If (BRTL & 0x40) { + Local0 |= 0x40 } Return (Local0) @@ -391,18 +391,18 @@ Method (GDPC, 0, Serialized) { - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x10)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x10) { + Local0 |= 0x0 } - If (And( BRTL, 0x20)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x20) { + Local0 |= 0x01 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x40) { + Local0 |= 0x02 } Return (Local0) @@ -411,7 +411,7 @@ /* Set Brightness Level */ Method(SBLL, 1, Serialized) { - Store (Arg0, BRTL) + BRTL = Arg0 TRAP(0xd5) // See mainboard's smihandler.c Return (0) } @@ -426,7 +426,7 @@ /* Get Brightness Level Medium? */ Method(GBLM, 0, Serialized) { - Store(0x3f, BRTL) + BRTL = 0x3f // XXX don't we have to set the brightness? Return(BRTL) } @@ -434,7 +434,7 @@ /* ??? */ Method(SUTE, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf5) } Else { TRAP(0xf6) @@ -462,33 +462,30 @@ /* Let coreboot update the flags */ TRAP(0xe5) - Store (0, Local0) - If(And(RFDV, 0x01)) { - Or(Local0, 0x01, Local0) + Local0 = 0 + If (RFDV & 0x01) { + Local0 |= 0x01 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x02) { + Local0 |= 0x02 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x04) { + Local0 |= 0x04 } - If(And(RFDV, 0x04)) { - Or(Local0, 0x04, Local0) + If (RFDV & 0x08) { + Local0 |= 0x08 } - If(And(RFDV, 0x08)) { - Or(Local0, 0x08, Local0) + If (GP15 & 0x01) { // GDIS + Local0 |= 0x10 } - If(And(GP15, 0x01)) { // GDIS - Or(Local0, 0x10, Local0) + If (GP12 & 0x01) { // WIFI Led (WLED) + Local0 |= 0x20 } - If(And(GP12, 0x01)) { // WIFI Led (WLED) - Or(Local0, 0x20, Local0) + If (BTEN & 0x01) { // BlueTooth Enable + Local0 |= 0x40 } - If(And(BTEN, 0x01)) { // BlueTooth Enable - Or(Local0, 0x40, Local0) - } - If(And(GP10, 0x01)) { // GPS Enable - Or(Local0, 0x80, Local0) + If (GP10 & 0x01) { // GPS Enable + Local0 |= 0x80 } Return (Local0) @@ -497,30 +494,30 @@ /* Set RFD */ Method(SRFD, 1, Serialized) { - If (And(Arg0, 0x01)) { - Store (1, GP14) // GLED - Store (1, GP15) // GDIS + If (Arg0 & 0x01) { + GP14 = 1 // GLED + GP15 = 1 // GDIS } Else { - Store (0, GP14) - Store (0, GP15) + GP14 = 0 + GP15 = 0 } /* WIFI */ - If (And(Arg0, 0x02)) { - Store (1, GP12) // WLED - Store (1, GP25) // WLAN + If (Arg0 & 0x02) { + GP12 = 1 // WLED + GP25 = 1 // WLAN } Else { - Store (0, GP12) - Store (0, GP25) + GP12 = 0 + GP25 = 0 } /* Bluetooth */ - If (And(Arg0, 0x04)) { - Store (1, GP13) // BLED - Store (1, BTEN) + If (Arg0 & 0x04) { + GP13 = 1 // BLED + BTEN = 1 } Else { - Store (0, GP13) // BLED - Store (0, BTEN) + GP13 = 0 // BLED + BTEN = 0 } Return (0) } @@ -542,7 +539,7 @@ /* Set IGD (Graphics) */ Method(SIGD, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf7) } Else { TRAP(0xf8) @@ -553,7 +550,7 @@ /* SMI-C? Set Mic? */ Method (SMIC, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xeb) } Else { TRAP(0xec) @@ -570,7 +567,7 @@ /* Not even decent function names anymore? */ Method(S024, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf1) } Else { TRAP(0xf2) @@ -588,13 +585,13 @@ /* ??? Something with PATA */ Method(S025, 1, Serialized) { - If(And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xfc) - Store (1, GP33) // CREN + GP33 = 1 // CREN Sleep(1500) - Store (1, GP34) // CRRS + GP34 = 1 // CRRS Sleep(500) Notify(^^PCI0.PATA, 0) @@ -602,7 +599,7 @@ } Else { TRAP(0xfb) Sleep(1500) - Store(0, GP33) // CREN + GP33 = 0 // CREN Sleep(1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID, 0) @@ -616,16 +613,16 @@ Method(G021, 0, Serialized) { TRAP(0xfe) - If (LEqual(ACIN, 0)) { + If (ACIN == 0) { TRAP(0xfa) TRAP(0xfd) - If (LEqual(ODDS, 1)) { + If (ODDS == 1) { TRAP(0xfb) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) Notify(^^PCI0.PATA.PRID.DSK0, 1) Sleep (1500) - Store (0, GP33) // CREN + GP33 = 0 // CREN Sleep (1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) @@ -648,7 +645,7 @@ /* ??? */ Method(S00B, 1, Serialized) { - If (And(Arg0, 1)) { + If (Arg0 & 1) { TRAP(0xdc) } Else { TRAP(0xdd) -- To view, visit https://review.coreboot.org/c/coreboot/+/45555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Gerrit-Change-Number: 45555 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/getac/p470/acpi/ec.asl: Remove duplicated code
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45865 ) Change subject: mb/getac/p470/acpi/ec.asl: Remove duplicated code ...................................................................... mb/getac/p470/acpi/ec.asl: Remove duplicated code "If(And(RFDV, 0x02)) {Or(Local0, 0x02, Local0)}" is duplicated. Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/ec.asl 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45865/1 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae644..5c0f4d8 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -469,9 +469,6 @@ If(And(RFDV, 0x02)) { Or(Local0, 0x02, Local0) } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) - } If(And(RFDV, 0x04)) { Or(Local0, 0x04, Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Gerrit-Change-Number: 45865 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: acpi/acpi.h: Update region spaces
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46445 ) Change subject: acpi/acpi.h: Update region spaces ...................................................................... acpi/acpi.h: Update region spaces Update operation region spaces according to ACPI Release 6.3 Errata A. Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/acpi/acpi.h 1 file changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46445/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index a9ec077..78740fb 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -99,19 +99,24 @@ u32 addrh; /* Register address, high 32 bits */ } __packed acpi_addr_t; -#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ -#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ -#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ -#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ -#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ +#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_CMOS 5 /* SystemCMOS */ +#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET 6 /* PciBarTarget */ +#define ACPI_ADDRESS_SPACE_IPMI 7 /* IPMI */ +#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO 8 /* GeneralPurposeIO */ +#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS 9 /* GenericSerialBus */ +#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ +#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2 Gerrit-Change-Number: 46445 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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