coreboot-gerrit October 2020

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Change in coreboot[master]: util/qemu: Add comprehensive default config for QEMU Q35
by Nico Huber (Code Review) 04 Nov '20

04 Nov '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46768 ) Change subject: util/qemu: Add comprehensive default config for QEMU Q35 ...................................................................... util/qemu: Add comprehensive default config for QEMU Q35 This config tries to mimic the actual devices of a mainboard with Intel's Q35 chipset. It provides a much better base to test coreboot (e.g. its allocator) and payloads. Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/qemu/Makefile.inc A util/qemu/q35-base.cfg 2 files changed, 182 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46768/1 diff --git a/util/qemu/Makefile.inc b/util/qemu/Makefile.inc index 33463498..651ef21 100644 --- a/util/qemu/Makefile.inc +++ b/util/qemu/Makefile.inc @@ -27,7 +27,9 @@ # $ make qemu QEMU_CFG_ARGS= QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc + QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= qemu-system-x86_64 -M q35 +QEMU_CFG-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= util/qemu/q35-base.cfg ifneq ($(QEMU-y),) diff --git a/util/qemu/q35-base.cfg b/util/qemu/q35-base.cfg new file mode 100644 index 0000000..87dcfcd --- /dev/null +++ b/util/qemu/q35-base.cfg @@ -0,0 +1,180 @@ +# $ qemu-system-x86_64 -nodefaults -readconfig q35-base.cfg -readconfig ... +# +# Devices that show up even with `-nodefaults`: +# 00.0 Host bridge +# 1f.0 LPC bridge +# 1f.2 SATA controller (AHCI mode) +# 1f.3 SMBus controller + +[machine] + type = "q35" + accel = "kvm:tcg" + +[memory] + size = "1024" + + +[device "q35-peg"] + driver = "pcie-root-port" + bus = "pcie.0" + addr = "01.0" + + +[device "q35-igpu"] + driver = "VGA" + bus = "pcie.0" + addr = "02.0" + + +[netdev "hostnet"] + type = "user" + +[device "net"] + driver = "e1000" + netdev = "hostnet" + bus = "pcie.0" + addr = "19.0" + + +[device "ich9-ehci-2"] + driver = "ich9-usb-ehci2" + multifunction = "on" + bus = "pcie.0" + addr = "1a.7" + +[device "ich9-uhci-4"] + driver = "ich9-usb-uhci4" + multifunction = "on" + bus = "pcie.0" + addr = "1a.0" + masterbus = "ich9-ehci-2.0" + firstport = "0" + +[device "ich9-uhci-5"] + driver = "ich9-usb-uhci5" + multifunction = "on" + bus = "pcie.0" + addr = "1a.1" + masterbus = "ich9-ehci-2.0" + firstport = "2" + +[device "ich9-uhci-6"] + driver = "ich9-usb-uhci6" + multifunction = "on" + bus = "pcie.0" + addr = "1a.2" + masterbus = "ich9-ehci-2.0" + firstport = "4" + + +[device "ich9-hda-audio"] + driver = "ich9-intel-hda" + bus = "pcie.0" + addr = "1b.0" + +[device "ich9-hda-duplex"] + driver = "hda-duplex" + bus = "ich9-hda-audio.0" + cad = "0" + + +[device "ich9-pcie-port-1"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.0" + port = "1" + chassis = "1" + +[device "ich9-pcie-port-2"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.1" + port = "2" + chassis = "2" + +[device "ich9-pcie-port-3"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.2" + port = "3" + chassis = "3" + +[device "ich9-pcie-port-4"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.3" + port = "4" + chassis = "4" + +[device "ich9-pcie-port-5"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.4" + port = "5" + chassis = "5" + +[device "ich9-pcie-port-6"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.5" + port = "6" + chassis = "6" + +[device "ich9-pcie-port-7"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.6" + port = "7" + chassis = "7" + +[device "ich9-pcie-port-8"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.7" + port = "8" + chassis = "8" + + +[device "ich9-ehci-1"] + driver = "ich9-usb-ehci1" + multifunction = "on" + bus = "pcie.0" + addr = "1d.7" + +[device "ich9-uhci-1"] + driver = "ich9-usb-uhci1" + multifunction = "on" + bus = "pcie.0" + addr = "1d.0" + masterbus = "ich9-ehci-1.0" + firstport = "0" + +[device "ich9-uhci-2"] + driver = "ich9-usb-uhci2" + multifunction = "on" + bus = "pcie.0" + addr = "1d.1" + masterbus = "ich9-ehci-1.0" + firstport = "2" + +[device "ich9-uhci-3"] + driver = "ich9-usb-uhci3" + multifunction = "on" + bus = "pcie.0" + addr = "1d.2" + masterbus = "ich9-ehci-1.0" + firstport = "4" + + +[device "ich9-pci-bridge"] + driver = "i82801b11-bridge" + bus = "pcie.0" + addr = "1e.0" -- To view, visit https://review.coreboot.org/c/coreboot/+/46768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822 Gerrit-Change-Number: 46768 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: util/qemu: Add `qemu` make target
by Nico Huber (Code Review) 04 Nov '20

04 Nov '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46767 ) Change subject: util/qemu: Add `qemu` make target ...................................................................... util/qemu: Add `qemu` make target Add some mechanics to automatically have a `qemu` make target for supported configurations. So with a QEMU target selected in Kconfig, one would ideally only have to run `make qemu` to test things. There are some notable variables that can be set or adapted in `Makefile.inc` files, the make command line or the environment. Primarily for `Makefile.inc` use: QEMU-y the QEMU executable QEMU_CFG-y a QEMU config that sets the available default devices, used to run more comprehensive tests by default, e.g. many more PCI devices For general use: QEMU_ARGS additional command line arguments (default: -serial stdio) QEMU_EXTRA_CFGS additional config files that can add devices QEMU_CFG_ARGS gathers config file related arguments, can be used to override a default config (QEMU_CFG-y) Examples: $ # Run coreboot's default config with additional command line args $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" $ # Force QEMU's built-in config $ make qemu QEMU_CFG_ARGS= Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile.inc A util/qemu/Makefile.inc 2 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46767/1 diff --git a/Makefile.inc b/Makefile.inc index 297f7b1..dbf702a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -83,7 +83,7 @@ subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool -subdirs-y += util/futility util/marvell util/bincfg util/supermicro +subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security diff --git a/util/qemu/Makefile.inc b/util/qemu/Makefile.inc new file mode 100644 index 0000000..33463498 --- /dev/null +++ b/util/qemu/Makefile.inc @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# This automatically adds a `qemu` make target if a compatible +# configuration is selected. There are some notable variables +# that can be set or adapted in `Makefile.inc` files, the make +# command line or the environment: +# +# Primarily for `Makefile.inc` use: +# QEMU-y the QEMU executable +# QEMU_CFG-y a QEMU config that sets the available default devices, +# used to run more comprehensive tests by default, +# e.g. many more PCI devices +# +# For general use: +# QEMU_ARGS additional command line arguments (default: -serial stdio) +# QEMU_EXTRA_CFGS additional config files that can add devices +# +# QEMU_CFG_ARGS gathers config file related arguments, +# can be used to override a default config (QEMU_CFG-y) +# +# Examples: +# +# $ # Run coreboot's default config with additional command line args +# $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" +# +# $ # Force QEMU's built-in config +# $ make qemu QEMU_CFG_ARGS= + +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= qemu-system-x86_64 -M q35 + +ifneq ($(QEMU-y),) + +QEMU_ARGS ?= -serial stdio +QEMU_EXTRA_CFGS ?= + +QEMU_CFG_ARGS ?= \ + $(if $(QEMU_CFG-y),-nodefaults) \ + $(addprefix -readconfig ,$(QEMU_CFG-y) $(QEMU_EXTRA_CFGS)) + +qemu: $(obj)/coreboot.rom + $(QEMU-y) $(QEMU_CFG_ARGS) $(QEMU_ARGS) -bios $< + +.PHONY: qemu + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75 Gerrit-Change-Number: 46767 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer
by Jacob Garber (Code Review) 04 Nov '20

04 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46729 ) Change subject: soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer ...................................................................... soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a constant pointer rather than making a copy. Found-by: Coverity CID 1432759 Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46729/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 1329feb..8bd8c41 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -195,16 +195,16 @@ * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource->StackRes[stack].BusBase; + const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -301,7 +301,7 @@ hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, - iio_resource, pcie_seg, false, NULL); + &iio_resource, pcie_seg, false, NULL); // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && @@ -365,7 +365,7 @@ if (socket == 0 && p == PORT_0) continue; current += acpi_create_dmar_ds_pci_br_for_port(current, p, - stack, iio_resource, pcie_seg, true, &first); + stack, &iio_resource, pcie_seg, true, &first); } } if (tmp != current) -- To view, visit https://review.coreboot.org/c/coreboot/+/46729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 Gerrit-Change-Number: 46729 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/volteer: clang-format of mainboard.c
by Jes Klinke (Code Review) 04 Nov '20

04 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47048 to review the following change. Change subject: mb/google/volteer: clang-format of mainboard.c ...................................................................... mb/google/volteer: clang-format of mainboard.c This CL is entirely generated by running the autmatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47048/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd..b4d6676 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -51,8 +51,7 @@ return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && - cr50_is_long_interrupt_pulse_enabled()) { + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* @@ -75,8 +74,7 @@ base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); - gpio_configure_pads_with_override(base_pads, base_num, - override_pads, override_num); + gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -84,14 +82,13 @@ bool has_usb4; /* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); if (!has_usb4) - memset(params->ITbtPcieRootPortEn, - 0, - ARRAY_SIZE(params->ITbtPcieRootPortEn) * - sizeof(*params->ITbtPcieRootPortEn)); + memset(params->ITbtPcieRootPortEn, 0, + ARRAY_SIZE(params->ITbtPcieRootPortEn) + * sizeof(*params->ITbtPcieRootPortEn)); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Gerrit-Change-Number: 47048 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
by Arthur Heymans (Code Review) 04 Nov '20

04 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46895 ) Change subject: soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T ...................................................................... soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46895/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 975afc9..28e7b83 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -27,22 +27,25 @@ config DCACHE_RAM_BASE hex - default 0xfe8b0000 + default 0xfe800000 config DCACHE_RAM_SIZE hex - default 0x170000 + default 0x1fff00 help The size of the cache-as-ram region required during bootblock - and/or romstage. + and/or romstage. FSP-T reserves the upper 0x100 for + FspReservedBuffer. config DCACHE_BSP_STACK_SIZE hex - default 0xA0000 + default 0x140000 help The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and - CB romstage stack requirement. + CB romstage stack requirement. The integration documentation + says this needs to be 256KiB, but practice show this needs to + be a lot more. config CPU_MICROCODE_CBFS_LOC hex @@ -67,11 +70,13 @@ config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0xA0000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. + the exact FSP requirement for Heap setup. The FSP integration + documentation says this needs to be at least 128KiB, but practice + show this needs to be 256KiB or more. config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/46895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Gerrit-Change-Number: 46895 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Don't enable Bus Master
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47031 ) Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ...................................................................... sb/intel/lynxpoint/sata.c: Don't enable Bus Master Bus Master is not required and reference code does not set it. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47031/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 4174e1f..d8eb2a8 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -51,9 +51,8 @@ /* SATA configuration */ - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Gerrit-Change-Number: 47031 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/intel/broadwell: Relocate PCH ACPI files
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46754 ) Change subject: soc/intel/broadwell: Relocate PCH ACPI files ...................................................................... soc/intel/broadwell: Relocate PCH ACPI files Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/soc/intel/broadwell/pch/acpi/adsp.asl R src/soc/intel/broadwell/pch/acpi/device_nvs.asl R src/soc/intel/broadwell/pch/acpi/ehci.asl R src/soc/intel/broadwell/pch/acpi/globalnvs.asl R src/soc/intel/broadwell/pch/acpi/gpio.asl R src/soc/intel/broadwell/pch/acpi/hda.asl R src/soc/intel/broadwell/pch/acpi/irqlinks.asl R src/soc/intel/broadwell/pch/acpi/lpc.asl R src/soc/intel/broadwell/pch/acpi/pch.asl R src/soc/intel/broadwell/pch/acpi/pcie.asl R src/soc/intel/broadwell/pch/acpi/pcie_port.asl R src/soc/intel/broadwell/pch/acpi/sata.asl R src/soc/intel/broadwell/pch/acpi/serialio.asl R src/soc/intel/broadwell/pch/acpi/smbus.asl R src/soc/intel/broadwell/pch/acpi/xhci.asl 19 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46754/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 32c71de..a61a669 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -16,7 +16,7 @@ #include "acpi/thermal.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -25,7 +25,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 3746d4b..6af99b4 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ #include <variant/acpi/thermal.asl> // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index b3b2ca6..c842e8b 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 4d81e15..a4b5bd8 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -13,7 +13,7 @@ #include <soc/intel/broadwell/acpi/platform.asl> /* Global NVS and variables */ - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -22,7 +22,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/pch/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/soc/intel/broadwell/pch/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/pch/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/soc/intel/broadwell/pch/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/pch/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/soc/intel/broadwell/pch/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/soc/intel/broadwell/pch/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/soc/intel/broadwell/pch/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/pch/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/soc/intel/broadwell/pch/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/soc/intel/broadwell/pch/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/soc/intel/broadwell/pch/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/soc/intel/broadwell/pch/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/soc/intel/broadwell/pch/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/soc/intel/broadwell/pch/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/pch/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/soc/intel/broadwell/pch/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/soc/intel/broadwell/pch/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/pch/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/soc/intel/broadwell/pch/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/soc/intel/broadwell/pch/acpi/xhci.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/46754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Gerrit-Change-Number: 46754 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Move smmrelocate.c MSR definitions to header
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46733 ) Change subject: cpu/intel/haswell: Move smmrelocate.c MSR definitions to header ...................................................................... cpu/intel/haswell: Move smmrelocate.c MSR definitions to header Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/smmrelocate.c 2 files changed, 20 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46733/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e0e1e1c..9349a3d 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -76,6 +76,26 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) + +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bit definitions */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 2fc20aa..9e3554f 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,22 +17,6 @@ #include <smp/node.h> #include "haswell.h" -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) -- To view, visit https://review.coreboot.org/c/coreboot/+/46733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Gerrit-Change-Number: 46733 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Revert "broadwell: Switch to using common ACPI _SWS code"
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Duncan Laurie, Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46734 to review the following change. Change subject: Revert "broadwell: Switch to using common ACPI _SWS code" ...................................................................... Revert "broadwell: Switch to using common ACPI _SWS code" This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267. Reason for revert: Blocks merging Haswell and Broadwell together. Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi/platform.asl M src/soc/intel/broadwell/ramstage.c 3 files changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46734/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6561fe2..e01d559 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -42,7 +42,6 @@ select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index c00edeb..d302720 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -18,9 +18,6 @@ * Foundation, Inc. */ -/* Enable ACPI _SWS methods */ -#include <soc/intel/common/acpi/acpi_wake_source.asl> - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) @@ -74,3 +71,21 @@ { Return (Package (){ 0, 0 }) } + +Scope (\_SB) +{ + Method (_SWS) + { + /* Index into PM1 for device that caused wake */ + Return (\PM1I) + } +} + +Scope (\_GPE) +{ + Method (_SWS) + { + /* Index into GPE for device that caused wake */ + Return (\GPEI) + } +} diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index c8fb6ed..e699e02 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -27,23 +27,56 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> -#include <soc/intel/common/acpi.h> -/* Save wake source information for calculating ACPI _SWS values */ -int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) +/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ +static void save_acpi_wake_source(global_nvs_t *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - static uint32_t gpe0_sts[GPE0_REG_MAX]; - int i; + uint16_t pm1; + int gpe_reg; - *pm1 = ps->pm1_sts & ps->pm1_en; + if (!ps) + return; - /* Mask off GPE0 status bits that are not enabled */ - *gpe0 = &gpe0_sts[0]; - for (i = 0; i < GPE0_REG_MAX; i++) - gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + pm1 = ps->pm1_sts & ps->pm1_en; - return GPE0_REG_MAX; + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + gnvs->gpei = -1; + for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { + u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; + int start = gpe_reg * GPE0_REG_SIZE; + int end = start + GPE0_REG_SIZE; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + gnvs->pm1i, gnvs->gpei); } static void s3_resume_prepare(void) @@ -56,6 +89,8 @@ if (!acpi_is_wakeup_s3()) memset(gnvs, 0, sizeof(global_nvs_t)); + else + save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/46734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Gerrit-Change-Number: 46734 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_cnl: Adjust in preparation for new variants
by Matt DeVillier (Code Review) 03 Nov '20

03 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47051 ) Change subject: mb/purism/librem_cnl: Adjust in preparation for new variants ...................................................................... mb/purism/librem_cnl: Adjust in preparation for new variants - Move the SoC select to board config (vs baseboard config) - Qualify the VGA PCI ID and CBFS size values based on board selection - Move devicetree to variant dir and add Kconfig entry - Use a separate board_info.txt for the baseboard and each variant Change-Id: I4764f2c1243ea49bd08e0735865cc3cb7a66441f Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig M src/mainboard/purism/librem_cnl/Kconfig.name M src/mainboard/purism/librem_cnl/board_info.txt A src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt R src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 5 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47051/1 diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 38be380..464350c 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -9,7 +9,6 @@ select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_WHISKEYLAKE select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER @@ -31,9 +30,13 @@ string default "librem_mini" if BOARD_PURISM_LIBREM_MINI +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config CBFS_SIZE hex - default 0x800000 + default 0x800000 if BOARD_PURISM_LIBREM_MINI config MAX_CPUS int @@ -49,7 +52,7 @@ config VGA_BIOS_ID string - default "8086,3ea0" + default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI config PXE_ROM_ID string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name index 326165ba..83f1495 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -1,3 +1,4 @@ config BOARD_PURISM_LIBREM_MINI bool "Librem Mini" select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select SOC_INTEL_WHISKEYLAKE diff --git a/src/mainboard/purism/librem_cnl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt index ca61edd..6c7620c 100644 --- a/src/mainboard/purism/librem_cnl/board_info.txt +++ b/src/mainboard/purism/librem_cnl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: Purism -Board name: librem_cnl -Category: desktop +Board name: Librem Cannonlake baseboard +Category: misc Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt new file mode 100644 index 0000000..843ff9f --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem Mini +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb similarity index 100% rename from src/mainboard/purism/librem_cnl/devicetree.cb rename to src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/47051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4764f2c1243ea49bd08e0735865cc3cb7a66441f Gerrit-Change-Number: 47051 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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