coreboot-gerrit October 2020

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Change in coreboot[master]: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45281 ) Change subject: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax ...................................................................... mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/d945gclf/acpi/platform.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45281/1 diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 30e4d2c..cf73fc1 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -20,12 +20,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } -- To view, visit https://review.coreboot.org/c/coreboot/+/45281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Gerrit-Change-Number: 45281 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Add support for link time optimization
by Jacob Garber (Code Review) 03 Nov '20

03 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38291 ) Change subject: libpayload: Add support for link time optimization ...................................................................... libpayload: Add support for link time optimization Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 149K 11.49s LTO 125K 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38291/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e3..9312f19 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,6 +80,13 @@ endchoice +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1b7986c..ecf7937 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -65,6 +65,10 @@ CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Gerrit-Change-Number: 38291 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: cpu/x86/mp_init: Add support for x86_64
by Patrick Rudolph (Code Review) 03 Nov '20

03 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44675 ) Change subject: cpu/x86/mp_init: Add support for x86_64 ...................................................................... cpu/x86/mp_init: Add support for x86_64 Fix compilation on x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44675/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..da0002f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -113,7 +113,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -339,16 +339,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/44675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Gerrit-Change-Number: 44675 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: pass verstage timestamps to x86
by Kangheui Won (Code Review) 02 Nov '20

02 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45059 ) Change subject: soc/amd/picasso: pass verstage timestamps to x86 ...................................................................... soc/amd/picasso: pass verstage timestamps to x86 Remove stubs for psp_verstage and initialize timestamp table with data from psp_verstage on bootblock. We need to convert numbers since timestamps on verstage uses microseconds granularity and x86 uses TSC. BUG=b:154142138, b:159220781 BRANCH=zork TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are included in the result. Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Signed-off-by: Kangheui Won <khwon(a)chromium.org> --- M src/include/bootblock_common.h M src/lib/Makefile.inc M src/lib/bootblock.c M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/psp_verstage/Makefile.inc M src/soc/amd/picasso/psp_verstage/psp_verstage.c D src/soc/amd/picasso/psp_verstage/timestamp.c 7 files changed, 43 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45059/1 diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96..da627d2 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -29,6 +29,8 @@ asmlinkage void ap_bootblock_c_entry(void); void bootblock_main_with_basetime(uint64_t base_timestamp); +void bootblock_main_with_timestamp(uint64_t base_timestamp, + struct timestamp_entry *timestamps, size_t num_timestamps); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4ce133a..5a960e9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -68,10 +68,7 @@ verstage-y += memcmp.c verstage-y += string.c -# TODO: Remove this when PSP bootblock timestamps are implemented. -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 1c433d0..3e2ef06 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,7 +25,7 @@ * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ -static void bootblock_main_with_timestamp(uint64_t base_timestamp, +void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4700027..2ba6be9 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> +#include <timestamp.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -119,7 +120,44 @@ write_resume_eip(); enable_pci_mmconf(); +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) + struct transfer_info_struct *info = (struct transfer_info_struct *) + CONFIG_PSP_SHAREDMEM_BASE; + + if (info->magic_val == TRANSFER_MAGIC_VAL && + info->timestamp_offset != 0) { + int i; + uint32_t tick_freq_mhz = timestamp_tick_freq_mhz(); + struct timestamp_table *psp_ts_table = (struct timestamp_table *) + (CONFIG_PSP_SHAREDMEM_BASE + info->timestamp_offset); + + /* if we're unable to determine timestamp tick, leave it as raw number */ + if (tick_freq_mhz == 0) { + tick_freq_mhz = 1; + } + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * Since bootblock_main_with_timestamp calls timestamp_add and + * timestamp_add subtracts base_time, we need to add base_time here. + * Also values are in us so multiply it by tick_freq_mhz + */ + uint64_t abs_stamp = psp_ts_table->base_time + tse->entry_stamp; + tse->entry_stamp = abs_stamp * tick_freq_mhz; + } + + base_timestamp = psp_ts_table->base_time * tick_freq_mhz; + bootblock_main_with_timestamp(base_timestamp, + psp_ts_table->entries, psp_ts_table->num_entries); + + } else { + bootblock_main_with_basetime(base_timestamp); + } +#else bootblock_main_with_basetime(base_timestamp); +#endif + } void bootblock_soc_early_init(void) diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 905613e..4f1642b 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -15,7 +15,6 @@ verstage-y += reset.c verstage-y += svc.c verstage-y += timer.c -verstage-y += timestamp.c verstage-y += vboot_crypto.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index ef4884f..b429ef3 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -16,6 +16,7 @@ #include <arch/stages.h> #include <stdarg.h> #include <stdio.h> +#include <timestamp.h> extern char _bss_start, _bss_end; static struct mem_region_device boot_dev = @@ -207,6 +208,7 @@ * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() */ + timestamp_init(timestamp_get()); svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); diff --git a/src/soc/amd/picasso/psp_verstage/timestamp.c b/src/soc/amd/picasso/psp_verstage/timestamp.c deleted file mode 100644 index b3b8f75..0000000 --- a/src/soc/amd/picasso/psp_verstage/timestamp.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <timestamp.h> - -/* Stubs */ -void timestamp_add_now(enum timestamp_id id) -{ -} - -void timestamp_add(enum timestamp_id id, uint64_t ts) -{ -} - -uint64_t timestamp_get(void) -{ - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Gerrit-Change-Number: 45059 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

7 44

Change in coreboot[master]: soc/amd/picasso: add monotonic_timer
by Kangheui Won (Code Review) 02 Nov '20

02 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46058 ) Change subject: soc/amd/picasso: add monotonic_timer ...................................................................... soc/amd/picasso: add monotonic_timer To accommodate better with PSP timestamp, add a layer around tsc to have microsecond granularity for timestamp table. BUG=b:159220781 BRANCH=zork TEST=build, flash and boot, check timestamps are correct Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/monotonic_timer.c 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46058/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6a5b932..360d59d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -24,7 +24,7 @@ select IOAPIC select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS - select TSC_MONOTONIC_TIMER + select COLLECT_TIMESTAMPS_NO_TSC select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..76fd100 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c @@ -32,6 +33,7 @@ romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +romstage-y += monotonic_timer.c romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c @@ -47,6 +49,7 @@ verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +verstage_x86-y += monotonic_timer.c verstage_x86-y += tsc_freq.c verstage_x86-y += reset.c @@ -70,6 +73,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +ramstage-y += monotonic_timer.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c @@ -84,6 +88,7 @@ smm-y += smihandler.c smm-y += smi_util.c +smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c new file mode 100644 index 0000000..941532c --- /dev/null +++ b/src/soc/amd/picasso/monotonic_timer.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <timer.h> +#include <timestamp.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timestamp_get()); +} + +uint64_t timestamp_get(void) +{ + return rdtscll() / tsc_freq_mhz(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc Gerrit-Change-Number: 46058 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 11

Change in em100[master]: Fix compatibility with old libcurl
by Stefan Reinauer (Code Review) 02 Nov '20

02 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/46926 ) Change subject: Fix compatibility with old libcurl ...................................................................... Fix compatibility with old libcurl libcurl versions before 7.32.00 didn't have CURLOPT_XFERINFOFUNCTION. Put the code using that macro under version-dependant contitionals. Signed-off-by: Alexander Amelkin <a.amelkin(a)yadro.com> Change-Id: Ib40a5ba9b5a52a82ad1e388b6fa46c854a10113e --- M curl.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/26/46926/1 diff --git a/curl.c b/curl.c index d13dfe8..e6ee8bb 100644 --- a/curl.c +++ b/curl.c @@ -36,6 +36,7 @@ #define TIMEOPT CURLINFO_TOTAL_TIME_T #define MINIMAL_PROGRESS_FUNCTIONALITY_INTERVAL 3000000 +#if LIBCURL_VERSION_NUM >= 0x073200 static int xferinfo(void *p __unused, curl_off_t dltotal __unused, curl_off_t dlnow __unused, curl_off_t ultotal __unused, curl_off_t ulnow __unused) @@ -51,6 +52,7 @@ pos = (pos + 1) % 4; return 0; } +#endif static size_t write_data(void *ptr, size_t size, size_t nmemb, void *stream) @@ -58,7 +60,7 @@ return fwrite(ptr, size, nmemb, (FILE *) stream); } -static int curl_get(const char *id, const char *filename, int progress) +static int curl_get(const char *id, const char *filename, int progress __unused) { FILE *file; CURLcode res; @@ -97,6 +99,7 @@ /* Write data to this file handle */ curl_easy_setopt(curl, CURLOPT_WRITEDATA, file); +#if LIBCURL_VERSION_NUM >= 0x073200 if (progress) { /* Simple progress indicator function */ curl_easy_setopt(curl, CURLOPT_XFERINFOFUNCTION, xferinfo); @@ -104,6 +107,7 @@ /* Enable progress indicator */ curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0L); } +#endif /* Follow redirections (as used by Google Drive) */ curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION , 1L); -- To view, visit https://review.coreboot.org/c/em100/+/46926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ib40a5ba9b5a52a82ad1e388b6fa46c854a10113e Gerrit-Change-Number: 46926 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: coreinfo: Add support for link time optimization
by Jacob Garber (Code Review) 02 Nov '20

02 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38293 ) Change subject: coreinfo: Add support for link time optimization ...................................................................... coreinfo: Add support for link time optimization This introduces a Kconfig option for compiling coreinfo with LTO. This option can be used independently of LTO in libpayload, though will benefit most if that is enabled as well. If both are enabled, the final size of coreinfo.elf is reduced from 125K to 122K. Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/coreinfo/Kconfig M payloads/coreinfo/Makefile 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38293/1 diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index fd4c1b4..5fb17bb 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -56,6 +56,13 @@ help The version number of this payload. +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 34c45d9..6452c00 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -90,9 +90,13 @@ include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Gerrit-Change-Number: 38293 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

8 18

Change in coreboot[master]: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 02 Nov '20

02 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45418 ) Change subject: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Signed-off-by: Manideep Kurumella <mkurumel(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/soc.c 3 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45418/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bb..b369d55 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,6 +9,7 @@ DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..80df6c8 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -52,6 +52,7 @@ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem, 0x86000000, 0x8C00000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..30ad967 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -15,6 +15,8 @@ REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + reserved_ram_resource(dev, 3, (uintptr_t)_dram_modem / KiB, + REGION_SIZE(dram_modem) / KiB); } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Gerrit-Change-Number: 45418 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 02 Nov '20

02 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46661 ) Change subject: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. two different modem regions wifi and lte to be handled in QC_SEC and modem Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Signed-off-by: Manideep Kurumella <mkurumel(a)codeaurora.org> Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8 --- M src/soc/qualcomm/common/include/soc/mmu_common.h M src/soc/qualcomm/common/mmu.c M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/carve_out.c M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/soc.c 7 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46661/1 diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index a38196f..b6c8aab 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -14,5 +14,6 @@ void soc_mmu_dram_config_post_dram_init(void); void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); +bool soc_modem_carve_out(void **start, void **end); #endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index 4f606be..ba1173e 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -4,10 +4,19 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> +__weak bool soc_modem_carve_out(void **start, void **end) { return false; } __weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) { - mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + void *start = NULL; + void *end = NULL; + + if (!soc_modem_carve_out(&start, &end)) { + mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + } else { + mmu_config_range(ddr_base, start - ddr_base, CACHED_RAM); + mmu_config_range(end, ddr_base + ddr_size - end, CACHED_RAM); + } soc_mmu_dram_config_post_dram_init(); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7f52a9a..07d2652 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += gpio.c romstage-y += qupv3_i2c.c romstage-y += clock.c +romstage-y += carve_out.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c romstage-y += qcom_qup_se.c romstage-y += qupv3_config.c @@ -52,6 +53,7 @@ ################################################################################ ramstage-y += soc.c +ramstage-y += carve_out.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += qupv3_spi.c diff --git a/src/soc/qualcomm/sc7180/carve_out.c b/src/soc/qualcomm/sc7180/carve_out.c new file mode 100644 index 0000000..0f0bdd5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/carve_out.c @@ -0,0 +1,26 @@ +#include <arch/stages.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> +#include <device/mmio.h> + +#define MODEM_ID_ADDR (void *)0x146ABC00 +#define MODEM_ID_LTE 0x004c5445 +#define MODEM_ID_WIFI 0x57494649 +#define MODEM_ID_WIFI_END (void *)0x88000000 + +bool soc_modem_carve_out(void **start, void **end) +{ + uint32_t modem_id = read32(MODEM_ID_ADDR); + switch (modem_id) { + case MODEM_ID_LTE: + *start = _dram_modem; + *end = _edram_modem; + return true; + case MODEM_ID_WIFI: + *start = _dram_modem; + *end = MODEM_ID_WIFI_END; + return true; + default: + return false; + } +} diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bb..b369d55 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,6 +9,7 @@ DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index ce08478..e450c33 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -51,6 +51,7 @@ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem, 0x86000000, 0x8C00000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..9037c45 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -9,12 +9,18 @@ static void soc_read_resources(struct device *dev) { + void *start = NULL; + void *end = NULL; + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + if (soc_modem_carve_out(&start, &end)) { + reserved_ram_resource(dev, 3, (uintptr_t)start / KiB, (end - start) / KiB); + } } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8 Gerrit-Change-Number: 46661 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: WIP: New Volteer variant for EVT reworked with Dauntless
by Jes Klinke (Code Review) 02 Nov '20

02 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46437 to review the following change. Change subject: WIP: New Volteer variant for EVT reworked with Dauntless ...................................................................... WIP: New Volteer variant for EVT reworked with Dauntless For development of the firmware to run on the Dauntless TPM, a number of Volteer EVT devices are being reworked to replace the H1 chip with probe wires to connect to an external Dauntless development board. Some modification to the AP firmware is required, not least because the Dauntless chip is connected via I2C bus, instead of SPI. Most of the Dauntless developers will not otherwise have a Chrome OS chroot. Because of the above, I thought it would make sense to have a new variant, for the reworked EVT, which I intend to create with this CL. I have not figured out, though, how to keep MAINBOARD_HAS_SPI_TPM_CR50 selected in Kconfig for all the existing variants, while instead selecting MAINBOARD_HAS_I2C_TPM_CR50 for the new variant only. As far as I can tell, we do not have separate Kconfig files for each variant. If someone can help me how to achieve the above, that would be very helpful. Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Signed-off-by: jbk(a)chromeos.org --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc A src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h A src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc A src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb 11 files changed, 569 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46437/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index edc9c91..bb29b82 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -23,7 +23,7 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE @@ -70,6 +70,14 @@ config DRIVER_TPM_SPI_BUS default 0x1 +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + config MAINBOARD_DIR string default "google/volteer" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 330accc..6fa2671 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -277,7 +277,7 @@ #| | before memory is up | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | + #| I2C1 | Touchscreen, ti50 TPM | #| I2C2 | WLAN, SAR0 | #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | @@ -286,13 +286,14 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, - .early_init = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), }, .i2c[2] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc new file mode 100644 index 0000000..13269db --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c new file mode 100644 index 0000000..fc23983 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), + /* F15 : GSXSRESET# ==> RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + + PAD_CFG_NF(GPP_C18, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C19, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..418f2e0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/mipi_camera.asl> diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc new file mode 100644 index 0000000..37e4c22 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt new file mode 100644 index 0000000..637fd23 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) +K4UBE3D4AA-MGCL 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt new file mode 100644 index 0000000..c532d0d --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +K4U6E3S4AA-MGCL +K4UBE3D4AA-MGCL +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb new file mode 100644 index 0000000..56ddaf7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb @@ -0,0 +1,246 @@ +chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + + device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}}" + device generic 0 on end + end + end # DPTF 0x9A03 + device ref ipu on end # IPU 0x9A19 + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device i2c 50 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms + register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB3_ACTIVE + probe DB_USB USB4_GEN3 + probe DB_USB USB3_NO_A + end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU & HSL follow CC + device generic 1 on + probe DB_USB USB3_PASSIVE + end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Gerrit-Change-Number: 46437 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020