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Change in coreboot[master]: mb/google/volteer/variants: Describe USB ports in devicetree
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46853 ) Change subject: mb/google/volteer/variants: Describe USB ports in devicetree ...................................................................... mb/google/volteer/variants: Describe USB ports in devicetree Add the USB ports to the devicetree for describing them in ACPI, including defining the port relationships and defining the reset GPIO for the bluetooth device. BUG=b:151731851 TEST=tested on volteer, all other boards were checked against the latest available schematic. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/trondo/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 11 files changed, 793 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46853/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5ecfccf..9fe0222 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -92,5 +92,68 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7fd6576..249505f 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -187,5 +187,68 @@ end end end # PMC + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 32204c5..31e1927 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,6 +1,81 @@ chip soc/intel/tigerlake device domain 0 on + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index f8b2921..a786bdd 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -119,5 +119,64 @@ end end device ref hda on end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 5f0f290..87ca0a3 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -71,5 +71,68 @@ device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 64b15b3..c5c0180 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -113,5 +113,68 @@ device generic 0 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79..c8e866a 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -194,5 +194,84 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index d18bb10..0fbc4f1 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -75,5 +75,64 @@ device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c5b4c72..c5ec115 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -255,5 +255,108 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f08..372b12f 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -250,5 +250,108 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index e8be8e3..a34ec51 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -209,5 +209,68 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c Gerrit-Change-Number: 46853 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: mb/google/boldar: Add memory configuration supoprt for boldar
by Aamir Bohra (Code Review) 02 Nov '20

02 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46646 ) Change subject: mb/google/boldar: Add memory configuration supoprt for boldar ...................................................................... mb/google/boldar: Add memory configuration supoprt for boldar Change-Id: Ie085310a8aaac4e5d68b6fdf335f6bfac680a9f7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/boldar/memory.c M src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc 2 files changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46646/1 diff --git a/src/mainboard/google/volteer/variants/boldar/memory.c b/src/mainboard/google/volteer/variants/boldar/memory.c index 1bce421..b7cd170 100644 --- a/src/mainboard/google/volteer/variants/boldar/memory.c +++ b/src/mainboard/google/volteer/variants/boldar/memory.c @@ -4,6 +4,68 @@ #include <baseboard/variants.h> #include <gpio.h> +static const struct lpddr5x_cfg baseboard_lpddr5x_memcfg = { + /* DQ CPU<>DRAM map */ + .dq_map = { + [0] = { + {10, 8, 9, 12, 15, 13, 14, 11,}, /* DDR0_DQ0[7:0] */ + {2, 6, 3, 7, 5, 1, 4, 0, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + {2, 0, 3, 2, 6, 4, 7, 5, }, /* DDR1_DQ0[7:0] */ + {8, 9, 10, 11, 13, 12, 14, 15,}, /* DDR1_DQ1[7:0] */ + }, + [2] = { + {1, 0, 3, 2, 6, 4, 5, 7, }, /* DDR2_DQ0[7:0] */ + {12, 13, 8, 9, 15, 11, 14, 10,}, /* DDR2_DQ1[7:0] */ + }, + [3] = { + {8, 9, 11, 10, 13, 15, 14, 12,}, /* DDR3_DQ0[7:0] */ + {6, 5, 4, 7, 3, 2, 0, 1,}, /* DDR3_DQ1[7:0] */ + }, + [4] = { + {8, 13, 9, 12, 15, 11, 14, 10,}, /* DDR4_DQ0[7:0] */ + {2, 7, 3, 6, 5, 1, 4, 0,}, /* DDR4_DQ1[7:0] */ + }, + [5] = { + {0, 2, 1, 3, 6, 7, 4, 5}, /* DDR5_DQ0[7:0] */ + {13, 12, 15, 14, 10, 9, 8, 11,}, /* DDR5_DQ1[7:0] */ + }, + [6] = { + {8, 13, 9, 12, 15, 10, 14, 11,}, /* DDR6_DQ0[7:0] */ + {3, 6, 2, 7, 4, 1, 0, 5}, /* DDR6_DQ1[7:0] */ + }, + [7] = { + {11, 9, 10, 8, 12, 14, 13, 15,}, /* DDR7_DQ0[7:0] */ + {4, 6, 1, 0, 7, 3, 2, 5, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR5X, + .lpddr5_cfg = &baseboard_lpddr5x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = { diff --git a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc index ed894fe..789b7ad 100644 --- a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) Parts = EMPTY +SPD_SOURCES += lpddr5-spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/46646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie085310a8aaac4e5d68b6fdf335f6bfac680a9f7 Gerrit-Change-Number: 46646 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block
by Subrata Banik (Code Review) 02 Nov '20

02 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45337 ) Change subject: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block ...................................................................... soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block This patch removes all redundant reset code block and make use of common pch/reset code block. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f --- M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/reset.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/elkhartlake/Makefile.inc D src/soc/intel/elkhartlake/reset.c M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/reset.c M src/soc/intel/jasperlake/Makefile.inc D src/soc/intel/jasperlake/reset.c M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/reset.c M src/soc/intel/tigerlake/Makefile.inc D src/soc/intel/tigerlake/reset.c 13 files changed, 2 insertions(+), 228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45337/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..7d829e9 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += i2c.c romstage-y += lpc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -45,7 +44,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/cannonlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..a2f38cc 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOC_INTEL_COMMON_PCH_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..f642598 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c deleted file mode 100644 index 107db5a..0000000 --- a/src/soc/intel/elkhartlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 05f4846..58944a1 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -25,7 +25,6 @@ romstage-y += espi.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -38,7 +37,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/icelake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..dd5b249 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c + ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +39,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/jasperlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index de516c1..e52ef85 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -56,7 +55,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c deleted file mode 100644 index 1076ad2..0000000 --- a/src/soc/intel/skylake/reset.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/me.h> -#include <soc/pm.h> - -static void do_force_global_reset(void) -{ - /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] - */ - pmc_global_reset_enable(true); - - /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ - do_full_reset(); -} - -void do_global_reset(void) -{ - if (!send_global_reset()) { - /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ - do_force_global_reset(); - } -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..28e09ad 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/tigerlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Gerrit-Change-Number: 45337 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

11 77

Change in coreboot[master]: soc/intel/common: Have weak implementation for do_global_reset()
by Subrata Banik (Code Review) 02 Nov '20

02 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47017 ) Change subject: soc/intel/common: Have weak implementation for do_global_reset() ...................................................................... soc/intel/common: Have weak implementation for do_global_reset() Not all IA SoC implement do_global_reset() function locally hence have a weak implementation for do_global_reset() inside common reset.c in order to call global_reset() function from common code. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b --- M src/soc/intel/common/reset.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47017/1 diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index c6c394b..0eb532b 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -8,6 +8,11 @@ #include "reset.h" +void __weak do_global_reset(void) +{ + /* Default empty implementation. */ +} + void global_reset(void) { printk(BIOS_INFO, "%s() called!\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/47017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b Gerrit-Change-Number: 47017 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: azalia: Use `HDA_GCTL_CRST` macro as unset-mask
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46728 ) Change subject: azalia: Use `HDA_GCTL_CRST` macro as unset-mask ...................................................................... azalia: Use `HDA_GCTL_CRST` macro as unset-mask The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent. Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 5 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46728/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index b91151a..972b253 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -46,7 +46,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 6cf1fea..1927adc 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 0e0ccd6..d6c7533 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3b2289ed..bf41490 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index c947092..97e705e2 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -42,7 +42,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Gerrit-Change-Number: 46728 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: azalia: Treat all negative return values as errors
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46727 ) Change subject: azalia: Treat all negative return values as errors ...................................................................... azalia: Treat all negative return values as errors Instead of checking whether the return value equals -1, just check if it is negative. Some Azalia implementations already do it, but most do not. Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 6 files changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46727/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 279f8a1..4ab45bc 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -40,7 +40,7 @@ int count; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -62,11 +62,11 @@ goto no_codec; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -166,7 +166,7 @@ printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -174,7 +174,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -192,12 +192,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4ab..b91151a 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -46,7 +46,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -142,7 +142,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -150,7 +150,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -168,12 +168,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -188,12 +188,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 99582b4..6cf1fea 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 1d1405e..0e0ccd6 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3fa344d..3b2289ed 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 011bde6..c947092 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -42,7 +42,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -138,7 +138,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -146,7 +146,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -164,12 +164,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -185,12 +185,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff Gerrit-Change-Number: 46727 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/lynxpoint: Align with Broadwell
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46726 ) Change subject: sb/intel/lynxpoint: Align with Broadwell ...................................................................... sb/intel/lynxpoint: Align with Broadwell Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46726/1 diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index d142d3e..802c58e 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,9 +7,7 @@ static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index b61115b..24897ca 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -46,7 +46,7 @@ /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8360ce6..7eef5ff 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,11 +289,14 @@ pci_write_config8(dev, 0xa9, 0x46); - RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x232c, ~1, 0); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); RCBA32_OR(0x1100, 0x00000100); RCBA32_OR(0x1100, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + RCBA32(0x3314) = 0x00012fff; RCBA32(0x3318) = 0x0dcf0400; RCBA32(0x3324) = 0x04000000; @@ -320,19 +323,24 @@ RCBA32(0x3a20) = 0x00000404; RCBA32(0x3a24) = 0x01010101; RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); RCBA32_OR(0x2618, 0x08000000); RCBA32_OR(0x2300, 0x00000002); RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; RCBA32(0x3350) = 0x022ddfff; RCBA32(0x3354) = 0x00000001; - RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ - RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ - RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ - RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ - RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ - RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + + /* Power Optimizer */ + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; RCBA32(0x3a80) = 0x05145005; pci_or_config32(dev, 0xac, 1 << 21); @@ -432,7 +440,7 @@ * RCBA + 0x2614[30:28] = 0x0 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ - RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); + RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ struct device *const gma = pcidev_on_root(2, 0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8b791f7..9c68a54 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -144,12 +144,12 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -387,7 +387,7 @@ // BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); if (bios_cntl & 1) { /* @@ -401,7 +401,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Gerrit-Change-Number: 46726 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Simplify PM init sequence
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46725 ) Change subject: sb/intel/lynxpoint/lpc.c: Simplify PM init sequence ...................................................................... sb/intel/lynxpoint/lpc.c: Simplify PM init sequence This sequence used to be an array of reg-and-or triplets, but can be simplified. The resulting sequence is closer to what Broadwell does. Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/46725/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 9018a1c..8360ce6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -291,49 +291,49 @@ RCBA32_AND_OR(0x232c, ~1, 0x00000000); RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); - RCBA32_AND_OR(0x1100, ~0, 0x00000100); - RCBA32_AND_OR(0x1100, ~0, 0x0000003f); + RCBA32_OR(0x1100, 0x00000100); + RCBA32_OR(0x1100, 0x0000003f); RCBA32_AND_OR(0x2320, ~0x60, 0x10); - RCBA32_AND_OR(0x3314, 0, 0x00012fff); - RCBA32_AND_OR(0x3318, 0, 0x0dcf0400); - RCBA32_AND_OR(0x3324, 0, 0x04000000); - RCBA32_AND_OR(0x3368, 0, 0x00041400); - RCBA32_AND_OR(0x3388, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x33ac, 0, 0x00007001); - RCBA32_AND_OR(0x33b0, 0, 0x00181900); - RCBA32_AND_OR(0x33c0, 0, 0x00060A00); - RCBA32_AND_OR(0x33d0, 0, 0x06200840); - RCBA32_AND_OR(0x3a28, 0, 0x01010101); - RCBA32_AND_OR(0x3a2c, 0, 0x04040404); - RCBA32_AND_OR(0x2b1c, 0, 0x03808033); - RCBA32_AND_OR(0x2b34, 0, 0x80000009); - RCBA32_AND_OR(0x3348, 0, 0x022ddfff); - RCBA32_AND_OR(0x334c, 0, 0x00000001); - RCBA32_AND_OR(0x3358, 0, 0x0001c000); - RCBA32_AND_OR(0x3380, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x3384, 0, 0x0001c7e1); - RCBA32_AND_OR(0x338c, 0, 0x0001c7e1); - RCBA32_AND_OR(0x3398, 0, 0x0001c000); - RCBA32_AND_OR(0x33a8, 0, 0x00181900); - RCBA32_AND_OR(0x33dc, 0, 0x00080000); - RCBA32_AND_OR(0x33e0, 0, 0x00000001); - RCBA32_AND_OR(0x3a20, 0, 0x00000404); - RCBA32_AND_OR(0x3a24, 0, 0x01010101); - RCBA32_AND_OR(0x3a30, 0, 0x01010101); - RCBA32_AND_OR(0x0410, ~0, 0x00000003); - RCBA32_AND_OR(0x2618, ~0, 0x08000000); - RCBA32_AND_OR(0x2300, ~0, 0x00000002); - RCBA32_AND_OR(0x2600, ~0, 0x00000008); - RCBA32_AND_OR(0x33b4, 0, 0x00007001); - RCBA32_AND_OR(0x3350, 0, 0x022ddfff); - RCBA32_AND_OR(0x3354, 0, 0x00000001); - RCBA32_AND_OR(0x33d4, ~0, 0x08000000); /* Power Optimizer */ - RCBA32_AND_OR(0x33c8, ~0, 0x00000080); /* Power Optimizer */ - RCBA32_AND_OR(0x2b10, 0, 0x0000883c); /* Power Optimizer */ - RCBA32_AND_OR(0x2b14, 0, 0x1e0a4616); /* Power Optimizer */ - RCBA32_AND_OR(0x2b24, 0, 0x40000005); /* Power Optimizer */ - RCBA32_AND_OR(0x2b20, 0, 0x0005db01); /* Power Optimizer */ - RCBA32_AND_OR(0x3a80, 0, 0x05145005); + RCBA32(0x3314) = 0x00012fff; + RCBA32(0x3318) = 0x0dcf0400; + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3368) = 0x00041400; + RCBA32(0x3388) = 0x3f8ddbff; + RCBA32(0x33ac) = 0x00007001; + RCBA32(0x33b0) = 0x00181900; + RCBA32(0x33c0) = 0x00060A00; + RCBA32(0x33d0) = 0x06200840; + RCBA32(0x3a28) = 0x01010101; + RCBA32(0x3a2c) = 0x04040404; + RCBA32(0x2b1c) = 0x03808033; + RCBA32(0x2b34) = 0x80000009; + RCBA32(0x3348) = 0x022ddfff; + RCBA32(0x334c) = 0x00000001; + RCBA32(0x3358) = 0x0001c000; + RCBA32(0x3380) = 0x3f8ddbff; + RCBA32(0x3384) = 0x0001c7e1; + RCBA32(0x338c) = 0x0001c7e1; + RCBA32(0x3398) = 0x0001c000; + RCBA32(0x33a8) = 0x00181900; + RCBA32(0x33dc) = 0x00080000; + RCBA32(0x33e0) = 0x00000001; + RCBA32(0x3a20) = 0x00000404; + RCBA32(0x3a24) = 0x01010101; + RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); + RCBA32_OR(0x2618, 0x08000000); + RCBA32_OR(0x2300, 0x00000002); + RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; + RCBA32(0x3350) = 0x022ddfff; + RCBA32(0x3354) = 0x00000001; + RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ + RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ + RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ + RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ + RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ + RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + RCBA32(0x3a80) = 0x05145005; pci_or_config32(dev, 0xac, 1 << 21); -- To view, visit https://review.coreboot.org/c/coreboot/+/46725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058 Gerrit-Change-Number: 46725 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46906 ) Change subject: mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field ...................................................................... mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field Define option value 6 for DB_USB where there is a Type-A port but no Type-C port on the daughterboard. BUG=b:151731851 TEST=build volteer boards Change-Id: I489d24316556dedfecd821e502f1461010b1400f Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/46906/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..7c73328 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -6,6 +6,7 @@ option USB4_GEN3 3 option USB3_PASSIVE 4 option USB3_NO_A 5 + option USB3_NO_C 6 end field THERMAL 4 7 end field AUDIO 8 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489d24316556dedfecd821e502f1461010b1400f Gerrit-Change-Number: 46906 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Enable MT8183_DRAM_EMCP for kakadu
by Sunwei Li (Code Review) 02 Nov '20

02 Nov '20

Sunwei Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46871 ) Change subject: Enable MT8183_DRAM_EMCP for kakadu ...................................................................... Enable MT8183_DRAM_EMCP for kakadu BUG=b:171841122 Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 --- M src/mainboard/google/kukui/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46871/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 23a4169..cff94da 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -36,7 +36,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 Gerrit-Change-Number: 46871 Gerrit-PatchSet: 1 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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