coreboot-gerrit October 2020

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Change in coreboot[master]: Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> ...
by Johnny Li (Code Review) 30 Oct '20

30 Oct '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46142 ) Change subject: Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f ...................................................................... Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46142/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..f0cf02d 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -4,6 +4,49 @@ register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" device domain 0 on device pci 05.0 on end # IPU 0x9A19 -- To view, visit https://review.coreboot.org/c/coreboot/+/46142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Gerrit-Change-Number: 46142 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Wim Vervoorn (Code Review) 30 Oct '20

30 Oct '20

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45955 ) Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... Patch Set 33: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 33 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Oct 2020 14:14:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
by Arthur Heymans (Code Review) 30 Oct '20

30 Oct '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35872 ) Change subject: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg ...................................................................... {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg The last argument for acpi_fill_mcfg is the last PCI bus, not the total number of busses. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/northbridge.c M src/soc/amd/stoneyridge/northbridge.c M src/southbridge/amd/pi/hudson/lpc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35872/1 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..756537b 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -167,7 +167,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..2304e73 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -183,7 +183,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 02123a1..cf73a8c 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -336,7 +336,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Gerrit-Change-Number: 35872 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: vc/amd/fsp: Update bl_errorcodes_public.h
by Martin Roth (Code Review) 30 Oct '20

30 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45943 ) Change subject: vc/amd/fsp: Update bl_errorcodes_public.h ...................................................................... vc/amd/fsp: Update bl_errorcodes_public.h Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f --- M src/soc/amd/picasso/psp_verstage/fch.c M src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h 3 files changed, 58 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45943/1 diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 89e7014..c3f8377 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -124,13 +124,13 @@ bar_map[i].set_bar(bar); } - return BL_UAPP_OK; + return (uint32_t)BL_OK; } uint32_t unmap_fch_devices(void) { void *bar; - uint32_t err, rtn = BL_UAPP_OK; + uint32_t err, rtn = (uint32_t)BL_OK; unsigned int i; for (i = 0; i < ARRAY_SIZE(bar_map); ++i) { diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S index 88bbf7e..15340d5 100644 --- a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S +++ b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S @@ -72,7 +72,7 @@ // to main BL using Svc_Exit(). // ShouldNotBeReached: - mov r0, #BL_UAPP_ERR_GENERIC // Returned from Main + mov r0, #BL_ERR_GENERIC // Returned from Main svc #0x0 // SVC_EXIT ENDPROC(_psp_vs_start) @@ -95,7 +95,7 @@ bne ret svcExit: - mov r0, #BL_UAPP_ERR_GENERIC + mov r0, #BL_ERR_GENERIC svc #0x0 // SVC_EXIT ret: diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h index ab24750..c6c052d 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (c) 2019, Advanced Micro Devices, Inc. + * Copyright (c) 2020, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,58 @@ #ifndef BL_ERRORCODES_PUBLIC_H #define BL_ERRORCODES_PUBLIC_H -#define BL_UAPP_OK 0x00 // General - Success -#define BL_UAPP_ERR_GENERIC 0x01 // Generic Error Code +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +typedef enum BL_RETCODE_T +{ + BL_OK = 0x00, // General - Success + BL_ERR_GENERIC = 0x01, // Generic Error Code + BL_ERR_MEMORY = 0x02, // Generic Memory Error + BL_ERR_BUFFER_OVERFLOW = 0x03, // Buffer Overflow + BL_ERR_INVALID_PARAMETER = 0x04, // Invalid Parameter(s) + BL_ERR_DATA_ALIGNMENT = 0x06, // Data Alignment Error + BL_ERR_NULL_PTR = 0x07, // Null Pointer Error + BL_ERR_INVALID_ADDRESS = 0x0A, // Invalid Address + BL_ERR_OUT_OF_RESOURCES = 0x0B, // Out of Resource Error + BL_ERR_DATA_ABORT = 0x0D, // Data Abort exception + BL_ERR_PREFETCH_ABORT = 0x0E, // Prefetch Abort exception + BL_ERR_GET_FW_HEADER = 0x13, // Failure in retrieving firmware + // header + BL_ERR_KEY_SIZE = 0x14, // Key size not supported + BL_ERR_ENTRY_NOT_FOUND = 0x15, // Entry not found at requested + // location + BL_ERR_UNSUPPORTED_PLATFORM = 0x16, // Error when feature is not enabled + // on a given platform. + BL_ERR_FWVALIDATION = 0x18, // Generic FW Validation error + BL_ERR_CCP_RSA = 0x19, // RSA operation fail - bootloader + BL_ERR_CCP_PASSTHR = 0x1A, // CCP Passthrough operation failed + BL_ERR_CCP_AES = 0x1B, // AES operation failed + BL_ERR_SHA = 0x1E, // SHA256/SHA384 operation failed + BL_ERR_ZLIB = 0x1F, // ZLib Decompression operation fail + BL_ERR_DIR_ENTRY_NOT_FOUND = 0x22, // PSP directory entry not found + BL_ERR_SYSHUBMAP_FAILED = 0x3A, // Unable to map a SYSHUB address to + // AXI space + BL_ERR_UAPP_PSP_HEADER_NOT_MATCH = 0x7A, // PSP level directory from OEM user- + // app does not match expected value. + BL_ERR_UAPP_BIOS_HEADER_NOT_MATCH = 0x7B, // BIOS level directory from OEM + // user-app not match expected value. + BL_ERR_UAPP_PSP_DIR_OFFSET_NOT_SET = 0x7C, // PSP Directory offset is not set + // by OEM user-app. + BL_ERR_UAPP_BIOS_DIR_OFFSET_NOT_SET = 0x7D, // BIOS Directory offset is not set + // by OEM user-app. + BL_ERR_POSTCODE_MAX_VALUE = 0x9F, // The maximum allowable error post + // code +} BL_RETCODE; + +/* Bootloader Return Codes, Success only (0xA0 through 0xFF) */ +typedef enum BL_TRACECODE_T +{ + BL_SUCCESS_USERMODE_OEM_APP = 0xF7, // Updated only PSPFW Status when OEM + // PSP BL user app returns success. + BL_SUCCESS_PSP_BIOS_DIRECTORY_UPDATE = 0xF8, // PSP and BIOS directories are loaded + // into SRAM from the offset provided + // by OEM user app. + + BL_SUCCESS_LAST_CODE = 0xFF, // Bootloader sequence finished +} BL_TRACECODE; #endif // BL_ERRORCODES_PUBLIC_H -- To view, visit https://review.coreboot.org/c/coreboot/+/45943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Gerrit-Change-Number: 45943 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/amd/picasso: Fix the PSP SMI trigger info
by Marshall Dawson (Code Review) 30 Oct '20

30 Oct '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46854 ) Change subject: soc/amd/picasso: Fix the PSP SMI trigger info ...................................................................... soc/amd/picasso: Fix the PSP SMI trigger info Assign one of the reserved triggers in SmiTrig0 to the PSP and correct the values passed during the MboxBiosCmdSmmInfo call. The #define of SMITYPE_PSP 33 is still correct and is intentionally unmodified. This patch should be innocuous as the system doesn't currently support SMI-based features of the PSP. The call only exists so the PSP will honor a mailbox command during S3 suspend. BUG=b:171815390 TEST=Run SST on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55 --- M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/psp.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46854/1 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5..0529ef6 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -160,6 +160,7 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index e40d395..702b0d9 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -27,11 +27,11 @@ if (!trig) return; - trig->address = (uintptr_t)acpimmio_smi + SMI_REG_CONTROL2; + trig->address = (uintptr_t)acpimmio_smi + SMI_REG_SMITRIG0; trig->address_type = SMM_TRIGGER_MEM; trig->value_width = SMM_TRIGGER_DWORD; - trig->value_and_mask = 0xfdffffff; - trig->value_or_mask = 0x02000000; + trig->value_and_mask = ~SMITRIG0_PSP; + trig->value_or_mask = SMITRIG0_PSP; } void soc_fill_smm_reg_info(struct smm_register_info *reg) -- To view, visit https://review.coreboot.org/c/coreboot/+/46854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55 Gerrit-Change-Number: 46854 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [WIP]amdfwtool: Take a config file instead of command line parameters
by Bao Zheng (Code Review) 30 Oct '20

30 Oct '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42859 to review the following change. Change subject: [WIP]amdfwtool: Take a config file instead of command line parameters ...................................................................... [WIP]amdfwtool: Take a config file instead of command line parameters Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/fw.cfg M util/amdfwtool/Makefile A util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c A util/amdfwtool/amdfwtool.h A util/amdfwtool/amdfwtool.sh A util/amdfwtool/data_parse.c A util/amdfwtool/sample.txt 10 files changed, 899 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42859/1 diff --git a/Makefile.inc b/Makefile.inc index bbb6685..0e10136 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -81,7 +81,7 @@ subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) @@ -566,9 +566,9 @@ cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool -$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +#$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c +# @printf " HOSTCC $(subst $(obj)/,,$(@))\n" +# $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -666,7 +666,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(objutil)/amdfwtool/amdfwtool $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo ########################################################################### # Common recipes for all stages @@ -1094,7 +1094,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..20fb5c2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -378,14 +378,6 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ --apob-nv-size $(shell printf "0x%x" \ @@ -398,38 +390,18 @@ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ + --config $(FIRMWARE_LOCATE)/fw.cfg \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +# --config /home/baozheng/x86/coreboot-gerrit/src/soc/amd/picasso/fw.cfg \ + + $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg new file mode 100644 index 0000000..f5b9d13 --- /dev/null +++ b/src/soc/amd/picasso/fw.cfg @@ -0,0 +1,46 @@ +# sample PSP fw config file +# Move to amd_blob +# type file +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +#PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +#PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +#PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +#PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +#PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +#PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +#PSP_SOFTFUSE 0x0000000010000001 +#PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e9fd91b..9f7a01b 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -2,15 +2,47 @@ # # All rights reserved. # -# SPDX-License-Identifier: BSD-3-Clause - +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# #***************************************************************************** HOSTCC ?= cc -amdfwtool_exe : amdfwtool.c - $(HOSTCC) amdfwtool.c -o amdfwtool +SRC = amdfwtool.c data_parse.c +OBJ = $(SRC:%.c=%.o) +TARGET = amdfwtool +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare -amdfwtool : amdfwtool_exe + +$(TARGET): $(OBJ) + $(CC) $(OBJ) $(LDFLAGS) -o $@ + +%.o: %.c $(HEADER) + $(CC) $(CFLAGS) -c -o $@ $< + +amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe clean: - @rm -f amdfwtool.o amdfwtool amdfwtool.exe + rm -f $(TARGET) $(OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc new file mode 100644 index 0000000..36ff207d --- /dev/null +++ b/util/amdfwtool/Makefile.inc @@ -0,0 +1,52 @@ +#***************************************************************************** +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +#HOSTCC ?= cc + +amdfwtoolobj = amdfwtool.o data_parse.o + +#TARGET = $(objutil)/amdfwtool/amdfwtool +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare + + +#$(TARGET): $(OBJ) +# $(CC) $(OBJ) $(LDFLAGS) -o $@ + +$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) + printf " AMDFWTOOL\n" + $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +#amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe + +#clean: +# rm -f $(TARGET) $(OBJ) +$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) + printf " AMDFWTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110..eb0cae8 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -56,6 +56,9 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> +#include <libgen.h> + +#include "amdfwtool.h" #ifndef CONFIG_ROM_SIZE #define CONFIG_ROM_SIZE 0x400000 @@ -98,13 +101,6 @@ */ #define PSP_COMBO 0 -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -216,92 +212,11 @@ printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); printf("-h | --help show this help\n"); + printf("-C | --config config file\n"); } -typedef enum _amd_bios_type { - AMD_BIOS_APCB = 0x60, - AMD_BIOS_APOB = 0x61, - AMD_BIOS_BIN = 0x62, - AMD_BIOS_APOB_NV = 0x63, - AMD_BIOS_PMUI = 0x64, - AMD_BIOS_PMUD = 0x65, - AMD_BIOS_UCODE = 0x66, - AMD_BIOS_APCB_BK = 0x68, - AMD_BIOS_MP2_CFG = 0x6a, - AMD_BIOS_PSP_SHARED_MEM = 0x6b, - AMD_BIOS_L2_PTR = 0x70, - AMD_BIOS_INVALID, -} amd_bios_type; -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 -#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) -typedef struct _amd_bios_entry { - amd_bios_type type; - int region_type; - int reset; - int copy; - int ro; - int zlib; - int inst; - int subpr; - uint64_t src; - uint64_t dest; - size_t size; - char *filename; - int level; -} amd_bios_entry; - -typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, - AMD_DEBUG_UNLOCK = 0x13, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_FW_PSP_WHITELIST = 0x3a, - AMD_FW_L2_PTR = 0x40, - AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_IMC, - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, -} amd_fw_type; - -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 -#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) -typedef struct _amd_fw_entry { - amd_fw_type type; - uint8_t subprog; - char *filename; - int level; - uint64_t other; -} amd_fw_entry; - -static amd_fw_entry amd_psp_fw_table[] = { +/* static */ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, @@ -343,14 +258,14 @@ { .type = AMD_FW_INVALID }, }; -static amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -static amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -658,6 +573,28 @@ } } +static void dump_psp_firmwares(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + +static void dump_bdt_firmwares(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -1039,7 +976,7 @@ fill_dir_header(biosdir, count, cookie); } // Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1087,6 +1024,7 @@ {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, /* other */ + {"config", required_argument, 0, 'C' }, {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, @@ -1097,7 +1035,7 @@ {NULL, 0, 0, 0 } }; -static void register_fw_fuse(char *str) +void register_fw_fuse(char *str) { int i; @@ -1145,6 +1083,40 @@ } } +static int register_fw_fuses(int fd, char *dir) +{ + struct stat fd_stat; + unsigned char *config_file; + +// fd = open(, O_RDONLY); +// if (fd < 0) { +// printf("Error opening file: %s: %s\n", +// src_file, strerror(errno)); +// return -1; +// } + + if (fstat(fd, &fd_stat)) { + printf("fstat error 1: %s\n", strerror(errno)); + close(fd); + return -2; + } + + //if (fd_stat.st_size > room) { + // printf("Error: %s will not fit. Exiting.\n", src_file); + // close(fd); + // return -3; + //} + + config_file = malloc (fd_stat.st_size+1); + read(fd, config_file, (size_t)fd_stat.st_size); + + config_file[fd_stat.st_size+1] = '\0'; + + process_config(config_file, dir); + printf("fuse written=[%s,%d] %x\n", __func__, __LINE__, amd_psp_fw_table[16].other); +} + + static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) { int i; @@ -1188,8 +1160,8 @@ psp_directory_table *pspdir; int comboable = 0; int fuse_defined = 0; - int targetfd; - char *output = NULL; + int targetfd, configfd; + char *output = NULL, *config = NULL; context ctx = { .rom_size = CONFIG_ROM_SIZE, }; @@ -1427,6 +1399,9 @@ sub = instance = 0; break; + case 'C': + config = optarg; + break; case 'h': usage(); return 0; @@ -1434,9 +1409,29 @@ break; } } + #if 1 + if (!config) { + printf("Error: config file is not specified.\n\n"); + retval = 1; + } - if (!fuse_defined) - register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); + configfd = open(config, O_RDONLY); + + if (configfd >=0) { + printf("%s opened\n", config); + register_fw_fuses(configfd, dirname(config)); + } else { + printf("open failed\n"); + } + + + dump_psp_firmwares(amd_psp_fw_table); + dump_bdt_firmwares(amd_bios_table); + printf("close config file\n"); + close (configfd); +#endif + //if (!fuse_defined) + // register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); if (!output) { printf("Error: Output value is not specified.\n\n"); @@ -1571,6 +1566,7 @@ amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); } + /* TODO:Free the filename. */ targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { write(targetfd, amd_romsig, ctx.current - romsig_offset); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h new file mode 100644 index 0000000..fda41b2 --- /dev/null +++ b/util/amdfwtool/amdfwtool.h @@ -0,0 +1,98 @@ +#ifndef _AMD_FW_TOOL_H_ +#define _AMD_FW_TOOL_H_ +#if defined(__GLIBC__) +typedef unsigned long long int uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#endif + + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_IMC, + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, +} amd_fw_type; + +typedef enum _amd_bios_type { + AMD_BIOS_APCB = 0x60, + AMD_BIOS_APOB = 0x61, + AMD_BIOS_BIN = 0x62, + AMD_BIOS_APOB_NV = 0x63, + AMD_BIOS_PMUI = 0x64, + AMD_BIOS_PMUD = 0x65, + AMD_BIOS_UCODE = 0x66, + AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_L2_PTR = 0x70, + AMD_BIOS_INVALID, +} amd_bios_type; + + +#define BDT_LVL1 0x1 +#define BDT_LVL2 0x2 +#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +typedef struct _amd_bios_entry { + amd_bios_type type; + char *filename; + int subpr; + int region_type; + int reset; + int copy; + int ro; + int zlib; + int inst; + uint64_t src; + uint64_t dest; + size_t size; + int level; +} amd_bios_entry; + + +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +void register_fw_fuse(char *str); + +#endif diff --git a/util/amdfwtool/amdfwtool.sh b/util/amdfwtool/amdfwtool.sh new file mode 100644 index 0000000..50006f8 --- /dev/null +++ b/util/amdfwtool/amdfwtool.sh @@ -0,0 +1,60 @@ +#!/bin/sh + +# --pubkey ../../3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin \ +# --bootloader /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspBootLoader_prod_RV.sbin \ +# --rtmpubkey /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RtmPubSignedRV.key \ +# --secureos /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//psp_os_combined_prod_RV.sbin \ +# --securedebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RavenSecureDebug_PublicKey.bin \ + +# --trustlets /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//dr_ftpm_prod_RV.csbin \ +# --subprogram 2 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwarePCO.csbin \ +# --subprogram 2 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2PCO.csbin \ +# --subprogram 1 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwareRV2.csbin \ +# --subprogram 1 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2RV2.csbin \ + +# --soft-fuse 0x0000000010000001 \ +# --subprogram 0 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Imem.csbin \ +# --subprogram 1 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Imem.csbin \ +# --subprogram 1 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin \ +# --subprogram 0 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Dmem.csbin \ +# --subprogram 1 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin \ +# --subprogram 1 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin \ +# --mp2-config /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2FWConfig.sbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader0_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader1_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader2_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader3_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader4_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader5_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader6_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader7_prod_RV.csbin \ +# --subprog 1 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_RV2_FP5_AM4.sbin \ +# --subprog 2 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_PCO_FP5_AM4.sbin \ +# --subprog 1 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWRV2.sbin \ +# --subprog 2 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWPCO.sbin \ +# --drv-entry-pts /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//drv_sys_prod_RV.sbin \ +# --ikek /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspIkekRV.bin \ +# --secdebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//secure_unlock_prod_RV.sbin \ + +./amdfwtool \ + --instance 0 --apcb ../../3rdparty/blobs/mainboard/amd/mandolin/apcb.bin \ + \ + \ + \ + \ + --apob-base 0x9f00000 \ + \ + --apob-nv-size 0x1000 \ + --bios-bin amd_biospsp.img \ + --bios-bin-dest 8078000 \ + --bios-uncomp-size 0x8000 \ + \ + \ + --combo-capable \ + --token-unlock \ + --flashsize 0x00800000 \ + --location 0xff820000 \ + --config sample.txt \ + --output amdfw.rom diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c new file mode 100644 index 0000000..03f1a7f --- /dev/null +++ b/util/amdfwtool/data_parse.c @@ -0,0 +1,457 @@ +#include <stdio.h> +#include <regex.h> +#include <string.h> + +#include "amdfwtool.h" + +/* TODO: a empty line does not matched. */ +static const char blank_or_comment_regex[] = + /* a blank line */ + "(^[[:space:]]*$)" "|" /* or ... */ + /* a line consisting of: optional whitespace followed by */ + "(^[[:space:]]*" + /* a '#' character and optionally, additional characters */ + "#.*$)"; +static regex_t blank_or_comment_expr; + +static const char entries_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_line_expr; + +static const char entries_subprog_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_subprog_line_expr; + +void compile_reg_expr(int cflags, const char *expr, regex_t *reg) +{ + static const size_t ERROR_BUF_SIZE = 256; + char error_msg[ERROR_BUF_SIZE]; + int result; + + if ((result = regcomp(reg, expr, cflags)) != 0) { + regerror(result, reg, error_msg, ERROR_BUF_SIZE); + printf("%s\n", error_msg); + exit(1); + } +} + +extern amd_fw_entry amd_psp_fw_table[]; +extern amd_bios_entry amd_bios_table[]; +void find_register_fw_filename(char *fw_name, char *filename, uint8_t subprog) +{ + unsigned int fw_type, fw_invalid, fw, entry_size; + void *tableptr; + uint8_t /* subprog = 0, */instance = 0; + + printf("fw_name=%s, fn=%s, subprog=%d\n", fw_name, filename, subprog); + if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_RTM_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 1; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 2; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { + fw_type = AMD_ABL0; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { + fw_type = AMD_ABL1; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { + fw_type = AMD_ABL2; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { + fw_type = AMD_ABL3; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { + fw_type = AMD_ABL4; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { + fw_type = AMD_ABL5; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { + fw_type = AMD_ABL6; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { + fw_type = AMD_ABL7; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPSCUREOS_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_OS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + fw_type = AMD_FW_PSP_TRUSTLETS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { + fw_type = AMD_DEBUG_UNLOCK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { + fw_type = AMD_S0I3_DRIVER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_WHITELIST_FILE") == 0) { + fw_type = AMD_FW_PSP_WHITELIST; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else { + fw_type = AMD_FW_INVALID; +// return ; + /* TODO: Add more */ + } + +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + printf("Search and fill the filename\n"); + /* Search and fill the filename */ + while (*(unsigned int *)tableptr != fw_invalid) { + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog) { + printf("type=%d,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + ((amd_fw_entry *)tableptr)->filename = filename; + break; + } else { +// printf("not found type=%d\n", *(unsigned int *)tableptr); + } + tableptr += entry_size; + } + printf("\n"); + printf("Search and fill the filename 2\n\n"); + #if 1 + if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + instance = 0; + } else { + fw_type = AMD_BIOS_INVALID; + } + tableptr = (void *)amd_bios_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + //printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog && + ((amd_bios_entry *)tableptr)->inst == instance) { + ((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + //((amd_bios_entry *)tableptr)->inst = instance; + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + break; + } + tableptr += sizeof (amd_bios_entry); + } + } + + printf("Search and fill the filename 3\n\n"); + if (strcmp(fw_name, "PSP_SOFTFUSE") == 0) { + fw_type = AMD_PSP_FUSE_CHAIN; + } else { + fw_type = AMD_BIOS_INVALID; + } + /* char *filename */ + printf("Search and fill the filename 3.1\n\n"); + tableptr = (void *)amd_psp_fw_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type) { + //((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + ((amd_fw_entry *)tableptr)->other = strtoull(filename, NULL, 16); + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fuse=%llx\n", ((amd_fw_entry *)tableptr)->other); + break; + } + tableptr += sizeof (amd_fw_entry); + } + } + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + + printf("Search and fill the filename 3.9\n\n"); + +#endif + +} + +unsigned int read_line(char **config, char **oneline) +{ + char *ptr = *config; + char *line_start; + int num; + +// printf("read_line %c\n", **config); + if (*ptr == NULL) return -1; + + line_start = ptr; + while (*ptr != '\n' && *ptr != NULL) { + ptr ++; + } + + num = ptr - line_start; + *oneline = malloc(num+1); + + memcpy (*oneline, line_start, num); + *(*oneline + num) = '\0'; + ptr ++; /* skip enter. */ + //*oneline = ptr; +// printf("readline = %s\n", *oneline); + *config = ptr; + return 0; +} +#define N_MATCHES 4 +void process_config(char *config, char *dir) +{ +// char line [ /* LINE_BUF_SIZE */128]; + char *oneline, *current, *path_filename; + regmatch_t match[N_MATCHES]; + uint8_t subprog = 0; + + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, blank_or_comment_regex, &blank_or_comment_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_line_regex, &entries_line_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_subprog_line_regex, &entries_subprog_line_expr); + + /* TODO: temp */ + //strcpy (line, "PSPBTLDR_FILE PspBootLoader_prod_RV.sbin\n\0"); +// strcpy (line, "AMD_PUBKEY_FILE AmdPubKeyRV.bin\n\0"); + + /* Get a line */ + current = config; + while (read_line(&current, &oneline) != -1) { + /* get line */ + /* blank comment */ +// printf("%d\n", __LINE__); + if (!regexec(&blank_or_comment_expr, oneline, 0, NULL, 0)){ + printf("skip comment and blank\n"); + continue; + } + +// printf("%d\n", __LINE__); + if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) { + printf("matched entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + } else if (regexec(&entries_subprog_line_expr, oneline, 4, match, 0) == 0) { + printf("matched subprog entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo, match[3].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so, match[3].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + oneline[match[3].rm_eo] = '\0'; + subprog = oneline[match[3].rm_so] - '0'; + } else { + printf("no match\n"); + continue; + } +// printf("%d\n", __LINE__); +// printf("%d\n", __LINE__); + +// printf("%s, %s\n", &(oneline[match[1].rm_so]), &(oneline[match[2].rm_so])); + path_filename = malloc(256); + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + find_register_fw_filename(&(oneline[match[1].rm_so]), path_filename, subprog); + + } + + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + +} diff --git a/util/amdfwtool/sample.txt b/util/amdfwtool/sample.txt new file mode 100644 index 0000000..8c3edcc --- /dev/null +++ b/util/amdfwtool/sample.txt @@ -0,0 +1,45 @@ +# sample +# PSP +# type file subprog +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +PSP_SOFTFUSE 0x0000000010000001 +PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/42859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Gerrit-Change-Number: 42859 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

6 158

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Opal Voravootivat (Code Review) 30 Oct '20

30 Oct '20

Opal Voravootivat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… PS15, Line 54: 10-15W PL1 Look like 3-15W below in the code https://review.coreboot.org/c/coreboot/+/46676/15/src/mainboard/google/volt… PS15, Line 55: PL2 is fixed at 64W Look like 15-51W below in the code -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 15 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 30 Oct 2020 11:53:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cbfs: Hook up to new CBFS implmentation
by Julius Werner (Code Review) 30 Oct '20

30 Oct '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38422 to review the following change. Change subject: cbfs: Hook up to new CBFS implmentation ...................................................................... cbfs: Hook up to new CBFS implmentation This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/Makefile.inc A src/include/cbfs_glue.h M src/lib/cbfs.c 3 files changed, 63 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38422/1 diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9..b2225cb 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,6 +30,13 @@ smm-y += cbfs.c postcar-y += cbfs.c +bootblock-y += bsd/cbfs_private.c +verstage-y += bsd/cbfs_private.c +romstage-y += bsd/cbfs_private.c +postcar-y += bsd/cbfs_private.c +ramstage-y += bsd/cbfs_private.c +smm-y += bsd/cbfs_private.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h new file mode 100644 index 0000000..10f4187 --- /dev/null +++ b/src/include/cbfs_glue.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include <commonlib/region.h> +#include <console/console.h> + +#define ENABLE_HASHING 0 + +#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#if CONFIG(DEBUG_CBFS) +#define DEBUG(...) printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__) +#else +#define DEBUG(...) +#endif + +typedef const struct region_device *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + return rdev_readat(dev, buffer, offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return region_device_sz(dev); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c712f76..d6fb99c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <boot_device.h> #include <cbfs.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/bsd/compression.h> #include <endian.h> #include <lib.h> @@ -29,14 +30,6 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { struct region_device rdev; @@ -44,28 +37,35 @@ if (cbfs_boot_region_device(&rdev)) return -1; - int ret = cbfs_locate(fh, &rdev, name, type); + union cbfs_mdata mdata; + size_t data_offset; + cb_err_t err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + return -1; + err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + } + if (err) + return -1; - /* - * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the - * active RW region, the RO (COREBOOT) region will be used to locate the file. - * - * This functionality makes it possible to avoid duplicate files in the RO - * and RW partitions while maintaining updateability. - * - * Files can be added to the RO_REGION_ONLY config option to use this feature. - */ - printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); + size_t msize = be32toh(mdata.h.offset); + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) + return -1; + if (type) { + if (!*type) + *type = be32toh(mdata.h.type); + else if (*type != be32toh(mdata.h.type)) + return -1; } - if (!ret) - if (vboot_measure_cbfs_hook(fh, name)) - return -1; + if (vboot_measure_cbfs_hook(fh, name)) + return -1; - return ret; + return 0; } void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/38422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d112d1239475920de2d872dac179c245275038d Gerrit-Change-Number: 38422 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: commonlib/bsd: Add new CBFS core implementation
by Julius Werner (Code Review) 30 Oct '20

30 Oct '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38421 to review the following change. Change subject: commonlib/bsd: Add new CBFS core implementation ...................................................................... commonlib/bsd: Add new CBFS core implementation This patch adds a new CBFS implementation that is intended to replace the existing commonlib/cbfs.c. The new implementation is designed to meet a bunch of current and future goals that in aggregate make it easier to start from scratch than to adapt the exisiting implementation: 1. Be BSD-licensed so it can evetually be shared with libpayload. 2. Allow generating/verifying a master hash for future CBFS per-file verification (see [1][2]). 3. Be very careful about reading (not mmaping) all data only once, to be suitable for eventual TOCTOU-safe verification. 4. Make it possibly to efficiently implement all current and future firmware use cases (both with and without verification). The main primitive is the cbfs_walk() function which will traverse a CBFS and call a callback for every file. cbfs_lookup() uses this to implement the most common use case of finding a file so that it can be read. A host application using this code (e.g. coreboot, libpayload, cbfstool) will need to provide a <cbfs_glue.h> header to provide the glue to access the respective CBFS storage backend implementation. This patch merely adds the code, the next patch will integrate it into coreboot. [1]: https://www.youtube.com/watch?v=Hs_EhewBgtM [2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_i… Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M MAINTAINERS A src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h A src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h 5 files changed, 284 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38421/1 diff --git a/MAINTAINERS b/MAINTAINERS index 77769c0..b5cad10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -489,8 +489,13 @@ F: src/device/oprom/ CBFS -F: src/include/cbfs.h -F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +M: Julius Werner <jwerner(a)chromium.org> +F: src/include/cbfs* +F: src/commonlib/bsd/include/commonlib/bsd/cbfs* +F: src/commonlib/bsd/cbfs* +F: src/lib/cbfs.c + +CBFSTOOL F: util/cbfstool/ CBMEM diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c new file mode 100644 index 0000000..4dd14cb --- /dev/null +++ b/src/commonlib/bsd/cbfs_private.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include <commonlib/bsd/cbfs_private.h> +#include <assert.h> + +static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer) +{ + DEBUG("Looking for next file @%#zx...\n", *offset); + *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT); + while (*offset + sizeof(*buffer) < cbfs_dev_size(dev)) { + if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer)) + return CB_CBFS_IO; + + if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0) + return CB_SUCCESS; + + *offset += CBFS_ALIGNMENT; + } + + DEBUG("End of CBFS reached\n"); + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + union cbfs_mdata *mdata, bool do_hash, + void *arg), + void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags flags) +{ + bool do_hash = ENABLE_HASHING && master_hash; + struct vb2_digest_context dc; + vb2_error_t vbrv; + + assert(ENABLE_HASHING || (!master_hash && !(flags & CBFS_WALK_WRITEBACK_HASH))); + if (do_hash && (vbrv = vb2_digest_init(&dc, master_hash->algo))) { + ERROR("Master hash algo %d digest init error: %#x\n", master_hash->algo, vbrv); + return CB_ERR_ARG; + } + + size_t offset = 0; + cb_err_t ret_header; + cb_err_t ret_walker = CB_CBFS_NOT_FOUND; + union cbfs_mdata mdata; + while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) { + const uint32_t attr_offset = be32toh(mdata.h.attributes_offset); + const uint32_t data_offset = be32toh(mdata.h.offset); + const uint32_t data_length = be32toh(mdata.h.len); + const uint32_t type = be32toh(mdata.h.type); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + + DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", + offset, be32toh(mdata.h.type), attr_offset, data_offset, data_length); + if (data_offset > sizeof(mdata)) { + ERROR("File metadata @%#zx too large\n", offset); + goto next_file; + } + if (offset + data_offset >= cbfs_dev_size(dev)) { + ERROR("Device ends in middle of metadata @%#zx\n", offset); + goto next_file; + } + + if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY)) + goto next_file; + + /* When hashing we need to read everything. Otherwise skip the attributes. + attr_offset may be 0, which means there are no attributes. */ + ssize_t todo; + if (do_hash || attr_offset == 0) + todo = data_offset - sizeof(mdata.h); + else + todo = attr_offset - sizeof(mdata.h); + if (todo <= 0 || data_offset < attr_offset) { + ERROR("Corrupt file header @%#zx\n", offset); + goto next_file; + } + + /* Read the rest of the metadata (filename, and possibly attributes). */ + if (cbfs_dev_read(dev, (uint8_t *)&mdata + sizeof(mdata.h), + offset + sizeof(mdata.h), todo) != todo) + return CB_CBFS_IO; + DEBUG("File name: '%s'\n", mdata.filename); + + if (do_hash && !empty && vb2_digest_extend(&dc, (void *)&mdata, data_offset)) + return CB_ERR; + + if (ret_walker == CB_CBFS_NOT_FOUND) + ret_walker = walker(dev, offset, &mdata, do_hash, arg); + + /* Return IO errors immediately. For others, finish the hash first if needed. */ + if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash)) + return ret_walker; + +next_file: + offset += data_offset + data_length; + } + + if (ret_header != CB_CBFS_NOT_FOUND) + return ret_header; + + if (do_hash) { + uint8_t real_hash[VB2_MAX_DIGEST_SIZE]; + size_t hash_size = vb2_digest_size(master_hash->algo); + if (vb2_digest_finalize(&dc, real_hash, sizeof(real_hash))) + return CB_ERR; + if (flags & CBFS_WALK_WRITEBACK_HASH) + memcpy(master_hash->bytes.raw, real_hash, hash_size); + else if (memcmp(master_hash->bytes.raw, real_hash, hash_size) != 0) + return CB_CBFS_HASH; + } + + return ret_walker; +} + +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src, + cbfs_dev_t dev, size_t offset, bool do_hash) +{ + const size_t attr_offset = be32toh(src->h.attributes_offset); + + /* In the hashing case or when there are no attributes, we already have everything. */ + if (do_hash || attr_offset == 0) { + memcpy(dst, src, be32toh(src->h.offset)); + return CB_SUCCESS; + } + + /* Otherwise we'll need to copy what we have and read in the rest. */ + const size_t todo = be32toh(src->h.offset) - attr_offset; + memcpy(dst, src, attr_offset); + void *dst_attrs = (uint8_t *)dst + attr_offset; + if (cbfs_dev_read(dev, dst_attrs, offset + attr_offset, todo) != todo) + return CB_CBFS_IO; + return CB_SUCCESS; +} + +uint32_t cbfs_filename_size(struct cbfs_file *h) +{ + uint32_t end_offset = be32toh(h->attributes_offset); + if (end_offset == 0) + end_offset = be32toh(h->offset); + return end_offset - sizeof(struct cbfs_file); +} + +struct cbfs_lookup_args { + union cbfs_mdata *mdata_out; + const char *name; + size_t namesize; + size_t *data_offset_out; +}; + +static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, union cbfs_mdata *mdata, + bool do_hash, void *arg) +{ + struct cbfs_lookup_args *args = arg; + if (args->namesize > cbfs_filename_size(&mdata->h) || + memcmp(args->name, mdata->filename, args->namesize) != 0) + return CB_CBFS_NOT_FOUND; + + LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); + if (cbfs_copy_fill_metadata(args->mdata_out, mdata, dev, offset, do_hash) != CB_SUCCESS) + return CB_CBFS_IO; + + *args->data_offset_out = offset + be32toh(mdata->h.offset); + return CB_SUCCESS; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *master_hash) +{ + struct cbfs_lookup_args args = { + .mdata_out = mdata_out, + .name = name, + .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */ + .data_offset_out = data_offset_out, + }; + return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab419a7..ab422e1 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -34,6 +34,11 @@ CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave device response, try again? */ CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ + + /* CBFS errors */ + CB_CBFS_IO = -400, /**< Underlying I/O error */ + CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ + CB_CBFS_HASH = -402, /**< Master hash validation failed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h new file mode 100644 index 0000000..b4fc1c7 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_ +#define _COMMONLIB_BSD_CBFS_PRIVATE_H_ + +#include <commonlib/bsd/cb_err.h> +#include <commonlib/bsd/cbfs_serialized.h> +#include <endian.h> +#include <stdbool.h> +#include <stdint.h> +#include <vb2_sha.h> + +/* + * This file needs to be provided by the host application using this CBFS library. It must + * define the following type, macros and functions: + * + * cbfs_dev_t An opaque type representing a CBFS storage backend. + * ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise. + * ERROR(...) printf-style macro to print errors. + * LOG(...) printf-style macro to print normal-operation log messages. + * DEBUG(...) printf-style macro to print detailed debug output. + * + * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size); + * Read |size| bytes starting at |offset| from |dev| into |buffer|. + * Returns amount of bytes read on success and < 0 on error. + * + * size_t cbfs_dev_size(cbfs_dev_t dev); + * Return the total size in bytes of the CBFS storage (actual CBFS area). + */ +#include <cbfs_glue.h> + +/* Helper structure to allocate space for a blob of metadata on the stack. */ +#define CBFS_METADATA_MAX_SIZE 256 +union cbfs_mdata { + struct { + struct cbfs_file h; + char filename[]; + }; + uint8_t raw[CBFS_METADATA_MAX_SIZE]; +}; + +/* Flags that modify behavior of cbfs_walk(). */ +enum cbfs_walk_flags { + /* Write the calculated hash back out to |master_hash->hash|, rather than comparing it. + |master_hash->algo| must still have been initialized by the caller. */ + CBFS_WALK_WRITEBACK_HASH = (1 << 0), + /* Call |walker| for empty file entries. Otherwise, empty entries will be skipped. + Either way, empty entries are never included in master_hash calculation. */ + CBFS_WALK_INCLUDE_EMPTY = (1 << 1), +}; + +/* + * Traverse a CBFS and call a |walker| callback function for every file. Can additionally + * calculate a master hash over the metadata of all files in the CBFS. If |master_hash| is NULL, + * hashing is disabled. + * + * |arg| and |dev| will be passed through to |walker| unmodified. |do_hash| is true iff + * hashing is enabled (master_hash != NULL). |offset| is the total offset in |dev| at which the + * current file metadata starts. |mdata| is a temporary buffer (only valid for the duration of + * this call to |walker|) containing already read metadata from the current file: if |do_hash| + * is true, all metadata in |mdata| (header, filename and attributes) will be valid, otherwise + * only the header and the filename (not attributes) will be valid. |walker| should call into + * cbfs_copy_fill_medadata() to copy the metadata of a file to a persistent buffer and + * automatically load remaining attributes from |dev| as needed based on |do_hash|. + * + * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further + * files. Any other return code will be used as the final return code for cbfs_walk(). It will + * return immediately unless it needs to calculate a hash in which case it will still traverse + * the remaining CBFS (but not call |walker| anymore). + */ +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + union cbfs_mdata *mdata, bool do_hash, + void *arg), + void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags); + + +/* + * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata + * of a file into a permanent buffer. Will copy the metadata from |src| into |dst| and load + * additional attributes from |dev| to copy behind that if |do_hash| is false. (|offset| is the + * offset of the whole file metadata, not just of the attributes.) + */ +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src, + cbfs_dev_t dev, size_t offset, bool do_hash); + +/* Helper function to determine the size of the filename part in a CBFS header. The actual + filename is NUL-terminated and due to alignment likely a bit shorter than this. */ +uint32_t cbfs_filename_size(struct cbfs_file *h); + +/* Find a file named |name| in the CBFS on |dev| and copy its metadata (including attributes) + * into |mdata_out|. Pass out offset to the file data and verify |master_hash| (if provided). */ +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *master_hash); + +#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index d2fc626..556c8e4 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -4,6 +4,7 @@ #define _CBFS_SERIALIZED_H_ #include <stdint.h> +#include <vb2_sha.h> /** These are standard values for the known compression algorithms that coreboot knows about for stages and @@ -123,12 +124,11 @@ uint32_t decompressed_size; } __packed; +/* Actual size in CBFS may be larger/smaller than struct size! */ struct cbfs_file_attr_hash { uint32_t tag; uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; + struct vb2_hash hash; } __packed; struct cbfs_file_attr_position { -- To view, visit https://review.coreboot.org/c/coreboot/+/38421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Gerrit-Change-Number: 38421 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

7 66

Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Nico Huber (Code Review) 30 Oct '20

30 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45955 ) Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... Patch Set 33: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 33 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Oct 2020 09:49:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020