coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Tim Wawrzynczak (Code Review) 29 Oct '20

29 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 14: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… PS14, Line 39: [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), : [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), : [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000) nit: this is easier to read if each column lines up https://review.coreboot.org/c/coreboot/+/46676/14/src/mainboard/google/volt… PS14, Line 68: nit: extra blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 14 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 20:33:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/haswell: Align more stuff with Broadwell
by Angel Pons (Code Review) 29 Oct '20

29 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46981 ) Change subject: nb/intel/haswell: Align more stuff with Broadwell ...................................................................... nb/intel/haswell: Align more stuff with Broadwell Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I1ab3df0657e8e2fa074197b445bdce624b0d4d48 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/northbridge.c 3 files changed, 20 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46981/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index cc4487c..0e7967f 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -33,8 +33,13 @@ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfxvtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4); + /* First, add DRHD entries */ + if (emit_igd) { const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 28a33d8..0758cdf 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -175,10 +175,10 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x4000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x8000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x1000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x1000) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a6f187c..64a274d 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -264,9 +264,8 @@ static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { + for (i = 0; i < NUM_MAP_ENTRIES; i++) read_map_entry(dev, &memory_map[i], &values[i]); - } } static void mc_report_map_entries(struct device *dev, uint64_t *values) @@ -569,7 +568,7 @@ northbridge_dmi_init(); northbridge_topology_init(); - /* Enable Power Aware Interrupt Routing. */ + /* Enable Power Aware Interrupt Routing */ pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ @@ -586,7 +585,7 @@ MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - /* Configure turbo power limits 1ms after reset complete bit. */ + /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); @@ -595,12 +594,12 @@ } static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &pci_dev_ops_pci, + .read_resources = mc_read_resources, + .acpi_fill_ssdt = generate_cpu_entries, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short mc_pci_device_ids[] = { @@ -628,7 +627,7 @@ static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type. */ + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab3df0657e8e2fa074197b445bdce624b0d4d48 Gerrit-Change-Number: 46981 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

Deepika Punyamurtula has uploaded a new patch set (#14) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 14 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: acpi_device: Add ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW
by Ricardo Ribalda (Code Review) 29 Oct '20

29 Oct '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46963 ) Change subject: acpi_device: Add ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW ...................................................................... acpi_device: Add ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW This is, GPIOs that their value is active low and need to trigger and IRQ on both edges. Change-Id: I9d55d0f321a832607f780c0a7ba7eddb7c893832 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/include/acpi/acpi_device.h 1 file changed, 13 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46963/1 diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 301f9b0..5dd584e 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -216,38 +216,42 @@ #define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) ACPI_GPIO_INPUT_CFG(gpio, 1) /* GpioInt-related macros */ -#define ACPI_GPIO_IRQ_CFG(_gpio, _mode, _polarity, _wake) { \ +#define ACPI_GPIO_IRQ_CFG(_gpio, _mode, _polarity, _wake, _active_low) { \ .type = ACPI_GPIO_TYPE_INTERRUPT, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ + .active_low = _active_low, \ .irq.mode = _mode, \ .irq.polarity = _polarity, \ .irq.wake = _wake, \ .pin_count = 1, \ .pins = { (_gpio) } } -#define ACPI_GPIO_IRQ_EDGE(gpio, polarity) \ - ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, 0) +#define ACPI_GPIO_IRQ_EDGE(gpio, polarity, active_low) \ + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, 0, active_low) #define ACPI_GPIO_IRQ_EDGE_WAKE(gpio, polarity) \ - ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, ACPI_IRQ_WAKE) + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, ACPI_IRQ_WAKE, 0) #define ACPI_GPIO_IRQ_LEVEL(gpio, polarity) \ - ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, 0) + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, 0, 0) #define ACPI_GPIO_IRQ_LEVEL_WAKE(gpio, polarity) \ - ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, ACPI_IRQ_WAKE) + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, ACPI_IRQ_WAKE, 0) /* Edge Triggered Active High GPIO interrupt */ #define ACPI_GPIO_IRQ_EDGE_HIGH(gpio) \ - ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_HIGH) + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_HIGH, 0) /* Edge Triggered Active Low GPIO interrupt */ #define ACPI_GPIO_IRQ_EDGE_LOW(gpio) \ - ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_LOW) + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_LOW, 0) /* Edge Triggered Active Both GPIO interrupt */ #define ACPI_GPIO_IRQ_EDGE_BOTH(gpio) \ - ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_BOTH) + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_BOTH, 0) + +#define ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW(gpio) \ + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_BOTH, 1) /* Edge Triggered Active High GPIO interrupt with wake */ #define ACPI_GPIO_IRQ_EDGE_HIGH_WAKE(gpio) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/46963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d55d0f321a832607f780c0a7ba7eddb7c893832 Gerrit-Change-Number: 46963 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Tim Wawrzynczak (Code Review) 29 Oct '20

29 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 31: TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" > Hi Tim, sensor 3 is the ambient sensor near the fan. […] Ack https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 74: > Good catch :) I have added it for now. […] If you are not changing this table from the baseboard, you can leave it out here and it will pick up the baseboard default (variants/baseboard/devicetree.cb) -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 13 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 18:49:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 13: (4 comments) https://review.coreboot.org/c/coreboot/+/46676/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46676/12//COMMIT_MSG@7 PS12, Line 7: UPSTREAM: > Remove here; this will get added when the patch is downstreamed into the chromium repo Done https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 26: # Default DPTF Policy for all Volteer boards if not overridden > This comment isn't true here Done, deleted this https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 31: TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" > Won't the fan be running constantly at these thresholds? Hi Tim, sensor 3 is the ambient sensor near the fan. These settings can help provide more granular fan control. The sensor temp is seen to vary between ~30-50 for different workloads https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 74: > Did you intend to leave out the setting for the 500mA charging rate?, i.e. […] Good catch :) I have added it for now. @Pegatron, please comment on this -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 13 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 18:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Deepika Punyamurtula (Code Review) 29 Oct '20

29 Oct '20

Deepika Punyamurtula has uploaded a new patch set (#13) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 13 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer: correct memory id for elemi
by Chen Wisley (Code Review) 29 Oct '20

29 Oct '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46770 ) Change subject: mb/google/volteer: correct memory id for elemi ...................................................................... mb/google/volteer: correct memory id for elemi BUG=170604353 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into kernel. Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db --- M src/mainboard/google/volteer/variants/elemi/memory.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46770/1 diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index d3de4be..32b7abc 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -21,10 +21,10 @@ int variant_memory_sku(void) { gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_3, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db Gerrit-Change-Number: 46770 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Tim Wawrzynczak (Code Review) 29 Oct '20

29 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 12: (4 comments) https://review.coreboot.org/c/coreboot/+/46676/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46676/12//COMMIT_MSG@7 PS12, Line 7: UPSTREAM: Remove here; this will get added when the patch is downstreamed into the chromium repo https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 26: # Default DPTF Policy for all Volteer boards if not overridden This comment isn't true here https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 31: TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" Won't the fan be running constantly at these thresholds? https://review.coreboot.org/c/coreboot/+/46676/12/src/mainboard/google/volt… PS12, Line 74: Did you intend to leave out the setting for the 500mA charging rate?, i.e. ``` [3] = { 8, 500 }}" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 12 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 17:43:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020