coreboot-gerrit October 2020

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Change in coreboot[master]: [TEST] Disable IPU for drawcia
by Maulik V Vaghela (Code Review) 29 Oct '20

29 Oct '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46957 ) Change subject: [TEST] Disable IPU for drawcia ...................................................................... [TEST] Disable IPU for drawcia Change-Id: Ia07529e92bad3c3015cf94c953ecffb488d00642 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46957/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 5942121..f4cd43b 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -65,21 +65,7 @@ register "tcc_offset" = "20" # TCC of 85C device domain 0 on - device pci 05.0 on # IPU - MIPI Camera - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{1,4}" - register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" - register "cio2_prt[0]" = "0" - register "cio2_prt[1]" = "2" - device generic 0 on end - end - end - + device pci 05.0 off end # IPU - MIPI Camera device pci 04.0 on chip drivers/intel/dptf # Default DPTF Policy for all drawcia boards if not overridden -- To view, visit https://review.coreboot.org/c/coreboot/+/46957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia07529e92bad3c3015cf94c953ecffb488d00642 Gerrit-Change-Number: 46957 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
by Subrata Banik (Code Review) 29 Oct '20

29 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46873 ) Change subject: mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' ...................................................................... mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c 4 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46873/1 diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 9d7cc91..209ee6a 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -51,12 +51,10 @@ switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - mupd->FspmConfig.DqPinsInterleaved = 1; memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: - mupd->FspmConfig.DqPinsInterleaved = 0; memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c index f8b3660..353bb7f 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -5,7 +5,23 @@ #include <baseboard/variants.h> #include <soc/romstage.h> -static const struct mb_cfg mem_config = { +static const struct mb_cfg ddr4_mem_config = { + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ @@ -33,13 +49,7 @@ { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* - * Baseboard Rcomp target values. - */ - .rcomp_targets = {40, 30, 33, 33, 30}, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -48,5 +58,12 @@ const struct mb_cfg *variant_memory_params(void) { - return &mem_config; + int board_id = get_board_id(); + + if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) + return &lpddr4_mem_config; + else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) + return &ddr4_mem_config; + + die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 76930be..5fed568 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -77,6 +77,12 @@ uint16_t rcomp_targets[5]; /* + * Dqs Pins Interleaved Setting. Enable/Disable Control + * TRUE = enable, FALSE = disable + */ + bool dq_pins_interleaved; + + /* * Early Command Training Enable/Disable Control * TRUE = enable, FALSE = disable */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index e7084a5..f5f747d 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -180,4 +180,5 @@ mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Gerrit-Change-Number: 46873 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 29 Oct '20

29 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#10). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 10 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 29 Oct '20

29 Oct '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 9: (6 comments) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 63: 15000 > Yes, this looks like a typo. These need to be different. […] Done https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 63: .pl1 = {.min_power = 15000, : .max_power = 15000, > PL1 min max set to the same value looks weird. I'm not quite sure if this is reasonable. Done https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 68: .pl2 = {.min_power = 51000, : .max_power = 51000, > as here. Done https://review.coreboot.org/c/coreboot/+/46676/7/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/7/src/mainboard/google/volte… PS7, Line 4: > TCC and PL1/PL2 ovveride settings are missing. Can you please add the below - […] Done https://review.coreboot.org/c/coreboot/+/46676/7/src/mainboard/google/volte… PS7, Line 39: 15000 > Can you also please help address this? This should be 3000 as per your report. Done https://review.coreboot.org/c/coreboot/+/46676/7/src/mainboard/google/volte… PS7, Line 44: 51000 > This should be 15000 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 07:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by build bot (Jenkins) (Code Review) 29 Oct '20

29 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/9/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/9/src/mainboard/google/volte… PS9, Line 3: register "DdiPort2Hpd" = "0" trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 07:52:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 29 Oct '20

29 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#9). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 29 Oct '20

29 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#8). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 8 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Subrata Banik (Code Review) 29 Oct '20

29 Oct '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/K… File src/drivers/intel/fsp2_0/Kconfig.debug_blob: https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/K… PS2, Line 42: bool "Display Firmware Ingredient Version Information" both help text is same ? https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/h… File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/h… PS2, Line 262: entire code can be optimized, you don't need complete #if/#endif guard https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/i… File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h: https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/i… PS2, Line 37: remove one empty line -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Oct 2020 07:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: SD Card detect INT fix
by Ronak Kanabar (Code Review) 29 Oct '20

29 Oct '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46656 ) Change subject: mb/google/dedede: SD Card detect INT fix ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88febf15a9450c11068439f3fb260308369ea3db Gerrit-Change-Number: 46656 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/jasperlake: Select DISPLAY_FSP_VERSION_INFO_2
by Ronak Kanabar (Code Review) 29 Oct '20

29 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45907 ) Change subject: soc/intel/jasperlake: Select DISPLAY_FSP_VERSION_INFO_2 ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If68b704c4304357b0046a510545fc213d7ed5887 Gerrit-Change-Number: 45907 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 29 Oct 2020 06:56:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020