Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44570
to review the following change.
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params was found in flash, do dram full calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 19ab639..dd80beb 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,16 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c
+MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 84c13b7..96a8c91 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -64,6 +64,39 @@ return DRAMC_ERR_FAST_CALIBRATION; }
+static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) + return -1; + + if (cbfs_prog_stage_load(&dram)) + return -2; + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -103,6 +136,20 @@ } else { printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "Successfully loaded blobs and run DRAM calibration\n"); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } }
static void setup_dramc_voltage_before_calibration(void)
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 1:
Not urgent, but for the dramc_params I think there are lots of duplication from 8183. We should move those to common/ so future chipsets can reuse same logic for loading cached DRAM.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG@9 PS5, Line 9: was were
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG@9 PS5, Line 9: n n.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44570
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/6
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 6: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG@9 PS5, Line 9: n
n.
Ack
https://review.coreboot.org/c/coreboot/+/44570/5//COMMIT_MSG@9 PS5, Line 9: was
were
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 6: Code-Review+1
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44570/10/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/10/src/soc/mediatek/mt8192/me... PS10, Line 145: Successfully loaded blobs and run DRAM calibration Maybe simply "Full calibration passed"?
Yidi Lin has uploaded a new patch set (#11) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/11
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44570/10/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/10/src/soc/mediatek/mt8192/me... PS10, Line 145: Successfully loaded blobs and run DRAM calibration
Maybe simply "Full calibration passed"?
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 11: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 11:
(10 comments)
https://review.coreboot.org/c/coreboot/+/44570/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44570/11//COMMIT_MSG@10 PS11, Line 10: Please elaborate, what blob version you used for testing, and paste the newly added messages, and also measure and add timings.
Please also mention and elaborate on the newly addad blob `dram.elf`. How big is it? What does it do?
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... PS11, Line 41: dram I think, I’d be good to make that name configurable in Kconfig.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 75: static int dram_run_full_calibration(struct dramc_param *dparam) Please measure the time of the blob execution (add CBMEM timestamps).
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 83: return -1; Please print an error message.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 86: return -2; Please print an error message.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 135: printk(BIOS_ERR, "Failed to run fast calibration\n"); This with the new messages below is confusing. The return value should be printed.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 149: DRAM-K What does DRAM-K stand for?
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 149: Full Calibration Starting full calilbration …
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 153: printk(BIOS_INFO, "Full calibration passed\n"); It should be prefixed with some RAM related term or be more elaborate.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 160: } If the the different error codes are not considered (-1…-4), they shouldn’t be used.
Yidi Lin has uploaded a new patch set (#12) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/12
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 14:
@yidi please address Paul's comments
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 14:
Patch Set 14:
@yidi please address Paul's comments
Xi Chen will help this change.
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 15:
(10 comments)
https://review.coreboot.org/c/coreboot/+/44570/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44570/11//COMMIT_MSG@10 PS11, Line 10:
Please elaborate, what blob version you used for testing, and paste the newly added messages, and al […]
Ack.
measure/timings already exists, in CBFS: CBFS log: locating 'fallbak/dram', Found @ offset 2af40 size 1c50d. read ... 12802us
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... PS11, Line 41: dram
I think, I’d be good to make that name configurable in Kconfig.
The name "dram" won't modify, i think it can also stay here?
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 75: static int dram_run_full_calibration(struct dramc_param *dparam)
Please measure the time of the blob execution (add CBMEM timestamps).
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 83: return -1;
Please print an error message.
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 86: return -2;
Please print an error message.
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 135: printk(BIOS_ERR, "Failed to run fast calibration\n");
This with the new messages below is confusing. The return value should be printed.
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 149: Full Calibration
Starting full calilbration …
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 149: DRAM-K
What does DRAM-K stand for?
stands for: dram calibration.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 153: printk(BIOS_INFO, "Full calibration passed\n");
It should be prefixed with some RAM related term or be more elaborate.
Ack
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 160: }
If the the different error codes are not considered (-1…-4), they shouldn’t be used.
Ack
Xi Chen has uploaded a new patch set (#16) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 83 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/16
Yidi Lin has uploaded a new patch set (#17) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/17
Yidi Lin has uploaded a new patch set (#18) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 83 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/18
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 18: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/Ma... PS11, Line 41: dram
The name "dram" won't modify, i think it can also stay here?
Given that we currently don't have plan to change this, should be fine to keep it in current shape until we've moved the whole calibration to a shared module.
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/11/src/soc/mediatek/mt8192/me... PS11, Line 149: DRAM-K
stands for: dram calibration.
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 18:
(7 comments)
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 145: : One space after ":"
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 145: printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration in %ld msecs, error:%d\n", Line too long (>96 chars)
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 146: stopwatch_duration_msecs Align this with BIOS_ERR
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 153: stopwatch_duration_msecs(&sw)); Same
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 161: Starting Running
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 168: stopwatch_duration_msecs(&sw)); Same
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 177: stopwatch_duration_msecs(&sw)); Same
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 18: -Code-Review
Xi Chen has uploaded a new patch set (#19) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 84 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/19
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 19:
(7 comments)
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... File src/soc/mediatek/mt8192/memory.c:
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 145: printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration in %ld msecs, error:%d\n",
Line too long (>96 chars)
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 145: :
One space after ":"
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 146: stopwatch_duration_msecs
Align this with BIOS_ERR
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 153: stopwatch_duration_msecs(&sw));
Same
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 161: Starting
Running
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 168: stopwatch_duration_msecs(&sw));
Same
Ack
https://review.coreboot.org/c/coreboot/+/44570/18/src/soc/mediatek/mt8192/me... PS18, Line 177: stopwatch_duration_msecs(&sw));
Same
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
Patch Set 19: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44570 )
Change subject: soc/mediatek/mt8192: Do dram full calibration ......................................................................
soc/mediatek/mt8192: Do dram full calibration
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44570 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 84 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8b2831c..13b5b21 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,16 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c
+MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + BL31_MAKEARGS += PLAT=mt8192
CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 5820fbf..549dede 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -7,6 +7,7 @@ #include <ip_checksum.h> #include <soc/emi.h> #include <symbols.h> +#include <timer.h>
static int mt_mem_test(const struct dramc_data *dparam) { @@ -41,7 +42,7 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) { if (!is_valid_dramc_param(dparam)) { - printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Invalid DRAM calibration data from flash\n"); dump_param_header((void *)dparam); return -1; } @@ -49,7 +50,7 @@ const u32 checksum = compute_checksum(dparam); if (dparam->header.checksum != checksum) { printk(BIOS_ERR, - "Invalid DRAM calibration checksum from flash " + "DRAM-K: Invalid DRAM calibration checksum from flash " "(expected: %#x, saved: %#x)\n", checksum, dparam->header.checksum); return DRAMC_ERR_INVALID_CHECKSUM; @@ -58,13 +59,13 @@ const u16 config = CONFIG(MT8192_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; if (dparam->dramc_datas.ddr_info.config_dvfs != config) { printk(BIOS_WARNING, - "Incompatible config for calibration data from flash " + "DRAM-K: Incompatible config for calibration data from flash " "(expected: %#x, saved: %#x)\n", config, dparam->dramc_datas.ddr_info.config_dvfs); return -1; }
- printk(BIOS_INFO, "DRAM calibration data valid pass\n"); + printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); mt_set_emi(&dparam->dramc_datas); if (mt_mem_test(&dparam->dramc_datas) == 0) return 0; @@ -72,6 +73,43 @@ return DRAMC_ERR_FAST_CALIBRATION; }
+static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) { + printk(BIOS_ERR, "DRAM-K: Locate program failed\n"); + return -1; + } + + if (cbfs_prog_stage_load(&dram)) { + printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n"); + return -2; + } + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "DRAM-K: Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -93,23 +131,51 @@ static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry) { struct dramc_param *dparam = dparam_ops->param; + struct stopwatch sw; + int ret;
/* Load calibration params from flash and run fast calibration */ mem_init_set_default_config(dparam, ddr_geometry); if (dparam_ops->read_from_flash(dparam)) { printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); - if (dram_run_fast_calibration(dparam) != 0) { - printk(BIOS_ERR, "Failed to run fast calibration\n"); + stopwatch_init(&sw); + + ret = dram_run_fast_calibration(dparam); + if (ret != 0) { + printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " + "in %ld msecs, error: %d\n", + stopwatch_duration_msecs(&sw), ret);
/* Erase flash data after fast calibration failed */ memset(dparam, 0xa5, sizeof(*dparam)); dparam_ops->write_to_flash(dparam); } else { - printk(BIOS_INFO, "Fast calibration passed\n"); + printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); return; } } else { - printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Failed to read calibration data from flash\n"); + } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + + stopwatch_init(&sw); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "DRAM-K: Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } else { + printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); } }
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