January 2020 - coreboot-gerrit

Change in coreboot[master]: mainboard/google: Allow Hatch variants to read SPD data over SMBus
by Edward O'Callaghan (Code Review) Jan. 2, 2020

Jan. 2, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36449 ) Change subject: mainboard/google: Allow Hatch variants to read SPD data over SMBus ...................................................................... mainboard/google: Allow Hatch variants to read SPD data over SMBus All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/romstage_spd_smbus.c 3 files changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36449/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 219be22..e339693 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -60,7 +60,11 @@ config ROMSTAGE_SPD_CBFS bool - default y + default y if !ROMSTAGE_SPD_SMBUS + +config ROMSTAGE_SPD_SMBUS + bool + default n config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 3ed82e7..0740c08 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c new file mode 100644 index 0000000..245b61d --- /dev/null +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/gpio.h> +#include <spd_bin.h> +#include <gpio.h> + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + int is_single_ch_mem; + struct cnl_mb_cfg memcfg; + variant_memory_params(&memcfg); + + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + memcfg.dq_pins_interleaved = 1; + get_spd_smbus(&blk); + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[0]; + if (!is_single_ch_mem) { + memcfg.spd[1].read_type = READ_SMBUS; + memcfg.spd[1].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[1]; + } + dump_spd_info(&blk); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Gerrit-Change-Number: 36449 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: {driver,soc}/intel: Move chipset specific logo handling to soc
by Wim Vervoorn (Code Review) Jan. 2, 2020

Jan. 2, 2020

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37791 ) Change subject: {driver,soc}/intel: Move chipset specific logo handling to soc ...................................................................... {driver,soc}/intel: Move chipset specific logo handling to soc FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of the chipset specific FSP structures. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook FBG1701 Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/logo.c M src/drivers/intel/fsp1_1/ramstage.c M src/soc/intel/braswell/chip.c 4 files changed, 34 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37791/1 diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index a5eac0e..e50edd8 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -26,6 +26,7 @@ /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Called after the silicon init code has run. */ void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ @@ -33,7 +34,7 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); -void load_logo(SILICON_INIT_UPD *params); +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params); void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index 03b2715..23aad01 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -11,15 +11,24 @@ * GNU General Public License for more details. */ +#include <cbfs.h> +#include <cbmem.h> #include <soc/ramstage.h> -#include <console/console.h> -#include <fsp/ramstage.h> -#include <include/cbfs.h> -void load_logo(SILICON_INIT_UPD *params) +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) { - params->PcdLogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->PcdLogoPtr, - params->PcdLogoSize, CBFS_TYPE_RAW); - if (!params->PcdLogoSize) - params->PcdLogoPtr = 0; + const struct cbmem_entry *logo_entry = NULL; + void *logo_buffer; + + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); + if (logo_entry) { + logo_buffer = cbmem_entry_start(logo_entry); + if (logo_buffer) { + *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, + 1 * MiB, CBFS_TYPE_RAW); + if (logo_size) + *logo_ptr = (UINT32)logo_buffer; + } + } + return (logo_entry); } diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 9ecdfd6..40e79cc 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -69,7 +69,7 @@ EFI_STATUS status; UPD_DATA_REGION *upd_ptr; VPD_DATA_REGION *vpd_ptr; - const struct cbmem_entry *logo_entry; + const struct cbmem_entry *logo_entry = NULL; /* Display the FSP header */ if (fsp_info_header == NULL) { @@ -96,13 +96,8 @@ load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); - if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) { - silicon_init_params.PcdLogoSize = 1 * MiB; - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, - silicon_init_params.PcdLogoSize); - silicon_init_params.PcdLogoPtr = (UINT32)cbmem_entry_start(logo_entry); - load_logo(&silicon_init_params); - } + if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) + logo_entry = soc_load_logo(&silicon_init_params); /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) @@ -122,7 +117,7 @@ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); /* The logo_entry can be freed up now as it is not required any longer */ - if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) + if (logo_entry && !is_s3_wakeup) cbmem_entry_remove(logo_entry); /* Mark graphics init done after SiliconInit if VBT was provided */ @@ -214,3 +209,9 @@ __weak void soc_silicon_init_params(SILICON_INIT_UPD *params) { } + +/* Load bmp and set FSP parameters, fsp_load_logo can be used */ +__weak const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) +{ + return NULL; +} diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d179cea..026b281 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -181,6 +181,11 @@ board_silicon_USB2_override(params); } +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) +{ + return fsp_load_logo(&params->PcdLogoPtr, &params->PcdLogoSize); +} + void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e Gerrit-Change-Number: 37791 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: intel/i82371eb: Drop unused code
by Kyösti Mälkki (Code Review) Jan. 2, 2020

Jan. 2, 2020

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38038 ) Change subject: intel/i82371eb: Drop unused code ...................................................................... intel/i82371eb: Drop unused code Change-Id: I71b5e46efac718df6d4b52d27a20fe1cf6d96427 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82371eb/Makefile.inc M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/i82371eb.h D src/southbridge/intel/i82371eb/reset.c 4 files changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38038/1 diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 390fd97..f30360f 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -23,7 +23,6 @@ ramstage-y += ide.c ramstage-y += usb.c ramstage-y += smbus.c -ramstage-y += reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 4d98a30..898cdff 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -47,14 +47,7 @@ /* TODO: List the other datasheets. */ #include <device/device.h> -#include "i82371eb.h" - -void i82371eb_enable(struct device *dev) -{ - /* TODO: Nothing to do? */ -} const struct chip_operations southbridge_intel_i82371eb_ops = { CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") - .enable_dev = i82371eb_enable, }; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index d35b215..55242ef 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,11 +19,6 @@ #if !defined(__ACPI__) -#include <device/device.h> -void i82371eb_enable(struct device *dev); - -void i82371eb_hard_reset(void); - void enable_smbus(void); void enable_pm(void); @@ -45,7 +40,6 @@ #define XBCS 0x4e /* X-Bus chip select register */ #define GENCFG 0xb0 /* General configuration register */ -#define RC 0xcf9 /* Reset control register */ /* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ @@ -115,8 +109,6 @@ #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ #define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ #define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ -#define SRST (1 << 1) /* System Reset */ -#define RCPU (1 << 2) /* Reset CPU */ #define SMB_HST_EN (1 << 0) /* Host Interface Enable */ #define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ #define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ diff --git a/src/southbridge/intel/i82371eb/reset.c b/src/southbridge/intel/i82371eb/reset.c deleted file mode 100644 index 1d1dd64..0000000 --- a/src/southbridge/intel/i82371eb/reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "i82371eb.h" - -/** - * Initiate a hard reset. - */ -void i82371eb_hard_reset(void) -{ - outb(SRST | RCPU, RC); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b5e46efac718df6d4b52d27a20fe1cf6d96427 Gerrit-Change-Number: 38038 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: lib/: Drop generic_dump_spd
by Kyösti Mälkki (Code Review) Jan. 2, 2020

Jan. 2, 2020

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38037 ) Change subject: lib/: Drop generic_dump_spd ...................................................................... lib/: Drop generic_dump_spd Not built, relies on SMBUS for SPD and we do not have a globally defined spd_read_byte() prototype. Change-Id: Ifb9d3aa31207cb5b99f475b70f52a03aca73432b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/lib/generic_dump_spd.c 1 file changed, 0 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38037/1 diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c deleted file mode 100644 index fdde026..0000000 --- a/src/lib/generic_dump_spd.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This code is derived from the Opteron boards' debug.c. - * It should go away either there or here, depending what fits better. - */ - -#include <console/console.h> - -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < 4; i++) { - unsigned int device; - device = ctrl->channel0[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for (j = 0; j < 256; j++) { - int status; - unsigned int char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = spd_read_byte(device, j); - if (status < 0) { - printk(BIOS_DEBUG, "bad device\n"); - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for (j = 0; j < 256; j++) { - int status; - unsigned int char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: "); - status = spd_read_byte(device, j); - if (status < 0) { - printk(BIOS_DEBUG, "bad device\n"); - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} - -#if 0 -void dump_spd_registers(void) -{ - unsigned int device; - device = SMBUS_MEM_DEVICE_START; - printk(BIOS_DEBUG, "\n"); - while (device <= SMBUS_MEM_DEVICE_END) { - int status = 0; - int i; - printk(BIOS_DEBUG, "dimm %02x", device); - for (i = 0; (i < 256) && (status == 0); i++) { - unsigned int char byte; - if ((i % 20) == 0) - printk(BIOS_DEBUG, "\n%3d: ", i); - status = smbus_read_byte(device, i, &byte); - if (status != 0) { - printk(BIOS_DEBUG, "bad device\n"); - continue; - } - printk(BIOS_DEBUG, "%02x ", byte); - } - device += SMBUS_MEM_DEVICE_INC; - printk(BIOS_DEBUG, "\n"); - } -} -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb9d3aa31207cb5b99f475b70f52a03aca73432b Gerrit-Change-Number: 38037 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: RFC) src/acpi: Update license headers to SPDX
by Martin Roth (Code Review) Jan. 2, 2020

Jan. 2, 2020

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36176 ) Change subject: RFC) src/acpi: Update license headers to SPDX ...................................................................... RFC) src/acpi: Update license headers to SPDX While I was working on updating the headers to move copyrights into the AUTHORS file, I got a request to switch to SPDX headers as well. Linux has moved completely to SPDX headers, which are easier to maintain, have good definitions, are very short, and can be checked automatically. This is completely unlike our current header situation. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3 --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/sata.c M src/acpi/sata.h 4 files changed, 9 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36176/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 72cfff5..3c6aeb1 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config ACPI_SATA_GENERATOR bool diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 53ac679..7c2092d 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -1 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c index d7fcbd6..ae43e7d 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +/* This file is part of the coreboot project. */ #include "sata.h" diff --git a/src/acpi/sata.h b/src/acpi/sata.h index fecf4c6..04cd80c 100644 --- a/src/acpi/sata.h +++ b/src/acpi/sata.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +/* This file is part of the coreboot project. */ #ifndef __ACPI_SATA_H__ #define __ACPI_SATA_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/36176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3 Gerrit-Change-Number: 36176 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: util/lint: Update license header text for SPDX headers.
by Martin Roth (Code Review) Jan. 2, 2020

Jan. 2, 2020

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36175 ) Change subject: util/lint: Update license header text for SPDX headers. ...................................................................... util/lint: Update license header text for SPDX headers. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e --- M util/lint/lint-000-license-headers 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36175/1 diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 9b3553b..db4390a 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -62,6 +62,8 @@ cmos\.default\ " +HEADER_TEXT="license header" + #space separated list of directories to test if [ "$1" = "" ]; then HEADER_DIRS="src util" @@ -69,6 +71,11 @@ HEADER_DIRS="$1" fi +if [ "$2" = "SPDX_ONLY" ]; then +SPDX_ONLY=1 +HEADER_TEXT="SPDX identifer" +fi + LC_ALL=C export LC_ALL #get initial list from git, removing HEADER_EXCLUDED files. @@ -96,6 +103,10 @@ } #search the files for license headers +check_for_license 'SPDX-License-Identifier: *GPL-2.0-or-later' +check_for_license 'SPDX-License-Identifier: *GPL-2.0-only' + +if [ ! "${SPDX_ONLY}" = "1" ]; then check_for_license "under the terms of the GNU General Public License" \ "WITHOUT ANY WARRANTY" check_for_license 'IS PROVIDED .*"AS IS"' @@ -106,13 +117,13 @@ check_for_license 'THE AUTHORS DISCLAIM.*ALL WARRANTIES WITH REGARD TO THIS SOFTWARE' check_for_license 'No license required' check_for_license 'GNU Lesser General Public' -check_for_license 'SPDX-License-Identifier:.*GPL-2.0-or-later' +fi for file in $headerlist; do # Verify the file exists, and has content that requires a header # This assumes that a file that has 4 lines or fewer is not notable # enough to require a license. if [ -f "$file" ] && [ "$(wc -l < "$file")" -gt 4 ]; then - echo "$file has no recognized license header." + echo "$file has no recognized ${HEADER_TEXT}." fi done -- To view, visit https://review.coreboot.org/c/coreboot/+/36175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e Gerrit-Change-Number: 36175 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/**/acpi_tables.c: Drop lid settings on desktops
by Angel Pons (Code Review) Jan. 2, 2020

Jan. 2, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37993 ) Change subject: mb/**/acpi_tables.c: Drop lid settings on desktops ...................................................................... mb/**/acpi_tables.c: Drop lid settings on desktops Unike laptops and some trash cans, desktop boardss do not have a lid. Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b75pro3-m/acpi_tables.c M src/mainboard/intel/dcp847ske/acpi_tables.c M src/mainboard/sapphire/pureplatinumh61/acpi_tables.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37993/1 diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 7d634a0..370b709 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -27,9 +27,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. - gnvs->lids = 1; - gnvs->tcrt = 100; gnvs->tpsv = 90; } diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index 88c7019..0d9c2c5 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -28,9 +28,6 @@ gnvs->s5u0 = 1; gnvs->s5u1 = 1; - // No LID: open by default. - gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index a790b0b..8503ccd 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -26,9 +26,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. - gnvs->lids = 1; - gnvs->tcrt = 100; gnvs->tpsv = 90; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702 Gerrit-Change-Number: 37993 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
by Mike Banon (Code Review) Jan. 2, 2020

Jan. 2, 2020

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38026 ) Change subject: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A ...................................................................... MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A These are the boards I have and currently working on. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I3f366105371c7d2568da6682b24cb52bce2d5467 --- M MAINTAINERS 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38026/1 diff --git a/MAINTAINERS b/MAINTAINERS index 6c565f7..97ffaee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,11 @@ S: Maintained F: src/mainboard/lenovo/ +LENOVO G505S MAINBOARD +M: Mike Banon <mikebdp2(a)gmail.com> +S: Maintained +F: src/mainboard/lenovo/g505s/ + APPLE MAINBOARDS M: Evgeny Zinoviev <me(a)ch1p.io> S: Maintained @@ -282,6 +287,11 @@ S: Maintained F: src/mainboard/asrock/h81m-hds/ +ASUS AM1I-A MAINBOARD +M: Mike Banon <mikebdp2(a)gmail.com> +S: Maintained +F: src/mainboard/asus/am1i-a/ + ASUS MAXIMUS IV GENE-Z MAINBOARD M: Tristan Corrick <tristan(a)corrick.kiwi> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/38026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f366105371c7d2568da6682b24cb52bce2d5467 Gerrit-Change-Number: 38026 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/acpi: Drop empty PCSD device nodes
by Nico Huber (Code Review) Jan. 2, 2020

Jan. 2, 2020

Hello HAOUAS Elyes, Michał Żygowski, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38033 to review the following change. Change subject: amd/acpi: Drop empty PCSD device nodes ...................................................................... amd/acpi: Drop empty PCSD device nodes These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID), but they don't provide any information and are not referenced anywhere. Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl 8 files changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38033/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 6e3bc93..8130791 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -24,10 +24,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index f679234..c360da6 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -44,10 +44,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index 3300db0..ce889c7 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -44,10 +44,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index f3d42fa..ffe1367 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -44,10 +44,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 761ff44..28e2224 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -44,10 +44,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index 3300db0..ce889c7 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -44,10 +44,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index b1c2d31..208ea26 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -45,10 +45,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index b1c2d31..208ea26 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -45,10 +45,6 @@ Name(_ADR, 0x00000000) } /* end AMRT */ -Device(PCSD) { /* Processor configuration space devices */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -} - /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) -- To view, visit https://review.coreboot.org/c/coreboot/+/38033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Gerrit-Change-Number: 38033 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836
by Mike Banon (Code Review) Jan. 2, 2020

Jan. 2, 2020

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33777 Change subject: asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836 ...................................................................... asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836 The majority of Socket AM1 APUs [1] - three out of five (three Athlons, the most powerful for this socket) - have the integrated VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Set the default to more common one. [1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22K… Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd --- M src/mainboard/asus/am1i-a/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/33777/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..42ab5c6 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -44,7 +44,7 @@ config VGA_BIOS_ID string - default "1002,9836" + default "1002,9830" config HUDSON_LEGACY_FREE bool -- To view, visit https://review.coreboot.org/c/coreboot/+/33777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd Gerrit-Change-Number: 33777 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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