coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/common: Split some SMBUS support file
by Kyösti Mälkki (Code Review) 03 Jan '20

03 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38049 ) Change subject: soc/intel/common: Split some SMBUS support file ...................................................................... soc/intel/common: Split some SMBUS support file It is expected that smbuslib.c will be removed, leave the parts we want to keep in smbus_early.c. Change-Id: I21355fe95385d07c9f254fc80c90264a9539bb00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38049/1 diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index 76de352..9202b5a 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -14,11 +14,9 @@ */ #include <device/pci_def.h> -#include <device/early_smbus.h> #include <intelblocks/smbus.h> #include <reg_script.h> #include <soc/pci_devs.h> -#include "smbuslib.h" static const struct reg_script smbus_init_script[] = { /* Set SMBus I/O base address */ @@ -35,21 +33,6 @@ REG_SCRIPT_END, }; -u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) -{ - return smbus_read16(SMBUS_IO_BASE, addr, offset); -} - -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - return smbus_read8(SMBUS_IO_BASE, addr, offset); -} - -u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) -{ - return smbus_write8(SMBUS_IO_BASE, addr, offset, value); -} - void smbus_common_init(void) { reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 0d3901f..e2a0ed9 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <device/early_smbus.h> #include <device/smbus_def.h> #include <timer.h> #include "smbuslib.h" @@ -176,3 +177,18 @@ return data; } + +u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) +{ + return smbus_read16(SMBUS_IO_BASE, addr, offset); +} + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return smbus_read8(SMBUS_IO_BASE, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return smbus_write8(SMBUS_IO_BASE, addr, offset, value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21355fe95385d07c9f254fc80c90264a9539bb00 Gerrit-Change-Number: 38049 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/braswell: Drop use of <device/early_smbus.h>
by Kyösti Mälkki (Code Review) 03 Jan '20

03 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38046 ) Change subject: intel/braswell: Drop use of <device/early_smbus.h> ...................................................................... intel/braswell: Drop use of <device/early_smbus.h> Change-Id: Id3fa0745e90d8bb99965eceec0ac129fe0ff7446 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/smbus.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38046/1 diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c index 1dfd4c7..abf2fea 100644 --- a/src/soc/intel/braswell/smbus.c +++ b/src/soc/intel/braswell/smbus.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <device/early_smbus.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <device/pci_def.h> @@ -24,16 +23,6 @@ #include <soc/smbus.h> #include <southbridge/intel/common/smbus.h> -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); -} - -u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) -{ - return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); -} - int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf) { #ifdef __SIMPLE_DEVICE__ -- To view, visit https://review.coreboot.org/c/coreboot/+/38046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3fa0745e90d8bb99965eceec0ac129fe0ff7446 Gerrit-Change-Number: 38046 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdblocks/acpimmio: add missing MMIO functions
by Michał Żygowski (Code Review) 03 Jan '20

03 Jan '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37813 ) Change subject: amdblocks/acpimmio: add missing MMIO functions ...................................................................... amdblocks/acpimmio: add missing MMIO functions Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 2 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37813/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index c441ab8..7194853 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -214,6 +214,36 @@ write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } +static inline uint8_t pm2_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline uint16_t pm2_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline uint32_t pm2_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline void pm2_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + +static inline void pm2_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + +static inline void pm2_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + static inline uint8_t biosram_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); @@ -354,6 +384,131 @@ write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } +/* Old GPIO configuration registers */ +static inline uint8_t gpio_100_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline uint16_t gpio_100_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline uint32_t gpio_100_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline void gpio_100_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +static inline void gpio_100_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +static inline void gpio_100_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +/* New GPIO banks configuration registers */ +/* GPIO bank 0 */ +static inline uint8_t gpio0_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline uint16_t gpio0_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline uint32_t gpio0_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline void gpio0_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +static inline void gpio0_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +static inline void gpio0_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +/* GPIO bank 1 */ +static inline uint8_t gpio1_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline uint16_t gpio1_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline uint32_t gpio1_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline void gpio1_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +static inline void gpio1_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +static inline void gpio1_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +/* GPIO bank 2 */ +static inline uint8_t gpio2_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline uint16_t gpio2_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline uint32_t gpio2_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline void gpio2_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + +static inline void gpio2_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + +static inline void gpio2_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + static inline uint8_t xhci_pm_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 9a15840..4d62b39 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -48,6 +48,7 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_GPIO_BASE_100 0xfed80100 #define ACPIMMIO_SMI_BASE 0xfed80200 #define ACPIMMIO_PMIO_BASE 0xfed80300 #define ACPIMMIO_PMIO2_BASE 0xfed80400 -- To view, visit https://review.coreboot.org/c/coreboot/+/37813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Gerrit-Change-Number: 37813 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdblocks/biosram: Force use of abstraction
by Kyösti Mälkki (Code Review) 03 Jan '20

03 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37862 ) Change subject: amdblocks/biosram: Force use of abstraction ...................................................................... amdblocks/biosram: Force use of abstraction Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/biosram.h 4 files changed, 48 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/37862/1 diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index e33f02d..814fdf3 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -11,9 +11,55 @@ * GNU General Public License for more details. */ -#include <cbmem.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/acpimmio_map.h> #include <amdblocks/biosram.h> +#include <cbmem.h> +#include <device/mmio.h> +#include <stdint.h> + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +static uint8_t biosram_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); +} + +static void biosram_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); +} + +static uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ +{ + return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); +} + +static uint32_t biosram_read32(uint8_t reg) +{ + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); +} + +static void biosram_write16(uint8_t reg, uint16_t value) +{ + biosram_write8(reg, value & 0xff); + value >>= 8; + biosram_write8(reg + sizeof(uint8_t), value & 0xff); +} + +static void biosram_write32(uint8_t reg, uint32_t value) +{ + biosram_write16(reg, value & 0xffff); + value >>= 16; + biosram_write16(reg + sizeof(uint16_t), value & 0xffff); +} + + +/* Access to BIOSRAM is only allowed through the abstractions below. */ void *get_ap_entry_ptr(void) { diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index a589ef5..202e47a 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -72,28 +72,3 @@ value >>= 16; pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index c441ab8..46d088f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -116,14 +116,6 @@ void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); - -/* Access BIOS RAM storage at 0xfed80500 */ -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); - - static inline uint8_t sm_pci_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); @@ -214,16 +206,6 @@ write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -static inline uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -static inline void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - static inline uint8_t acpi_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index db28310..4bfd629 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -16,12 +16,6 @@ #include <stdint.h> -/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ -#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ -#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ -#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ -#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ - /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Gerrit-Change-Number: 37862 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/i2c: add i2c driver for Realtek 1308
by Wonkyu Kim (Code Review) 03 Jan '20

03 Jan '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37882 ) Change subject: src/drivers/i2c: add i2c driver for Realtek 1308 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44fc8199f2153e18537023dfd92e0ce6a3ecb9c Gerrit-Change-Number: 37882 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Jan 2020 02:28:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 03 Jan '20

03 Jan '20

Wonkyu Kim has uploaded a new patch set (#12) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, UART, RP, I2C max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 03 Jan '20

03 Jan '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 11: (5 comments) https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 102: if SOC_INTEL_TIGERLAKE > > Code should have default value without condition ... […] Ack https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 115: 16 > This should be 12 Done https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 149: if SOC_INTEL_TIGERLAKE > Code should have default value without condition and this soc folder is TGL soc folder. […] Ack https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 168: if SOC_INTEL_TIGERLAKE > Use default for Tigerlake which does not require condition. Done https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 173: if SOC_INTEL_TIGERLAKE > Use default for Tigerlake which does not require condition. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 11 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Jan 2020 01:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c: add i2c driver for Realtek 1308
by Nick Vaccaro (Code Review) 03 Jan '20

03 Jan '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37882 ) Change subject: src/drivers/i2c: add i2c driver for Realtek 1308 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44fc8199f2153e18537023dfd92e0ce6a3ecb9c Gerrit-Change-Number: 37882 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Jan 2020 01:04:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Add initial mainboard code
by Wonkyu Kim (Code Review) 03 Jan '20

03 Jan '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37868 ) Change subject: mb/intel/tglrvp: Add initial mainboard code ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Gerrit-Change-Number: 37868 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Jan 2020 00:36:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Add initial mainboard code
by Wonkyu Kim (Code Review) 03 Jan '20

03 Jan '20

Wonkyu Kim has uploaded a new patch set (#10) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37868 ) Change subject: mb/intel/tglrvp: Add initial mainboard code ...................................................................... mb/intel/tglrvp: Add initial mainboard code This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Tigerlake". 2. Replace "icelake_rvp" with "tglrvp". 3. Rename "icl" with "tgl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake". 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add board support namely BOARD_INTEL_TGLRVP_UP3 10. Replace icl_u and icl_y variant with tglrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per tigerlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 32MB BIOS region. TEST=Build tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/mainboard.c A src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/empty.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/spd/spd_util.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb A src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 23 files changed, 1,220 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37868/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/37868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Gerrit-Change-Number: 37868 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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