Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 )
Change subject: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings
......................................................................
Patch Set 6: Code-Review-1
Please rebase on current master. You'll see that the Tiger Lake changes
don't compile.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 )
Change subject: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings
......................................................................
Patch Set 6:
(1 comment)
We should give people a chance to test coreboot+GitHub FSP
before moving forward. IIRC, Ice Lake worked on a WIP port
during 36C3, what about Comet Lake? Denverton?
https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/ro…
PS6, Line 43:
There is no way to predict if the official headers will lack it. And
I doubt if this is build tested.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 )
Change subject: drivers/fsp2_0: drop support for FSP-T
......................................................................
Patch Set 5:
> Patch Set 5:
>
> Has this been discussed at the project level? What's the result of the discussion?
AFAIK this has been discussed in one of the leadership meetings. @Patrick Georgi any info on that?
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 )
Change subject: drivers/fsp2_0: drop support for FSP-T
......................................................................
Patch Set 5:
Has this been discussed at the project level? What's the result of the discussion?
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