Change in coreboot[master]: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bind...

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 )

Change subject: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings
......................................................................


Patch Set 6:

(1 comment)

We should give people a chance to test coreboot+GitHub FSP
before moving forward. IIRC, Ice Lake worked on a WIP port
during 36C3, what about Comet Lake? Denverton?

https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... 
PS6, Line 43: 
There is no way to predict if the official headers will lack it. And
I doubt if this is build tested.



-- 
To view, visit https://review.coreboot.org/c/coreboot/+/37579
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9
Gerrit-Change-Number: 37579
Gerrit-PatchSet: 6
Gerrit-Owner: Mimoja <[e-mail]>
Gerrit-Reviewer: Angel Pons <[e-mail]>
Gerrit-Reviewer: David Guckian <[e-mail]>
Gerrit-Reviewer: Edward O'Callaghan <[e-mail]>
Gerrit-Reviewer: Mimoja <[e-mail]>
Gerrit-Reviewer: Nico Huber <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Philipp Deppenwiese <[e-mail]>
Gerrit-Reviewer: Vanessa Eusebio <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Comment-Date: Thu, 02 Jan 2020 14:03:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment