Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35625 )
Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Update arm-trusted-firmware submodule to upstream master
Updating from commit id 42cdeb93:
2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration)
to commit id 6a7cbfd5:
2019-09-18 15:22:03 +0000 - (Merge "amlogic: scpi: Add support to retrieve chip ID" into integration)
This brings in 38 new commits.
Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35625/1
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 42cdeb9..6a7cbfd 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 42cdeb93080f2b54a75be14e4f5ee776872f3f0f
+Subproject commit 6a7cbfd56837409b85c26df0206177e59fc95a79
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c
Gerrit-Change-Number: 35625
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35624 )
Change subject: Update chromeec submodule to upstream master
......................................................................
Update chromeec submodule to upstream master
Updating from commit id 860fe2962:
2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.)
to commit id 1906434c4:
2019-09-26 10:32:54 +0000 - (tcpci: add missing CPRINTS argument)
This brings in 1681 new commits.
Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M 3rdparty/chromeec
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35624/1
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index 860fe29..1906434 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d
+Subproject commit 1906434c4e62fac6792b6b81874810495be49b2e
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a
Gerrit-Change-Number: 35624
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35154 )
Change subject: ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled
......................................................................
ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled
Don't set a default bus type for the Chrome EC on x86. The platform
must select the bus, typically LPC or ESPI.
BUG=b:140055300
TEST=Build tested only
Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
M src/ec/google/chromeec/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/35154/1
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 2242653..2eb3b95 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -60,7 +60,7 @@
config EC_GOOGLE_CHROMEEC_LPC
depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
- def_bool y
+ def_bool n
help
Google Chrome EC via LPC bus.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Gerrit-Change-Number: 35154
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34816 )
Change subject: southbridge/intel: Add config option to validate firmware descriptor
......................................................................
southbridge/intel: Add config option to validate firmware descriptor
Add new config option to validate the Intel firmware descriptor against
the fmap layout. This will prevent a firmware descriptor from being used
that could corrupt regions of the bootimage in certian circumstances.
BUG=chromium:992215
TEST=Coming
Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f
Signed-off-by: Mathew King <mathewk(a)chromium.org>
---
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/firmware/Makefile.inc
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/34816/1
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index c3bd90d..6b7b5e6 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -54,6 +54,13 @@
This config states descriptor mode is *required* for the platform to
function properly, or to function at all.
+config VALIDATE_INTEL_DESCRIPTOR
+ def_bool n if INTEL_DESCRIPTOR_MODE_CAPABLE
+ help
+ This config enables validating the Intel firmware descriptor against the
+ fmap layout. If the firmware descriptor layout does not match the fmap
+ then the bootimage cannot be built.
+
config INTEL_CHIPSET_LOCKDOWN
depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
#ChromeOS's payload seems to handle finalization on its on.
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
index 898ab60..3b14f75 100644
--- a/src/southbridge/intel/common/firmware/Makefile.inc
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -35,6 +35,11 @@
printf " DD Adding Intel Firmware Descriptor\n"
dd if=$(IFD_BIN_PATH) \
of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y)
+ $(objutil)/ifdtool/ifdtool \
+ $(IFDTOOL_USE_CHIPSET) \
+ -t $(obj)/coreboot.pre
+endif
ifeq ($(CONFIG_HAVE_ME_BIN),y)
printf " IFDTOOL me.bin -> coreboot.pre\n"
$(objutil)/ifdtool/ifdtool \
--
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Gerrit-Branch: master
Gerrit-Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f
Gerrit-Change-Number: 34816
Gerrit-PatchSet: 1
Gerrit-Owner: Mathew King <mathewk(a)chromium.org>
Gerrit-MessageType: newchange
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35064 )
Change subject: mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer size
......................................................................
mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer size
Connected 4K monitor is not configured at max resolution. The
framebuffer size is too small.
Increase the framebuffer size to 64MB. This is sufficient for max
configuration of 1 HDMI monitor combined with internal LCD panel.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/facebook/fbg1701/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35064/1
diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb
index 3c82a03..a1999d8 100644
--- a/src/mainboard/facebook/fbg1701/devicetree.cb
+++ b/src/mainboard/facebook/fbg1701/devicetree.cb
@@ -9,7 +9,7 @@
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
- register "PcdIgdDvmt50PreAlloc" = "1"
+ register "PcdIgdDvmt50PreAlloc" = "2"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
--
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Gerrit-Branch: master
Gerrit-Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Gerrit-Change-Number: 35064
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-MessageType: newchange
Pavlushka has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33842
Change subject: src/superio/nuvoton/common/early_serial.c: Add symbol to select COM port for NCT5539D
......................................................................
src/superio/nuvoton/common/early_serial.c: Add symbol to select COM port for NCT5539D
src/superio/nuvoton/Makefile.inc: Add definition for NCT5539D
src/superio/nuvoton: Add support for NCT5539D
Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com>
Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c
---
M src/superio/nuvoton/Makefile.inc
M src/superio/nuvoton/common/early_serial.c
A src/superio/nuvoton/nct5539d/Kconfig
A src/superio/nuvoton/nct5539d/Makefile.inc
A src/superio/nuvoton/nct5539d/nct5539d.h
A src/superio/nuvoton/nct5539d/superio.c
6 files changed, 197 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33842/1
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index de4e99c..7306242 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -24,3 +24,4 @@
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c
index eaa3c5a..aaa0c63 100644
--- a/src/superio/nuvoton/common/early_serial.c
+++ b/src/superio/nuvoton/common/early_serial.c
@@ -73,6 +73,10 @@
/* Route COM A to GPIO8 pin group */
pnp_write_config(dev, 0x2a, 0x00);
+ if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A))
+ /* Route COM A to GPIO8 pin group */
+ pnp_write_config(dev, 0x2a, 0x40);
+
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig
new file mode 100644
index 0000000..0dd1402
--- /dev/null
+++ b/src/superio/nuvoton/nct5539d/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_NUVOTON_NCT5539D
+ bool
+ select SUPERIO_NUVOTON_COMMON_PRE_RAM
+
+config SUPERIO_NUVOTON_NCT5539D_COM_A
+ bool
+ depends on SUPERIO_NUVOTON_NCT5539D
+ default n
diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc
new file mode 100644
index 0000000..6e3fdf2
--- /dev/null
+++ b/src/superio/nuvoton/nct5539d/Makefile.inc
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c
diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h
new file mode 100644
index 0000000..f34660c
--- /dev/null
+++ b/src/superio/nuvoton/nct5539d/nct5539d.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NUVOTON_NCT5539D_H
+#define SUPERIO_NUVOTON_NCT5539D_H
+
+/* Logical Device Numbers (LDN). */
+#define NCT5539D_SP1 0x02 /* UART A */
+#define NCT5539D_KBC 0x05 /* Keyboard Controller */
+#define NCT5539D_CIR 0x06 /* Consumer IR */
+#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */
+#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */
+#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */
+#define NCT5539D_ACPI 0x0A /* ACPI */
+#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */
+#define NCT5539D_BCLK_WDT2 0x0D /* BCLK, WDT2 */
+#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */
+#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */
+#define NCT5539D_GPIO_PSO 0x11/*GPIO, RI PSOUT Wake-Up Status*/
+#define NCT5539D_SWEC 0x12/*SW Error Control*/
+#define NCT5539D_FLED 0x15 /* Fading LED */
+#define NCT5539D_DS 0x16 /* Deep Sleep */
+
+/* Virtual LDNs */
+#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
+#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
+#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
+#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
+#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345)
+#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345)
+#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345)
+#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345)
+#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78)
+#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78)
+#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS)
+#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS)
+#define NCT5539D_PCHDSW ((3 << 8) | NCT5539D_DS)
+#define NCT5539D_DSWWOPT ((4 << 8) | NCT5539D_DS)
+#define NCT5539D_DS3OPT ((5 << 8) | NCT5539D_DS)
+#define NCT5539D_DSDSS ((6 << 8) | NCT5539D_DS)
+#define NCT5539D_DSPU ((7 << 8) | NCT5539D_DS)
+
+#endif /* SUPERIO_NUVOTON_NCT5539D_H */
diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c
new file mode 100644
index 0000000..4cec976
--- /dev/null
+++ b/src/superio/nuvoton/nct5539d/superio.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com>
+ * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+* Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "nct5539d.h"
+
+
+static void nct5539d_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case NCT5539D_KBC:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = nct5539d_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0,
+ 0x0ff8, },
+ { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+ 0x0fff, 0x0fff, },
+ { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0,
+ 0x0ff8, },
+ { NULL, NCT5539D_ACPI},
+ { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+ 0x0ffe, 0x0ffe, },
+ { NULL, NCT5539D_BCLK_WDT2},
+ { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0,
+ 0x0ff8, },
+ { NULL, NCT5539D_GPIO_PP_OD},
+ { NULL, NCT5539D_WDT1},
+ { NULL, NCT5539D_WDT3},
+ { NULL, NCT5539D_GPIOBASE, PNP_IO0,
+ 0x0ff8, },
+ { NULL, NCT5539D_GPIO0},
+ { NULL, NCT5539D_GPIO2},
+ { NULL, NCT5539D_GPIO3},
+ { NULL, NCT5539D_GPIO4},
+ { NULL, NCT5539D_GPIO5},
+ { NULL, NCT5539D_GPIO7},
+ { NULL, NCT5539D_GPIO8},
+ { NULL, NCT5539D_GPIO_PSO},
+ { NULL, NCT5539D_SWEC},
+ { NULL, NCT5539D_FLED},
+ { NULL, NCT5539D_DS5},
+ { NULL, NCT5539D_DS3},
+ { NULL, NCT5539D_PCHDSW},
+ { NULL, NCT5539D_DSWWOPT},
+ { NULL, NCT5539D_DS3OPT},
+ { NULL, NCT5539D_DSDSS},
+ { NULL, NCT5539D_DSPU},
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct5539d_ops = {
+ CHIP_NAME("NUVOTON NCT5539D Super I/O")
+ .enable_dev = enable_dev,
+};
--
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Gerrit-MessageType: newchange
Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31617
Change subject: superio/ite/it8613e: add support for ITE IT8613E
......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses
FANs 2-5 and have SmartGuardian always enabled (no ON/OFF control) so
it relies on support in common ITE code. LDNs were taken from datasheet.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
A src/superio/ite/it8613e/Kconfig
A src/superio/ite/it8613e/Makefile.inc
A src/superio/ite/it8613e/chip.h
A src/superio/ite/it8613e/it8613e.h
A src/superio/ite/it8613e/superio.c
5 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/1
diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig
new file mode 100644
index 0000000..f09cac2
--- /dev/null
+++ b/src/superio/ite/it8613e/Kconfig
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+## Copyright (C) 2018 Kevin Cody-Little <kcodyjr(a)gmail.com>
+## Copyright (C) 2019 Protectli
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8613E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
+ select SUPERIO_ITE_ENV_CTRL
+ select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
+ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
+ select SUPERIO_ITE_ENV_CTRL_5FANS
+ select SUPERIO_ITE_ENV_CTRL_NO_ONOFF
diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc
new file mode 100644
index 0000000..75ab26b
--- /dev/null
+++ b/src/superio/ite/it8613e/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+## Copyright (C) 2019 Protectli
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c
diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h
new file mode 100644
index 0000000..65875c8
--- /dev/null
+++ b/src/superio/ite/it8613e/chip.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ * Copyright (C) 2019 Protectli
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8613E_CHIP_H
+#define SUPERIO_ITE_IT8613E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8613e_config {
+ struct ite_ec_config ec;
+};
+
+#endif /* SUPERIO_ITE_IT8613E_CHIP_H */
diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h
new file mode 100644
index 0000000..dace936
--- /dev/null
+++ b/src/superio/ite/it8613e/it8613e.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ * Copyright (C) 2019 Protectli
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8613E_H
+#define SUPERIO_ITE_IT8613E_H
+
+#define IT8613E_SP1 0x01 /* Com1 */
+#define IT8613E_EC 0x04 /* Environment controller */
+#define IT8613E_KBCK 0x05 /* PS/2 keyboard */
+#define IT8613E_KBCM 0x06 /* PS/2 mouse */
+#define IT8613E_GPIO 0x07 /* GPIO */
+#define IT8613E_CIR 0x0a /* Consumer Infrared */
+
+#endif /* SUPERIO_ITE_IT8613E_H */
diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c
new file mode 100644
index 0000000..6bffc16
--- /dev/null
+++ b/src/superio/ite/it8613e/superio.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ * Copyright (C) 2019 Protectli
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+#include <superio/ite/common/env_ctrl.h>
+
+#include "chip.h"
+#include "it8613e.h"
+
+static void it8613e_init(struct device *dev)
+{
+ const struct superio_ite_it8613e_config *conf = dev->chip_info;
+ const struct resource *res;
+
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case IT8613E_EC:
+ res = find_resource(dev, PNP_IDX_IO0);
+ if (!conf || !res)
+ break;
+ ite_ec_init(res->base, &conf->ec);
+ break;
+ case IT8613E_KBCK:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ case IT8613E_KBCM:
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8613e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ /* Serial Port 1 */
+ { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
+ /* Environmental Controller */
+ { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ffc, },
+ /* KBC Keyboard */
+ { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x0fff, 0x0fff, },
+ /* KBC Mouse */
+ { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, },
+ /* GPIO */
+ { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0fff, },
+ /* Consumer Infrared */
+ { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8613e_ops = {
+ CHIP_NAME("ITE IT8613E Super I/O")
+ .enable_dev = enable_dev,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a
Gerrit-Change-Number: 31617
Gerrit-PatchSet: 1
Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Gerrit-MessageType: newchange