coreboot-gerrit September 2019

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Change in coreboot[master]: intel/i945,i82801gx: Refactor early PCI bridge reset
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35678 ) Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ...................................................................... intel/i945,i82801gx: Refactor early PCI bridge reset Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 4 files changed, 26 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35678/1 diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..23f010c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <cf9_reset.h> -#include <delay.h> #include <console/console.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -246,10 +245,8 @@ enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset(); ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..7949b69 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> -#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -209,10 +208,8 @@ enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset(); ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d6d37d9..7ed58f6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,6 +17,8 @@ #include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> +#include <delay.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> @@ -549,14 +551,9 @@ * PCI bus 0x0a and check whether we find a device on 0:a.0 */ - /* First we reset the secondary bus */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg); reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -565,10 +562,7 @@ reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); + pci_s_bridge_set_secondary(p2peg, tmp_secondary); reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -614,11 +608,9 @@ reg32 |= 1; pci_write_config32(p2peg, PEGSTS, reg32); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -774,17 +766,14 @@ MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Toggle PCIRST# */ + pci_s_assert_secondary_reset(p2peg); reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); pci_write_config32(p2peg, 0x224, reg32); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + pci_s_deassert_secondary_reset(p2peg); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; @@ -880,6 +869,14 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } +void ich7_p2p_secondary_reset(void) +{ + pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); + pci_s_assert_secondary_reset(p2p_bridge); + mdelay(200); + pci_s_deassert_secondary_reset(p2p_bridge); +} + void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..fec8919 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,6 +39,8 @@ void i82801gx_enable(struct device *dev); #endif +void ich7_p2p_secondary_reset(void); + void enable_smbus(void); #if ENV_ROMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/35678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Gerrit-Change-Number: 35678 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: soc/intel: Drop config IED_REGION_SIZE
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34694 ) Change subject: soc/intel: Drop config IED_REGION_SIZE ...................................................................... soc/intel: Drop config IED_REGION_SIZE This a non-configurable platform constant, and if it were to be made configurable, it would be bool on/off switch. Change-Id: I812b35f765c7d6da95283714db0b38a3a09cec28 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 13 files changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/34694/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4bc6a65..a59d27f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -131,10 +131,6 @@ string default "cnl" -config IED_REGION_SIZE - hex - default 0x400000 - config HEAP_SIZE hex default 0x8000 diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f..605cc99 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -47,6 +47,9 @@ int smm_save_state_in_msrs; }; +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4*MiB) + /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 18ddeee..6674c9d 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -51,7 +51,7 @@ uintptr_t sub_base; size_t sub_size; void *smm_base; - const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t ied_size = FIXED_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3ba997d..9b27433 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -35,7 +35,7 @@ /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->IedSize = FIXED_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) m_cfg->UserBd = BOARD_TYPE_DESKTOP; diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 7931018..2f6eb9a 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -82,10 +82,6 @@ string default "icl" -config IED_REGION_SIZE - hex - default 0x400000 - config HEAP_SIZE hex default 0x8000 diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593..2887c5b 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -46,6 +46,9 @@ int smm_save_state_in_msrs; }; +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4*MiB) + /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 317f0fb..05ed749 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -49,7 +49,7 @@ uintptr_t sub_base; size_t sub_size; void *smm_base; - const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t ied_size = FIXED_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a4..23568a8 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -42,7 +42,7 @@ } m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->IedSize = FIXED_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4f4ec46..ad5f30c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -153,10 +153,6 @@ hex default 0x80000 -config IED_REGION_SIZE - hex - default 0x400000 - config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e976..9d8e24e 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,6 +48,9 @@ int smm_save_state_in_msrs; }; +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4*MiB) + void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 1058300..5133c21 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -63,7 +63,7 @@ uintptr_t sub_base; size_t sub_size; void *smm_base; - const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t ied_size = FIXED_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2d0de2f..b01dfb8 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -71,7 +71,7 @@ upd->MmioSize = 0x800; /* 2GB in MB */ upd->TsegSize = CONFIG_SMM_TSEG_SIZE; - upd->IedSize = CONFIG_IED_REGION_SIZE; + upd->IedSize = FIXED_IED_REGION_SIZE; upd->ProbelessTrace = config->ProbelessTrace; upd->EnableTraceHub = config->EnableTraceHub; if (vboot_recovery_mode_enabled()) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index bb86c63..b6e3551 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -271,7 +271,7 @@ m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->IedSize = FIXED_IED_REGION_SIZE; m_cfg->ProbelessTrace = config->ProbelessTrace; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; -- To view, visit https://review.coreboot.org/c/coreboot/+/34694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I812b35f765c7d6da95283714db0b38a3a09cec28 Gerrit-Change-Number: 34694 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35733 ) Change subject: intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1 ...................................................................... intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1 Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_baytrail/i2c.c M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35733/1 diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 3ea91e3..5f6ca467 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -117,7 +117,7 @@ base_ptr = (char*)base_adr[bus]; /* Set the I2C-device the user wants to use */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); /* Ensure we have the right PCI device */ if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || @@ -174,7 +174,7 @@ int stat; /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { printk(BIOS_INFO, "I2C: Invalid Base address\n"); @@ -233,7 +233,7 @@ int stat; /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { return I2C_ERR_INVALID_ADR; diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5f2b1b6..e0c2ff0 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -139,6 +139,8 @@ # define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) # define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +#define PCH_DEV_SLOT_I2C1 I2C1_DEV + /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Gerrit-Change-Number: 35733 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: intel/fsp_baytrail: Rename from xx_DEV_FUNC
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35732 ) Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ...................................................................... intel/fsp_baytrail: Rename from xx_DEV_FUNC Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/1 diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..59dc6be 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev); diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c0b0998..0df07ee 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -79,7 +79,7 @@ DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(XXX_DEVFN_SOC); config = config_of(dev); /* Set up default verb tables - Just HDMI audio */ @@ -142,26 +142,26 @@ continue; switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t"); - case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + case XXX_DEVFN_MIPI: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { @@ -174,24 +174,24 @@ printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", dev->enabled?"Enabled":"Disabled"); break; - case EMMC_DEV_FUNC: /* EMMC 4.1*/ + case XXX_DEVFN_EMMC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; - case MMC45_DEV_FUNC: /* MMC 4.5*/ + case XXX_DEVFN_MMC45: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; - case XHCI_DEV_FUNC: + case XXX_DEVFN_XHCI: UpdData->PcdEnableXhci = dev->enabled; break; - case EHCI_DEV_FUNC: + case XXX_DEVFN_EHCI: UpdData->PcdEnableXhci = !(dev->enabled); break; - case LPE_DEV_FUNC: + case XXX_DEVFN_LPE: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 5abe719..defd34a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,8 +17,6 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_ -#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - /* PCI config registers in LPC bridge. */ #define REVID 0x08 #define ABASE 0x40 /* IO BAR */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5d70879..5f2b1b6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -27,39 +27,39 @@ #define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x0f00 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) +# define XXX_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) /* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 # define MIPI_DEVID 0x0f38 -# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) +# define XXX_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) /* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 # define EMMC_DEVID 0x0f14 -# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) +# define XXX_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 # define SDIO_DEVID 0x0f15 -# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) +# define XXX_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 # define SD_DEVID 0x0f16 -# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) +# define XXX_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) /* SATA */ #define SATA_DEV 0x13 @@ -74,7 +74,7 @@ # define SATA_SP 0xD0 # define SATA_BIST1 0xE4 # define SATA_BIST2 0xE8 -# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) +# define XXX_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) /* xHCI */ @@ -84,25 +84,25 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +# define XXX_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 -# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) /* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 # define OTG_DEVID 0x0f37 -# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) /* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 # define MMC45_DEVID 0x0f50 -# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) +# define XXX_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) /* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -130,26 +130,26 @@ # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 # define I2C7_DEVID 0x0f47 -# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +# define XXX_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define XXX_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define XXX_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define XXX_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define XXX_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define XXX_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 # define TXE_DEVID 0x0f18 -# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) +# define XXX_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEVID 0x0f04 -# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) +# define XXX_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) # define HDA_AZUBAR 0x14 # define HDA_MMLA 0x64 # define HDA_MMUA 0x68 @@ -168,16 +168,16 @@ # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) +# define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 -# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) +# define XXX_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) /* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -199,12 +199,12 @@ # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 # define SPI_DEVID 0xf0e -# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) +# define XXX_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define XXX_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define XXX_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define XXX_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define XXX_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define XXX_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) /* Platform Controller Unit */ @@ -212,11 +212,12 @@ # define LPC_DEV PCU_DEV # define LPC_FUNC 0 # define LPC_DEVID 0x0f1c +# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) + # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +# define XXX_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) #endif /* _BAYTRAIL_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Gerrit-Change-Number: 35732 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35730 ) Change subject: sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC ...................................................................... sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/southbridge/intel/fsp_rangeley/pci_devs.h 2 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35730/1 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 43e71f4..a9d2ba7 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -52,7 +52,7 @@ DEVTREE_CONST config_t *config; printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(XXX_DEVFN_SOC); config = dev->chip_info; /* Set SPD addresses */ @@ -103,30 +103,30 @@ continue; switch (dev->path.pci.devfn) { - case GBE1_DEV_FUNC: - case GBE2_DEV_FUNC: - case GBE3_DEV_FUNC: - case GBE4_DEV_FUNC: + case XXX_DEVFN_GBE1: + case XXX_DEVFN_GBE2: + case XXX_DEVFN_GBE3: + case XXX_DEVFN_GBE4: UpdData->PcdEnableLan |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableLan %d\n", UpdData->PcdEnableLan); break; - case SATA2_DEV_FUNC: + case XXX_DEVFN_SATA2: UpdData->PcdEnableSata2 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", UpdData->PcdEnableSata2); break; - case SATA3_DEV_FUNC: + case XXX_DEVFN_SATA3: UpdData->PcdEnableSata3 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", UpdData->PcdEnableSata3); break; - case IQAT_DEV_FUNC: + case XXX_DEVFN_IQAT: UpdData->PcdEnableIQAT |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", UpdData->PcdEnableIQAT); break; - case USB2_DEV_FUNC: + case XXX_DEVFN_USB2: UpdData->PcdEnableUsb20 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", UpdData->PcdEnableUsb20); diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 89f3c5c..69edae6 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -26,72 +26,72 @@ /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) +# define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) +# define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) +# define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) +# define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 -# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) +# define XXX_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 -# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) +# define XXX_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 -# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) +# define XXX_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 -# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) +# define XXX_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 -# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) +# define XXX_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 -# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) +# define XXX_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 -# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) +# define XXX_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 -# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) +# define XXX_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 -# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) +# define XXX_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 -# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) +# define XXX_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ #define PCU_DEV 0x1f @@ -99,18 +99,18 @@ /* Low Pin Count (LPC/ISA) */ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define XXX_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 -# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) +# define XXX_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 -# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) +# define XXX_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC) #define SOC_DEVID 0x1f08 #define PCIE_PORT1_DEVID 0x1f10 -- To view, visit https://review.coreboot.org/c/coreboot/+/35730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Gerrit-Change-Number: 35730 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/sconfig: Issue header for exposed PCI and PNP names
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35488 ) Change subject: util/sconfig: Issue header for exposed PCI and PNP names ...................................................................... util/sconfig: Issue header for exposed PCI and PNP names Let `sconfig` output a C header file with the symbol names that we generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP device names). We add another command line argument for the path to the header file. As the file is similar in nature to our `config.h` we simply put it in $(obj)/ too. Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc M util/sconfig/main.c 2 files changed, 38 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35488/1 diff --git a/Makefile.inc b/Makefile.inc index 3c3088d..aca787f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -591,11 +591,12 @@ endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c +DEVICETREE_STATIC_H := $(obj)/static.h $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6b421ec..5c23333 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -696,7 +696,7 @@ return 0; } -static void pass0(FILE *fil, struct device *ptr, struct device *next) +static void pass0(FILE *fil, FILE *head, struct device *ptr, struct device *next) { if (ptr == &base_root_dev) { fprintf(fil, "STORAGE struct bus %s_links[];\n", @@ -781,7 +781,7 @@ fprintf(fil, "\t};\n"); } -static void pass1(FILE *fil, struct device *ptr, struct device *next) +static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) { int pin; struct chip_instance *chip_ins = ptr->chip_instance; @@ -883,16 +883,22 @@ emit_dev_links(fil, ptr); } -static void expose_device_names(FILE *fil, struct device *ptr, struct device *next) +static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) { /* Only devices on root bus here. */ - if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) + if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } - if (ptr->bustype == PNP) + if (ptr->bustype == PNP) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } } static void add_siblings_to_queue(struct queue_entry **bfs_q_head, @@ -916,8 +922,8 @@ } } -static void walk_device_tree(FILE *fil, struct device *ptr, - void (*func)(FILE *, struct device *, +static void walk_device_tree(FILE *fil, FILE *head, struct device *ptr, + void (*func)(FILE *, FILE *, struct device *, struct device *)) { struct queue_entry *bfs_q_head = NULL; @@ -926,7 +932,7 @@ while ((ptr = dequeue_head(&bfs_q_head))) { add_children_to_queue(&bfs_q_head, ptr); - func(fil, ptr, peek_queue_head(bfs_q_head)); + func(fil, head, ptr, peek_queue_head(bfs_q_head)); } } @@ -995,7 +1001,7 @@ } } -static void inherit_subsystem_ids(FILE *file, struct device *dev, +static void inherit_subsystem_ids(FILE *file, FILE *head, struct device *dev, struct device *next) { struct device *p; @@ -1020,17 +1026,18 @@ static void usage(void) { - printf("usage: sconfig devicetree_file output_file [override_devicetree_file]\n"); + printf("usage: sconfig devicetree_file output_file header_file [override_devicetree_file]\n"); exit(1); } enum { DEVICEFILE_ARG = 1, OUTPUTFILE_ARG, + HEADERFILE_ARG, OVERRIDE_DEVICEFILE_ARG, }; -#define MANDATORY_ARG_COUNT 3 +#define MANDATORY_ARG_COUNT 4 #define OPTIONAL_ARG_COUNT 1 #define TOTAL_ARG_COUNT (MANDATORY_ARG_COUNT + OPTIONAL_ARG_COUNT) @@ -1365,6 +1372,7 @@ const char *base_devtree = argv[DEVICEFILE_ARG]; const char *outputc = argv[OUTPUTFILE_ARG]; + const char *outputh = argv[HEADERFILE_ARG]; const char *override_devtree; parse_devicetree(base_devtree, &base_root_bus); @@ -1389,18 +1397,31 @@ exit(1); } + FILE *autohead = fopen(outputh, "w"); + if (!autohead) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputh); + perror(NULL); + fclose(autogen); + exit(1); + } + fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); + fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); + fprintf(autohead, "#include <device/device.h>\n\n"); + emit_chips(autogen); - walk_device_tree(autogen, &base_root_dev, inherit_subsystem_ids); + walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); fprintf(autogen, "\n/* pass 0 */\n"); - walk_device_tree(autogen, &base_root_dev, pass0); + walk_device_tree(autogen, autohead, &base_root_dev, pass0); fprintf(autogen, "\n/* pass 1 */\n"); - walk_device_tree(autogen, &base_root_dev, pass1); + walk_device_tree(autogen, autohead, &base_root_dev, pass1); /* Expose static devicenames to global namespace. */ fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, &base_root_dev, expose_device_names); + walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); + fclose(autohead); fclose(autogen); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/35488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Gerrit-Change-Number: 35488 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in libgfxinit[master]: gma: Refactor Update_Outputs()
by Nico Huber (Code Review) 04 Oct '19

04 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35528 ) Change subject: gma: Refactor Update_Outputs() ...................................................................... gma: Refactor Update_Outputs() In Update_Outputs(), we used to have two steps, iterating over all available pipes: We disabled all pipes whose mode changed or that would be disabled otherwise. Then, we enabled all pipes with new modes. As checks for validity of the configurations were only done on demand in the second step, that left us with no knowledge about what configs would actually be tried. To make this information available for future work, we add a validation in between the existing two. That gives us: 1. Disable pipes - whose mode changed - that were disconneced 2. Validate all new configs 3. Enable/update pipes with new configs This way, we can make global decisions between 2. and 3. based on the new, _valid_ configurations. The `Loop_Invariant` of 2. allows us to keep the validation in mind, to satisfy pre-conditions of the various steps ahead. Change-Id: I079ae8f85c821a272b5d095c1ef437ee804aa9ac Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config_helpers.ads M common/hw-gfx-gma.adb 2 files changed, 60 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/28/35528/1 diff --git a/common/hw-gfx-gma-config_helpers.ads b/common/hw-gfx-gma-config_helpers.ads index 023b3e5..a2aeb06 100644 --- a/common/hw-gfx-gma-config_helpers.ads +++ b/common/hw-gfx-gma-config_helpers.ads @@ -33,7 +33,12 @@ Pipe : in Pipe_Index; Port : in Port_Type; Mode : in Mode_Type; - Success : out Boolean); + Success : out Boolean) + with + Post => + (if Success then + Port_Cfg.Mode.H_Visible = Mode.H_Visible and + Port_Cfg.Mode.V_Visible = Mode.V_Visible); ---------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index de79fd3..462f5c4 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -96,10 +96,11 @@ Pipe_Cfg : in Pipe_Config; Success : out Boolean) with - Pre => Pipe_Cfg.Port in Active_Port_Type + Pre => + Pipe_Cfg.Port in Active_Port_Type and + Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Pipe_Cfg.Mode, Pipe) is Port_Cfg : Port_Config; - Scaler_Available : Boolean; begin pragma Debug (Debug.New_Line); pragma Debug (Debug.Put_Line @@ -109,12 +110,6 @@ (Port_Cfg, Pipe, Pipe_Cfg.Port, Pipe_Cfg.Mode, Success); if Success then - Display_Controller.Scaler_Available (Scaler_Available, Pipe); - Success := Config_Helpers.Valid_Config - (Pipe_Cfg.Framebuffer, Port_Cfg.Mode, Pipe, Scaler_Available); - end if; - - if Success then Connector_Info.Preferred_Link_Setting (Port_Cfg, Success); end if; @@ -221,19 +216,9 @@ end if; end Check_HPD; - Power_Changed : Boolean := False; - Old_Configs : Pipe_Configs; - - -- Only called when we actually tried to change something - -- so we don't congest the log with unnecessary messages. - procedure Update_Power - is - begin - if not Power_Changed then - Power_And_Clocks.Power_Up (Old_Configs, Configs); - Power_Changed := True; - end if; - end Update_Power; + Update_Power : Boolean := False; + Old_Configs, + New_Configs : Pipe_Configs; function Full_Update (Cur_Config, New_Config : Pipe_Config) return Boolean is @@ -253,13 +238,14 @@ end Full_Update; begin Old_Configs := Cur_Configs; + New_Configs := Configs; -- disable all pipes that changed or had a hot-plug event for Pipe in Pipe_Index loop declare Unplug_Detected : Boolean; Cur_Config : Pipe_Config renames Cur_Configs (Pipe); - New_Config : Pipe_Config renames Configs (Pipe); + New_Config : Pipe_Config renames New_Configs (Pipe); begin if Cur_Config.Port /= Disabled then Check_HPD (Cur_Config.Port, Unplug_Detected); @@ -267,35 +253,60 @@ if Full_Update (Cur_Config, New_Config) or Unplug_Detected then Disable_Output (Pipe, Cur_Config); Cur_Config.Port := Disabled; - Update_Power; + Update_Power := True; end if; end if; end; end loop; + -- validate new configs, filter invalid configs and those waiting for HPD + for Pipe in Pipe_Index loop + declare + Success : Boolean := True; + Scaler_Available : Boolean; + Cur_Config : Pipe_Config renames Cur_Configs (Pipe); + New_Config : Pipe_Config renames New_Configs (Pipe); + begin + if New_Config.Port /= Disabled then + if Wait_For_HPD (New_Config.Port) then + Check_HPD (New_Config.Port, Success); + Wait_For_HPD (New_Config.Port) := not Success; + end if; + + if Success then + Display_Controller.Scaler_Available (Scaler_Available, Pipe); + Success := Config_Helpers.Valid_Config + (New_Config.Framebuffer, New_Config.Mode, + Pipe, Scaler_Available); + end if; + + if not Success then + New_Config.Port := Disabled; + end if; + end if; + end; + pragma Loop_Invariant + (for all P in Pipe_Index'First .. Pipe => + New_Configs (P).Port = Disabled or + Config_Helpers.Valid_FB + (New_Configs (P).Framebuffer, New_Configs (P).Mode, P)); + end loop; + -- enable all pipes that changed and should be active for Pipe in Pipe_Index loop declare Success : Boolean; - Scaler_Available : Boolean; Cur_Config : Pipe_Config renames Cur_Configs (Pipe); - New_Config : Pipe_Config renames Configs (Pipe); + New_Config : Pipe_Config renames New_Configs (Pipe); begin + -- full update if New_Config.Port /= Disabled and Full_Update (Cur_Config, New_Config) then - if Wait_For_HPD (New_Config.Port) then - Check_HPD (New_Config.Port, Success); - Wait_For_HPD (New_Config.Port) := not Success; - else - Success := True; - end if; + Power_And_Clocks.Power_Up (Old_Configs, New_Configs); + Update_Power := True; - if Success then - Update_Power; - Enable_Output (Pipe, New_Config, Success); - end if; - + Enable_Output (Pipe, New_Config, Success); if Success then Cur_Config := New_Config; end if; @@ -304,23 +315,17 @@ elsif New_Config.Port /= Disabled and Cur_Config.Framebuffer /= New_Config.Framebuffer then - Display_Controller.Scaler_Available (Scaler_Available, Pipe); - if Config_Helpers.Valid_Config - (New_Config.Framebuffer, New_Config.Mode, - Pipe, Scaler_Available) - then - Display_Controller.Setup_FB - (Pipe, New_Config.Mode, New_Config.Framebuffer); - Display_Controller.Update_Cursor - (Pipe, New_Config.Framebuffer, New_Config.Cursor); - Cur_Config := New_Config; - end if; + Display_Controller.Setup_FB + (Pipe, New_Config.Mode, New_Config.Framebuffer); + Display_Controller.Update_Cursor + (Pipe, New_Config.Framebuffer, New_Config.Cursor); + Cur_Config := New_Config; end if; end; end loop; - if Power_Changed then - Power_And_Clocks.Power_Down (Old_Configs, Configs, Cur_Configs); + if Update_Power then + Power_And_Clocks.Power_Down (Old_Configs, New_Configs, Cur_Configs); end if; end Update_Outputs; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I079ae8f85c821a272b5d095c1ef437ee804aa9ac Gerrit-Change-Number: 35528 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 10

Change in libgfxinit[master]: gma config_helpers: Add Maximum_Dotclock() function
by Nico Huber (Code Review) 04 Oct '19

04 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35529 ) Change subject: gma config_helpers: Add Maximum_Dotclock() function ...................................................................... gma config_helpers: Add Maximum_Dotclock() function Change-Id: Iaa25e774d38c7af12150523739d902cf8e758674 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma-config_helpers.ads 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/29/35529/1 diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb index a86af9e..8614787 100644 --- a/common/hw-gfx-gma-config_helpers.adb +++ b/common/hw-gfx-gma-config_helpers.adb @@ -79,6 +79,18 @@ when DP1 .. DP3 => DP); end To_Display_Type; + function Maximum_Dotclock (Configs : Pipe_Configs) return Frequency_Type + is + Max : Frequency_Type := Frequency_Type'First; + begin + for I in Pipe_Index loop + if Max < Configs (I).Mode.Dotclock then + Max := Configs (I).Mode.Dotclock; + end if; + end loop; + return Max; + end Maximum_Dotclock; + ---------------------------------------------------------------------------- -- Prepares link rate and lane count settings for an FDI connection. diff --git a/common/hw-gfx-gma-config_helpers.ads b/common/hw-gfx-gma-config_helpers.ads index a2aeb06..4756af2 100644 --- a/common/hw-gfx-gma-config_helpers.ads +++ b/common/hw-gfx-gma-config_helpers.ads @@ -28,6 +28,8 @@ function To_Display_Type (Port : Active_Port_Type) return Display_Type; + function Maximum_Dotclock (Configs : Pipe_Configs) return Frequency_Type; + procedure Fill_Port_Config (Port_Cfg : out Port_Config; Pipe : in Pipe_Index; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Iaa25e774d38c7af12150523739d902cf8e758674 Gerrit-Change-Number: 35529 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 7

Change in libgfxinit[master]: gma config_helpers: Revise Validate_Config()
by Nico Huber (Code Review) 04 Oct '19

04 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35527 ) Change subject: gma config_helpers: Revise Validate_Config() ...................................................................... gma config_helpers: Revise Validate_Config() Split it into Valid_FB() and Valid_Config() and make both expression functions. This will make it easier to use them for proofs. Change-Id: I0931217658000d3ff6d71515acb45aeb063768d5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma-config_helpers.ads M common/hw-gfx-gma-pipe_setup.ads M common/hw-gfx-gma.adb 4 files changed, 42 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/27/35527/1 diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb index c95bebc..a86af9e 100644 --- a/common/hw-gfx-gma-config_helpers.adb +++ b/common/hw-gfx-gma-config_helpers.adb @@ -12,7 +12,6 @@ -- GNU General Public License for more details. -- -with HW.GFX.GMA.Config; with HW.GFX.GMA.Connector_Info; with HW.GFX.GMA.DP_Info; with HW.GFX.GMA.Registers; @@ -182,40 +181,4 @@ end if; end Fill_Port_Config; - ---------------------------------------------------------------------------- - - -- Validates that a given configuration should work with - -- a given framebuffer. - function Validate_Config - (FB : Framebuffer_Type; - Mode : Mode_Type; - Pipe : Pipe_Index; - Scaler_Available : Boolean) - return Boolean - is - begin - -- No downscaling - -- Respect maximum scalable width - -- VGA plane is only allowed on the primary pipe - -- Only 32bpp RGB (ignored for VGA plane) - -- Stride must be big enough and a multiple of 64 bytes or the tile size - -- (ignored for VGA plane) - -- Y-Tiling and rotation are only supported on newer generations (with - -- Plane_Control) - -- 90 degree rotations are only supported with Y-tiling - return - ((Rotated_Width (FB) = Mode.H_Visible and - Rotated_Height (FB) = Mode.V_Visible) or - (Scaler_Available and - Rotated_Width (FB) <= Config.Maximum_Scalable_Width (Pipe) and - Rotated_Width (FB) <= Mode.H_Visible and - Rotated_Height (FB) <= Mode.V_Visible)) and - (FB.Offset /= VGA_PLANE_FRAMEBUFFER_OFFSET or Pipe = Primary) and - (FB.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or - (FB.BPC = 8 and Valid_Stride (FB) and - (Config.Has_Plane_Control or - (FB.Tiling /= Y_Tiled and FB.Rotation = No_Rotation)) and - (FB.Tiling = Y_Tiled or not Rotation_90 (FB)))); - end Validate_Config; - end HW.GFX.GMA.Config_Helpers; diff --git a/common/hw-gfx-gma-config_helpers.ads b/common/hw-gfx-gma-config_helpers.ads index d56be5e..023b3e5 100644 --- a/common/hw-gfx-gma-config_helpers.ads +++ b/common/hw-gfx-gma-config_helpers.ads @@ -14,6 +14,8 @@ with HW; +with HW.GFX.GMA.Config; + private package HW.GFX.GMA.Config_Helpers is @@ -39,18 +41,44 @@ Reason => "Needed for older compiler versions"); use type HW.Pos32; pragma Warnings (GNAT, On, """Integer_32"" is already use-visible *"); - function Validate_Config + + -- Validate that a framebuffer is valid for a given mode and pipe. + function Valid_FB + (FB : Framebuffer_Type; + Mode : Mode_Type; + Pipe : Pipe_Index) + return Boolean is + (-- No downscaling + -- Respect maximum scalable width + -- VGA plane is only allowed on the primary pipe + -- Only 32bpp RGB (ignored for VGA plane) + -- Stride must be big enough and a multiple of 64 bytes or the tile size + -- (ignored for VGA plane) + -- Y-Tiling and rotation are only supported on newer generations (with + -- Plane_Control) + -- 90 degree rotations are only supported with Y-tiling + ((Rotated_Width (FB) = Mode.H_Visible and + Rotated_Height (FB) = Mode.V_Visible) or + (Rotated_Width (FB) <= Config.Maximum_Scalable_Width (Pipe) and + Rotated_Width (FB) <= Mode.H_Visible and + Rotated_Height (FB) <= Mode.V_Visible)) and + (FB.Offset /= VGA_PLANE_FRAMEBUFFER_OFFSET or Pipe = Primary) and + (FB.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or + (FB.BPC = 8 and Valid_Stride (FB) and + (Config.Has_Plane_Control or + (FB.Tiling /= Y_Tiled and FB.Rotation = No_Rotation)) and + (FB.Tiling = Y_Tiled or not Rotation_90 (FB))))); + + -- Also validate that we only scale if a scaler is available. + function Valid_Config (FB : Framebuffer_Type; Mode : Mode_Type; Pipe : Pipe_Index; Scaler_Available : Boolean) - return Boolean - with - Post => - (if Validate_Config'Result then - Rotated_Width (FB) <= Mode.H_Visible and - Rotated_Height (FB) <= Mode.V_Visible and - (FB.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or - FB.Height + FB.Start_Y <= FB.V_Stride)); + return Boolean is + (Valid_FB (FB, Mode, Pipe) and + ((Rotated_Width (FB) = Mode.H_Visible and + Rotated_Height (FB) = Mode.V_Visible) or + Scaler_Available)); end HW.GFX.GMA.Config_Helpers; diff --git a/common/hw-gfx-gma-pipe_setup.ads b/common/hw-gfx-gma-pipe_setup.ads index 0edb0c9..990f306 100644 --- a/common/hw-gfx-gma-pipe_setup.ads +++ b/common/hw-gfx-gma-pipe_setup.ads @@ -13,6 +13,7 @@ -- with HW.GFX.GMA.Config; +with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.Registers; use type HW.Int32; @@ -26,11 +27,7 @@ Framebuffer : Framebuffer_Type; Cursor : Cursor_Type) with - Pre => - Rotated_Width (Framebuffer) <= Port_Cfg.Mode.H_Visible and - Rotated_Height (Framebuffer) <= Port_Cfg.Mode.V_Visible and - (Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or - Framebuffer.Height + Framebuffer.Start_Y <= Framebuffer.V_Stride); + Pre => Config_Helpers.Valid_FB (Framebuffer, Port_Cfg.Mode, Pipe); procedure Off (Pipe : Pipe_Index); @@ -43,11 +40,7 @@ Mode : Mode_Type; Framebuffer : Framebuffer_Type) with - Pre => - Rotated_Width (Framebuffer) <= Mode.H_Visible and - Rotated_Height (Framebuffer) <= Mode.V_Visible and - (Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or - Framebuffer.Height + Framebuffer.Start_Y <= Framebuffer.V_Stride); + Pre => Config_Helpers.Valid_FB (Framebuffer, Mode, Pipe); procedure Update_Cursor (Pipe : Pipe_Index; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 15d234a..de79fd3 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -110,7 +110,7 @@ if Success then Display_Controller.Scaler_Available (Scaler_Available, Pipe); - Success := Config_Helpers.Validate_Config + Success := Config_Helpers.Valid_Config (Pipe_Cfg.Framebuffer, Port_Cfg.Mode, Pipe, Scaler_Available); end if; @@ -305,7 +305,7 @@ Cur_Config.Framebuffer /= New_Config.Framebuffer then Display_Controller.Scaler_Available (Scaler_Available, Pipe); - if Config_Helpers.Validate_Config + if Config_Helpers.Valid_Config (New_Config.Framebuffer, New_Config.Mode, Pipe, Scaler_Available) then -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I0931217658000d3ff6d71515acb45aeb063768d5 Gerrit-Change-Number: 35527 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 5

Change in libgfxinit[master]: gma pcode: Move and revise mailbox handling
by Nico Huber (Code Review) 04 Oct '19

04 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35710 to review the following change. Change subject: gma pcode: Move and revise mailbox handling ...................................................................... gma pcode: Move and revise mailbox handling Unify the PCODE mailbox implementations (Linux' i915 uses the same implementation since Sandy Bridge, too) and add `Wait` and `Success` parameters so we can act correctly if something failed. This adds a lot of boilerplate. But we keep it contained in the new package `PCode` and the code outside it looks cleaner and handles errors more gracefully. In GNATprove, we track state of the mailbox' readiness in a ghost variable `Mailbox_Ready`. This allows us to skip the initial wait loop if we know that we already waited at the end of a previous call. The first call to a mailbox procedure has to be made with `Wait_Ready => True`. Also, start to experiment with a `use` clause for the `Register` package. It allows us to write a little more condensed code, with- out sacrificing much (in this program we can expect that `Read`/ `Write` means register access?) So far it looks good? Change-Id: I5daa3effb7ab774e4a35bd8794b0f67f57e4caa4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb M common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads A common/hw-gfx-gma-pcode.adb A common/hw-gfx-gma-pcode.ads M common/hw-gfx-gma.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb 8 files changed, 234 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/10/35710/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 7c5403b..67b6c17 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -31,6 +31,8 @@ gfxinit-y += hw-gfx-gma-pch-vga.adb gfxinit-y += hw-gfx-gma-pch-vga.ads gfxinit-y += hw-gfx-gma-pch.ads +gfxinit-y += hw-gfx-gma-pcode.adb +gfxinit-y += hw-gfx-gma-pcode.ads gfxinit-y += hw-gfx-gma-pipe_setup.adb gfxinit-y += hw-gfx-gma-pipe_setup.ads gfxinit-y += hw-gfx-gma-port_detect.ads diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index f6576d9..77f6b35 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -17,6 +17,7 @@ with HW.Debug; with HW.GFX.GMA.Config; with HW.GFX.GMA.Registers; +with HW.GFX.GMA.PCode; with HW.GFX.GMA.Power_And_Clocks_Haswell; with HW.GFX.GMA.DDI_Phy; @@ -242,10 +243,19 @@ when others => CDCLK_CD2X_DIV_SEL_1); -- for CDClk = CDClk_Ref CDCLK_CD2X_SSA_Precharge : constant Word32 := (if Freq >= 500_000_000 then CDCLK_CD2X_SSA_PRECHARGE_ENABLE else 0); + + Success : Boolean; begin - Power_And_Clocks_Haswell.GT_Mailbox_Write + PCode.Mailbox_Write (MBox => BXT_PCODE_CDCLK_CONTROL, - Value => BXT_CDCLK_PREPARE_FOR_CHANGE); + Command => BXT_CDCLK_PREPARE_FOR_CHANGE, + Wait_Ready => True, + Success => Success); + if not Success then + pragma Debug (Debug.Put_Line + ("ERROR: PCODE didn't acknowledge frequency change.")); + return; + end if; Write (Register => BXT_DE_PLL_ENABLE, @@ -274,9 +284,9 @@ CDCLK_CD2X_SSA_Precharge or CDCLK_CTL_CD_FREQ_DECIMAL (Freq)); - Power_And_Clocks_Haswell.GT_Mailbox_Write - (MBox => BXT_PCODE_CDCLK_CONTROL, - Value => Word32 ((Freq + (25_000_000 - 1)) / 25_000_000)); + PCode.Mailbox_Write + (MBox => BXT_PCODE_CDCLK_CONTROL, + Command => Word64 ((Freq + (25_000_000 - 1)) / 25_000_000)); end Set_CDClk; ---------------------------------------------------------------------------- diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb index 1c23254..332c3df 100644 --- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb +++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb @@ -17,6 +17,7 @@ with HW.Time; with HW.Debug; with HW.GFX.GMA.Config; +with HW.GFX.GMA.PCode; with HW.GFX.GMA.Registers; package body HW.GFX.GMA.Power_And_Clocks_Haswell is @@ -55,8 +56,6 @@ IPS_CTL_ENABLE : constant := 1 * 2 ** 31; DISPLAY_IPS_CONTROL : constant := 16#19#; - GT_MAILBOX_READY : constant := 1 * 2 ** 31; - ---------------------------------------------------------------------------- procedure PSR_Off @@ -88,18 +87,6 @@ ---------------------------------------------------------------------------- - procedure GT_Mailbox_Write (MBox : Word32; Value : Word32) is - begin - pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - - Registers.Wait_Unset_Mask (Registers.GT_MAILBOX, GT_MAILBOX_READY); - Registers.Write (Registers.GT_MAILBOX_DATA, Value); - Registers.Write (Registers.GT_MAILBOX, GT_MAILBOX_READY or MBox); - - Registers.Wait_Unset_Mask (Registers.GT_MAILBOX, GT_MAILBOX_READY); - Registers.Write (Registers.GT_MAILBOX_DATA, 0); - end GT_Mailbox_Write; - procedure IPS_Off is Enabled : Boolean; @@ -110,7 +97,7 @@ Registers.Is_Set_Mask (Registers.IPS_CTL, IPS_CTL_ENABLE, Enabled); if Enabled then if Config.Has_IPS_CTL_Mailbox then - GT_Mailbox_Write (DISPLAY_IPS_CONTROL, 0); + PCode.Mailbox_Write (DISPLAY_IPS_CONTROL, 0, Wait_Ready => True); Registers.Wait_Unset_Mask (Register => Registers.IPS_CTL, Mask => IPS_CTL_ENABLE, diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads index 87f5d07..7c5a647 100644 --- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads +++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads @@ -15,7 +15,6 @@ private package HW.GFX.GMA.Power_And_Clocks_Haswell is procedure PSR_Off; - procedure GT_Mailbox_Write (MBox : Word32; Value : Word32); procedure Pre_All_Off; procedure Post_All_Off is null; diff --git a/common/hw-gfx-gma-pcode.adb b/common/hw-gfx-gma-pcode.adb new file mode 100644 index 0000000..dd0fc6e --- /dev/null +++ b/common/hw-gfx-gma-pcode.adb @@ -0,0 +1,138 @@ +-- +-- Copyright (C) 2014-2016, 2019 secunet Security Networks AG +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with GNAT.Source_Info; + +with HW.Debug; +with HW.GFX.GMA.Registers; + +use HW.GFX.GMA.Registers; + +package body HW.GFX.GMA.PCode is + + GT_MAILBOX_READY : constant := 1 * 2 ** 31; + + -- Send a command and optionally wait for and return the reply. + procedure Mailbox_Write_Read + (MBox : in Word32; + Command : in Word64; + Reply : out Word64; + Wait_Ready : in Boolean := False; + Wait_Ack : in Boolean := True; + Success : out Boolean) + with + Pre => Mailbox_Ready or Wait_Ready, + Post => (if Wait_Ack and Success then Mailbox_Ready) + is + use type HW.Word64; + + Data : Word32; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Reply := 0; + Success := True; + + if Wait_Ready then + Wait_Unset_Mask (GT_MAILBOX, GT_MAILBOX_READY, Success => Success); + if not Success then + return; + end if; + end if; + + Write (GT_MAILBOX_DATA, Word32 (Command and 16#ffff_ffff#)); + Write (GT_MAILBOX_DATA_1, Word32 (Shift_Right (Command, 32))); + Write (GT_MAILBOX, GT_MAILBOX_READY or MBox); + Mailbox_Ready := False; + + if Wait_Ack then + Wait_Unset_Mask (GT_MAILBOX, GT_MAILBOX_READY, Success => Success); + Mailbox_Ready := Success; + + Read (GT_MAILBOX_DATA, Data); + Reply := Word64 (Data); + Read (GT_MAILBOX_DATA_1, Data); + Reply := Shift_Left (Word64 (Data), 32) or Reply; + + Write (GT_MAILBOX_DATA, 0); + Write (GT_MAILBOX_DATA_1, 0); + end if; + end Mailbox_Write_Read; + + procedure Mailbox_Write + (MBox : in Word32; + Command : in Word64; + Wait_Ready : in Boolean := False; + Wait_Ack : in Boolean := True; + Success : out Boolean) + is + pragma Warnings (GNATprove, Off, "unused assignment to ""Ignored_R"""); + Ignored_R : Word64; + begin + Mailbox_Write_Read + (MBox, Command, Ignored_R, Wait_Ready, Wait_Ack, Success); + end Mailbox_Write; + + procedure Mailbox_Request + (MBox : in Word32; + Command : in Word64; + Reply_Mask : in Word64; + Reply : in Word64 := 16#ffff_ffff_ffff_ffff#; + TOut_MS : in Natural := Registers.Default_Timeout_MS; + Wait_Ready : in Boolean := False; + Success : out Boolean) + is + use type HW.Word64; + + Timeout : constant Time.T := Time.MS_From_Now (TOut_MS); + Timed_Out : Boolean := False; + + Received_Reply : Word64; + begin + Success := False; + loop + pragma Loop_Invariant ((not Success and Wait_Ready) or Mailbox_Ready); + Mailbox_Write_Read + (MBox => MBox, + Command => Command, + Reply => Received_Reply, + Wait_Ready => not Success and Wait_Ready, + Success => Success); + exit when not Success; + + if (Received_Reply and Reply_Mask) = (Reply and Reply_Mask) then + -- Ignore timeout if we succeeded anyway. + Timed_Out := False; + exit; + end if; + exit when Timed_Out; + + Timed_Out := Time.Timed_Out (Timeout); + end loop; + + Success := Success and then not Timed_Out; + end Mailbox_Request; + + procedure Mailbox_Write + (MBox : Word32; + Command : Word64; + Wait_Ready : Boolean := False) + is + pragma Warnings (GNATprove, Off, "unused assignment to ""Ignored_S"""); + Ignored_S : Boolean; + begin + Mailbox_Write (MBox, Command, Wait_Ready, False, Ignored_S); + end Mailbox_Write; + +end HW.GFX.GMA.PCode; diff --git a/common/hw-gfx-gma-pcode.ads b/common/hw-gfx-gma-pcode.ads new file mode 100644 index 0000000..ef2564a --- /dev/null +++ b/common/hw-gfx-gma-pcode.ads @@ -0,0 +1,60 @@ +-- +-- Copyright (C) 2016, 2019 secunet Security Networks AG +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA.Registers; + +private package HW.GFX.GMA.PCode is + + -- We have to ensure that previous usage of the mailbox finished + -- (Wait_Ready) or know that we already did so (Mailbox_Ready). + -- + -- If we wait for the other side to acknowledge (Wait_Ack), we + -- know that it's ready (=> Mailbox_Ready). + + -- XXX: Supposed to be a `Ghost` variable, but GNAT seems too broken? + Mailbox_Ready : Boolean with Part_Of => HW.GFX.GMA.State; + + -- Just send a command, discard the reply. + procedure Mailbox_Write + (MBox : in Word32; + Command : in Word64; + Wait_Ready : in Boolean := False; + Wait_Ack : in Boolean := True; + Success : out Boolean) + with + Pre => Mailbox_Ready or Wait_Ready, + Post => (if Wait_Ack and Success then Mailbox_Ready); + + -- Repeatedly send a request command the expected reply is received. + procedure Mailbox_Request + (MBox : in Word32; + Command : in Word64; + Reply_Mask : in Word64; + Reply : in Word64 := 16#ffff_ffff_ffff_ffff#; + TOut_MS : in Natural := Registers.Default_Timeout_MS; + Wait_Ready : in Boolean := False; + Success : out Boolean) + with + Pre => Mailbox_Ready or Wait_Ready, + Post => (if Success then Mailbox_Ready); + + -- For final mailbox commands that don't have to wait. + procedure Mailbox_Write + (MBox : Word32; + Command : Word64; + Wait_Ready : Boolean := False) + with + Pre => Mailbox_Ready or Wait_Ready; + +end HW.GFX.GMA.PCode; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 15d234a..dbdee5c 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -21,6 +21,7 @@ with HW.GFX.GMA.Config; with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.Registers; +with HW.GFX.GMA.PCode; with HW.GFX.GMA.Power_And_Clocks; with HW.GFX.GMA.Panel; with HW.GFX.GMA.PLLs; @@ -39,6 +40,7 @@ (State => (Dev.Address_State, Registers.Address_State, + PCode.Mailbox_Ready, PLLs.State, Panel.Panel_State, Cur_Configs, Allocated_PLLs, HPD_Delay, Wait_For_HPD, @@ -376,6 +378,7 @@ (Config.Variable, Dev.Address_State, Registers.Address_State, + PCode.Mailbox_Ready, PLLs.State, Panel.Panel_State, Cur_Configs, Allocated_PLLs, HPD_Delay, Wait_For_HPD, @@ -435,6 +438,7 @@ pragma Debug (Debug.Set_Register_Write_Delay (Write_Delay)); Linear_FB_Base := 0; + PCode.Mailbox_Ready := False; Wait_For_HPD := HPD_Type'(others => False); HPD_Delay := HPD_Delay_Type'(others => Now); Allocated_PLLs := (others => PLLs.Invalid); diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb index c6eb2cf..2ab7f21 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb @@ -18,6 +18,7 @@ with HW.Debug; with HW.GFX.GMA.Config; with HW.GFX.GMA.Registers; +with HW.GFX.GMA.PCode; with HW.GFX.GMA.Power_And_Clocks_Haswell; use type HW.Word64; @@ -86,8 +87,6 @@ SKL_CDCLK_PREPARE_FOR_CHANGE : constant := 3; SKL_CDCLK_READY_FOR_CHANGE : constant := 1; - GT_MAILBOX_READY : constant := 1 * 2 ** 31; - function CDCLK_CTL_CD_FREQ_DECIMAL (Freq : Pos16; Plus_Half : Boolean) @@ -98,22 +97,6 @@ ---------------------------------------------------------------------------- - procedure GT_Mailbox_Write (MBox : Word32; Value : Word64) is - begin - pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - - Registers.Wait_Unset_Mask (Registers.GT_MAILBOX, GT_MAILBOX_READY); - Registers.Write - (Registers.GT_MAILBOX_DATA, Word32 (Value and 16#ffff_ffff#)); - Registers.Write - (Registers.GT_MAILBOX_DATA_1, Word32 (Shift_Right (Value, 32))); - Registers.Write (Registers.GT_MAILBOX, GT_MAILBOX_READY or MBox); - - Registers.Wait_Unset_Mask (Registers.GT_MAILBOX, GT_MAILBOX_READY); - end GT_Mailbox_Write; - - ---------------------------------------------------------------------------- - procedure PD_Off (PD : Power_Domain) is Ctl1, Ctl2, Ctl3, Ctl4 : Word32; @@ -251,10 +234,7 @@ procedure Initialize is - CDClk_Change_Timeout : Time.T; - Timed_Out : Boolean; - - MBox_Data0 : Word32; + Success : Boolean; begin Registers.Set_Mask (Register => Registers.NDE_RSTWRN_OPT, @@ -282,29 +262,20 @@ (Register => Registers.LCPLL1_CTL, Mask => LCPLL1_CTL_PLL_LOCK); - CDClk_Change_Timeout := Time.MS_From_Now (3); - Timed_Out := False; - loop - GT_Mailbox_Write - (MBox => SKL_PCODE_CDCLK_CONTROL, - Value => SKL_CDCLK_PREPARE_FOR_CHANGE); - Registers.Read (Registers.GT_MAILBOX_DATA, MBox_Data0); - if (MBox_Data0 and SKL_CDCLK_READY_FOR_CHANGE) /= 0 then - -- Ignore timeout if we succeeded anyway. - Timed_Out := False; - exit; - end if; - exit when Timed_Out; + PCode.Mailbox_Request + (MBox => SKL_PCODE_CDCLK_CONTROL, + Command => SKL_CDCLK_PREPARE_FOR_CHANGE, + Reply_Mask => SKL_CDCLK_READY_FOR_CHANGE, + Wait_Ready => True, + Success => Success); - Timed_Out := Time.Timed_Out (CDClk_Change_Timeout); - end loop; - pragma Debug (Timed_Out, Debug.Put_Line - ("ERROR: PCODE not ready for frequency change after 3ms.")); + pragma Debug (not Success, Debug.Put_Line + ("ERROR: PCODE not ready for frequency change.")); - if not Timed_Out then - GT_Mailbox_Write + if Success then + PCode.Mailbox_Write (MBox => SKL_PCODE_CDCLK_CONTROL, - Value => 16#0000_0000#); -- 0 - 337.5MHz + Command => 16#0000_0000#); -- 0 - 337.5MHz -- 1 - 450.0MHz -- 2 - 540.0MHz -- 3 - 675.0MHz -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I5daa3effb7ab774e4a35bd8794b0f67f57e4caa4 Gerrit-Change-Number: 35710 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019