coreboot-gerrit September 2019

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Change in ...coreboot[master]: device: Rename scan_static_bus() -> enable_static_devices()
by Nico Huber (Code Review) 07 Oct '19

07 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31900 Change subject: device: Rename scan_static_bus() -> enable_static_devices() ...................................................................... device: Rename scan_static_bus() -> enable_static_devices() The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/root_device.c M src/include/device/device.h M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/hda/hda.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31900/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index f8e2907..8f2d446 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -26,7 +26,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; /** - * Scan devices on static buses. + * Enable devices on static buses. * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time @@ -43,7 +43,7 @@ * @param bus Pointer to the device to which the static buses are attached to. */ -void scan_static_bus(struct device *bus) +void enable_static_devices(struct device *bus) { struct device *child; struct bus *link; @@ -67,7 +67,7 @@ { printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } @@ -78,7 +78,7 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); /* Scan bridges in case this device is a hub */ for (link = bus->link_list; link; link = link->next) @@ -136,7 +136,7 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); for (link = bus->link_list; link; link = link->next) scan_bridges(link); diff --git a/src/include/device/device.h b/src/include/device/device.h index 2e2cda9..cbee197 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -278,9 +278,9 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); +void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); -void scan_static_bus(struct device *bus); void scan_lpc_bus(struct device *bus); void scan_usb_bus(struct device *bus); diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 2bd6599..7f7eb90 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -23,7 +23,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 8ab835e..c1426e0 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -69,7 +69,7 @@ .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Gerrit-Change-Number: 31900 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/facebook/fbg1701: Enable display of logo
by Frans Hendriks (Code Review) 07 Oct '19

07 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34402 ) Change subject: mainboard/facebook/fbg1701: Enable display of logo ...................................................................... mainboard/facebook/fbg1701: Enable display of logo Specify FSP1_1_LOGO_FILE_NAME and enable display of logo. BUG=N/A TEST=Display is displayed on Facebook FBG1701 Change-Id: I24c6fcd829aa45c1b194f6ae273a20526aa89943 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34402/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 95d8f6c..ada5f2a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -76,7 +76,13 @@ config FSP1_1_DISPLAY_LOGO bool - default n + default y + +config FSP1_1_LOGO_FILE_NAME + string + depends on FSP1_1_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/34402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c6fcd829aa45c1b194f6ae273a20526aa89943 Gerrit-Change-Number: 34402 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo
by Frans Hendriks (Code Review) 07 Oct '19

07 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34401 ) Change subject: 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo ...................................................................... 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo Use blobs version with logo file BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I926e998745556de9ae913b4b7a6cde8b3ddb4bcf Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34401/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd..ab91bf0 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit ab91bf059215318373f5a2d29f28a603b4139359 -- To view, visit https://review.coreboot.org/c/coreboot/+/34401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926e998745556de9ae913b4b7a6cde8b3ddb4bcf Gerrit-Change-Number: 34401 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/monolake: Add GPIO table and initialize
by Jingle Hsu (Code Review) 07 Oct '19

07 Oct '19

Jingle Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35367 ) Change subject: mb/ocp/monolake: Add GPIO table and initialize ...................................................................... mb/ocp/monolake: Add GPIO table and initialize Add GPIO table for Monolake to initialize GPIOs. Tested on Monolake Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/1 diff --git a/src/mainboard/ocp/monolake/gpio.h b/src/mainboard/ocp/monolake/gpio.h new file mode 100644 index 0000000..982daa4 --- /dev/null +++ b/src/mainboard/ocp/monolake/gpio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#ifndef MONOLAKE_GPIO_H +#define MONOLAKE_GPIO_H + +static const struct gpio_config gpio_tables[] = { + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + +#endif diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..d7f2c3a 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +#include "gpio.h" /* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -59,6 +61,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/35367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Gerrit-Change-Number: 35367 Gerrit-PatchSet: 1 Gerrit-Owner: Jingle Hsu Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[...
by Peter Lemenkov (Code Review) 06 Oct '19

06 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35449 ) Change subject: mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[01] variables ...................................................................... mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[01] variables Change-Id: I330e5b5ff352668a8847d1e4646f4ef5be6a806f Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/platform.asl 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35449/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..167fe03 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..21d8115 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/35449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I330e5b5ff352668a8847d1e4646f4ef5be6a806f Gerrit-Change-Number: 35449 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] Give `lenovo_serial` EEPROMs a name in dt
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35457 ) Change subject: [WIP] Give `lenovo_serial` EEPROMs a name in dt ...................................................................... [WIP] Give `lenovo_serial` EEPROMs a name in dt Change-Id: I99edb7a8428ac7efa275fa09a10ec051b0f9abd3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/mainboard/lenovo/x200/devicetree.cb 2 files changed, 13 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35457/1 diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 0a6b343..3464e4a 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -20,17 +20,22 @@ #include <smbios.h> #include <console/console.h> #include <version.h> +#include <static.h> #include "lenovo.h" #define ERROR_STRING "*INVALID*" static struct device *at24rf08c_find_bank(u8 bank) { - struct device *dev; - dev = dev_find_slot_on_smbus(1, 0x54 | bank); - if (!dev) - printk(BIOS_WARNING, "EEPROM not found\n"); - return dev; + switch (bank) { + case 0: + return &__static_lenovo_serial0; + case 2: + return &__static_lenovo_serial2; + default: + die("%s: Unknown EEPROM bank number.\n", __func__); + return NULL; + } } static int at24rf08c_read_byte(struct device *dev, u8 addr) @@ -134,14 +139,7 @@ memset(result, 0, sizeof (result)); - dev = dev_find_slot_on_smbus(1, 0x56); - if (dev == NULL) { - printk(BIOS_WARNING, "EEPROM not found\n"); - already_read = 1; - memset(uuid, 0, 16); - return; - } - + dev = at24rf08c_find_bank(2); for (i = 0; i < 16; i++) { int t; int j; diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 2ed4308..5ff5d52 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -215,9 +215,9 @@ ioapic_irq 2 INTC 0x12 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c - device i2c 54 on end + device i2c 54 as lenovo_serial0 on end device i2c 55 on end - device i2c 56 on end + device i2c 56 as lenovo_serial2 on end device i2c 57 on end device i2c 5c on end device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/35457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99edb7a8428ac7efa275fa09a10ec051b0f9abd3 Gerrit-Change-Number: 35457 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE] soc/intel exit_car.S
by Kyösti Mälkki (Code Review) 06 Oct '19

06 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35187 ) Change subject: [NOTFORMERGE] soc/intel exit_car.S ...................................................................... [NOTFORMERGE] soc/intel exit_car.S Change-Id: Icd369029d9bbf0aa72923513952e1aacf88c0f40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/exit_car.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car.S 6 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35187/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 769a758..8ae7a66 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -34,6 +34,7 @@ call gdt_init /* chipset_teardown_car() is expected to disable cache-as-ram. */ + /* ..... */ call chipset_teardown_car /* Enable caching if not already enabled. */ @@ -42,6 +43,7 @@ mov %eax, %cr0 /* Ensure cache is clean. */ + /* ..... */ invd /* Set up new stack. */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 8adc5f6..ee71d81 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -29,6 +29,7 @@ post_code(0x30) /* Disable cache. */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 3b99128..ba57546 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -27,6 +27,7 @@ post_code(0x30) /* Disable cache. */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f0bb3f..37dfd3f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -131,6 +131,7 @@ #endif /* Disable cache */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index f9d056e..9a36df0 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -23,6 +23,7 @@ pop %esp /* Disable cache */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index ab7886c..8aa8bfb 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -44,6 +44,10 @@ */ pop %ebx + + /* Disable cache ??? */ + + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr @@ -55,6 +59,7 @@ car_nem_teardown: /* invalidate cache contents. */ + /* maybe redundant ? */ invd /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ @@ -69,6 +74,8 @@ .global car_cqos_teardown car_cqos_teardown: + /* inconsistent, no invd here */ + /* Go back to all-evicting mode, set both masks to all-1s */ mov $MSR_L2_QOS_MASK(0), %ecx rdmsr @@ -91,6 +98,7 @@ car_nem_enhanced_teardown: /* invalidate cache contents. */ + /* maybe redundant ? */ invd /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd369029d9bbf0aa72923513952e1aacf88c0f40 Gerrit-Change-Number: 35187 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: sb/intel/ibexpeak: Remove handled RCBA entries from replay
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35440 ) Change subject: sb/intel/ibexpeak: Remove handled RCBA entries from replay ...................................................................... sb/intel/ibexpeak: Remove handled RCBA entries from replay The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 4 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35440/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 9d98637..df591cd 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,22 +66,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -120,8 +104,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a426d89..644c1c2 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,22 +61,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -116,8 +100,8 @@ unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Gerrit-Change-Number: 35440 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: sb/intel/ibexpeak: Add CIR initialization
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35439 ) Change subject: sb/intel/ibexpeak: Add CIR initialization ...................................................................... sb/intel/ibexpeak: Add CIR initialization This properly the chipset initialization registers. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 112 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3a06a8c..9d98637 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,21 +66,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -135,8 +120,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } } @@ -186,6 +171,8 @@ setup_pch_gpios(&mainboard_gpio_map); + pch_setup_cir(NEHALEM_MOBILE); + /* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5a4a9f1..a426d89 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,21 +61,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -131,8 +116,8 @@ unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } } @@ -181,6 +166,8 @@ setup_pch_gpios(&mainboard_gpio_map); + pch_setup_cir(NEHALEM_MOBILE); + /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f..97565d6 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c endif diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000..5628bc5 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include "pch.h" + +/* This set up magic Chipset Initialization Registers */ + +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization registers\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + + RCBA32(CIR7) = 0xf; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff7ffff, 0x600000); + break; + } + + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8fdf80; + RCBA32(CIR18) = 0; /* Does not match EDS */ + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x6002000; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x20000; + + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfffff; + RCBA32(CIR15) = 0x7f8fdfff; + RCBA32(CIR17) = 0x3900; + RCBA32(CIR19) = 0x10000; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x6000008; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x10000; + } else { + die("unsupported CPU!\n"); + } +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index ee0f9ad..bc194ac 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type); #ifndef __ROMCC__ #include <device/device.h> @@ -104,6 +105,9 @@ #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) +#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -352,6 +356,22 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 +#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4 + #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) -- To view, visit https://review.coreboot.org/c/coreboot/+/35439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Gerrit-Change-Number: 35439 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 22

Change in libgfxinit[master]: gma i2c: Increase timeout, again
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35450 ) Change subject: gma i2c: Increase timeout, again ...................................................................... gma i2c: Increase timeout, again Can a timeout be long enough? We still face the same problem as in 68f439d4f1 (gma i2c: Increase timeout to >100ms). User reports have shown, that the 110ms still were not enough, 200ms would be but to be safe this time, increase the timeout to 500ms. That may result in very long delays, but only if the hardware is even more broken that what we encountered so far. Change-Id: Ia7b28f5a4ed1cd382a7ebfba5ce1ffe1b7a333a8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-gma-i2c.adb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/50/35450/1 diff --git a/common/hw-gfx-gma-i2c.adb b/common/hw-gfx-gma-i2c.adb index bc81734..73f95de 100644 --- a/common/hw-gfx-gma-i2c.adb +++ b/common/hw-gfx-gma-i2c.adb @@ -225,7 +225,7 @@ Registers.Wait_Set_Mask (Register => GMBUS_Regs (2), Mask => GMBUS2_HARDWARE_READY, - TOut_MS => 110); + TOut_MS => 500); Registers.Read (GMBUS_Regs (2), GMBUS2); Success := (GMBUS2 and GMBUS2_HARDWARE_READY) /= 0 and -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ia7b28f5a4ed1cd382a7ebfba5ce1ffe1b7a333a8 Gerrit-Change-Number: 35450 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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