Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35547 )
Change subject: mb/supermicro/x11-lga1151-series: completely rework documentation
......................................................................
mb/supermicro/x11-lga1151-series: completely rework documentation
This completely reworks the documentation for both boards of the series
and moves common stuff to the series documentation.
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c
---
D Documentation/mainboard/supermicro/x11-lga1151-series/index.md
A Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md
4 files changed, 149 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35547/1
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md
deleted file mode 100644
index 63b730c..0000000
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md
+++ /dev/null
@@ -1,8 +0,0 @@
-# X11 LGA1151 series
-
-The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor
-differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE,
-IPMI etc. This is why those boards are grouped as "X11 LGA1151 series".
-
-- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
-- [X11SSM-F](x11ssm-f/x11ssm-f.md)
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
new file mode 100644
index 0000000..21685a8
--- /dev/null
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -0,0 +1,62 @@
+# X11 LGA1151 series
+
+The [Supermicro X11 LGA1151 series] are mostly the same boards with some minor differences in
+internal and external interfaces like available PCIe slots, NICs (1 GbE, 10 GbE), IPMI, RAID
+Controller etc.
+
+## Supported boards
+
+- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
+- [X11SSM-F](x11ssm-f/x11ssm-f.md)
+
+## Required proprietary blobs
+
+- [Intel FSP2.0]
+- Intel ME
+
+## De-blobbing
+
+- [Intel FSP2.0] can not be removed as long as there is no free replacement
+- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
+- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not
+ needed. For more details refer to the respective datasheet (e.g 333016-008 for I210).
+- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC]
+
+## Flashing coreboot
+
+Look at the [flashing tutorial] and the board-specific section.
+
+## Known issues
+
+These issues apply to all boards. Have a look at the board-specific issues, too.
+
+- Intel SGX causes secondary APs to crash (disabled for now) when HT is enabled
+- TianoCore doesn't work with Aspeed NGI, as it's text mode only
+
+## ToDo
+
+- Fix issues above
+- Fix issues in board specific sections
+- Fix TODOs mentioned in code
+- Add more boards! :-)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU | Intel Kaby Lake |
++------------------+--------------------------------------------------+
+| PCH | Intel C232/C236 |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel SPS (server version of the ME) |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
+[OpenBMC]: https://www.openbmc.org/
+[flashrom]: https://flashrom.org/Flashrom
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
index 79e7f3e..30400e0 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
@@ -2,46 +2,40 @@
This section details how to run coreboot on the [Supermicro X11SSH-TF].
-## Required proprietary blobs
-
-* [Intel FSP2.0]
-* Intel ME
-
## Flashing coreboot
-The board can be flashed externally using *some* programmers.
-The CH341 was found working, while Dediprog won't detect the chip.
-
-For more details have a look at the [flashing tutorial].
+The board can be flashed externally using *some* programmers. The CH341 was found working, while
+Dediprog didn't detect the chip.
The flash IC can be found between the two PCIe slots near the southbridge:
![](x11ssh-tf_flash.jpg)
## BMC (IPMI)
-This board has an ASPEED [AST2400], which has BMC functionality. The
-BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the
-mainboard near the [AST2400]. This chip is an [MX25L25635F].
+This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a
+32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This chip is an
+[MX25L25635F].
## Known issues
-- Intel SGX causes secondary APs to crash (disabled for now).
-- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
-- SMBus / I2C does not work (interrupt timeout)
+See general issue section.
+
+## ToDo
+
+- Fix TODOs mentioned in code
## Tested and working
- USB ports
-- M.2 2280 NVMe slot
-- 2x 10GB Ethernet
-- SATA
-- RS232
-- VGA on Aspeed
-- Super I/O initialisation
+- Ethernet
+- SATA ports
+- RS232 external
- ECC DRAM detection
- PCIe slots
-- TPM on TPM expansion header
+- M.2 2280 NVMe slot
- BMC (IPMI)
+- VGA on Aspeed
+- TPM on TPM expansion header
## Technology
@@ -51,23 +45,45 @@
+------------------+--------------------------------------------------+
| PCH | Intel C236 |
+------------------+--------------------------------------------------+
-| Super I/O | ASPEED AST2400 |
-+------------------+--------------------------------------------------+
| Coprocessor | Intel SPS (server version of the ME) |
+------------------+--------------------------------------------------+
-| Coprocessor | ASPEED AST2400 |
+| Super I/O | ASPEED AST2400 |
++------------------+--------------------------------------------------+
+| Ethernet | 2x Intel® X550 10GBase-T Ethernet |
+| | 1x dedicated BMC |
++------------------+--------------------------------------------------+
+| PCIe slots | 1x 3.0 x8 |
+| | 1x 3.0 x2 (in x4) |
+| | 1x 3.0 M.2 2260 x4 (Key M, with S-ATA) |
++------------------+--------------------------------------------------+
+| USB slots | 2x USB 2.0 (ext) |
+| | 2x USB 3.0 (ext) |
+| | 1x USB 3.0 (int) |
+| | 1x dual USB 3.0 header |
+| | 2x dual USB 2.0 header |
++------------------+--------------------------------------------------+
+| SATA slots | 8x SATA III |
++------------------+--------------------------------------------------+
+| Other slots | 1x RS232 (ext) |
+| | 1x RS232 header |
+| | 1x TPM header |
+| | 1x Power SMB header |
+| | 6x PWM Fan connector |
+| | 2x I-SGPIO |
+| | 2x S-ATA DOM Power connector |
+| | 1x XDP Port |
+| | 1x External BMC I2C Header (for IPMI card) |
+| | 1x Chassis Intrusion Header |
+------------------+--------------------------------------------------+
```
## Extra links
+- [Supermicro X11SSH-TF]
- [Board manual]
-[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/…
-[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
-[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
-[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md
index c39de36..913d58e 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md
@@ -2,51 +2,28 @@
This section details how to run coreboot on the [Supermicro X11SSM-F].
-## Required proprietary blobs
-
-* [Intel FSP2.0]
-* Intel ME
-
-## De-blobbing
-
-* [Intel FSP2.0] can not be removed as long as there is no free replacement
-* Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
-* Intel Ethernet Controller I210 Firmware can be removed when it's extended
- functionality is not needed. For more details refer to Intel document
- 333016-008.
-* BMC/IPMI Firmware can be replaced by OpenBMC
-
## Flashing coreboot
-The board can be flashed externally using *some* programmers.
-FTDI FT2232H and FT232H based programmers worked.
-
-For more details have a look at the [flashing tutorial].
+The board can be flashed externally using *some* programmers. FTDI FT2232H and FT232H based
+programmers worked.
The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4.
## BMC (IPMI)
-This board has an ASPEED [AST2400], which has BMC functionality. The
-BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the
-mainboard near the PCH PCIe Slot 4. This chip is an [MX25L25635F].
+This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a
+32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a
+[MX25L25635F].
## Known issues
-- Intel SGX causes secondary APs to crash (disabled for now).
-- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
-- SATA Hotplug does not work
-- SMBus / I2C does not work (interrupt timeout)
- P2SB / 1f.1 hidden access error
- "only partially covers this bridge" error
- LNXTHERM missing (acpi, src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl maybe?)
-- Error no CMOS option 'power_on_after_fail'
- PCI function 4 swapped to 0 (huh?)
- PCI function 2 swapped to 0 (huh?)
- register differences to vendor firmare:
- BIOS_PCI_EXP_EN 1->0
- - ETR3_CF9LOCK 1->0
- - HOT_PLUG_EN 1->0 (fsp pcie hotplug?)
- PCI_EXP_EN 1->0
- GPIO_TIER2_SCI_EN 1->0
@@ -60,17 +37,16 @@
## Tested and working
- USB ports
-- 2x GbE
-- SATA
-- RS232
-- Super I/O initialisation
+- Ethernet
+- SATA ports
+- RS232 external
- ECC DRAM detection
- PCIe slots
- BMC (IPMI)
+- VGA on Aspeed
## Not tested yet
-- VGA on Aspeed
- TPM on TPM expansion header
## Technology
@@ -81,23 +57,47 @@
+------------------+--------------------------------------------------+
| PCH | Intel C236 |
+------------------+--------------------------------------------------+
-| Super I/O | ASPEED AST2400 |
-+------------------+--------------------------------------------------+
| Coprocessor | Intel SPS (server version of the ME) |
+------------------+--------------------------------------------------+
-| Coprocessor | ASPEED AST2400 |
+| Super I/O | ASPEED AST2400 |
++------------------+--------------------------------------------------+
+| Ethernet | 2x Intel I210-AT 1 GbE |
+| | 1x dedicated BMC |
++------------------+--------------------------------------------------+
+| PCIe slots | 1x 3.0 x8 |
+| | 1x 3.0 x8 (in x16) |
+| | 2x 3.0 x4 (in x8) |
++------------------+--------------------------------------------------+
+| USB slots | 2x USB 2.0 (ext) |
+| | 2x USB 3.0 (ext) |
+| | 1x USB 3.0 (int) |
+| | 1x dual USB 3.0 header |
+| | 2x dual USB 2.0 header |
++------------------+--------------------------------------------------+
+| SATA slots | 8x S-ATA III |
++------------------+--------------------------------------------------+
+| Other slots | 1x RS232 (ext) |
+| | 1x RS232 header |
+| | 1x TPM header |
+| | 1x Power SMB header |
+| | 5x PWM Fan connector |
+| | 2x I-SGPIO |
+| | 2x S-ATA DOM Power connector |
+| | 1x XDP Port |
+| | 1x External BMC I2C Header (for IPMI card) |
+| | 1x Chassis Intrusion Header |
+------------------+--------------------------------------------------+
```
## Extra links
+- [Supermicro X11SSM-F]
- [Board manual]
+- [Log dumps]
-[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F
[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1785.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
[MX25L12873F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L12873F.pdf
-[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
-[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
-[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F
+[Log dumps]: log_dumps.tgz
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c
Gerrit-Change-Number: 35547
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner
Gerrit-MessageType: newchange
Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35455 )
Change subject: config: provide a way to specify a user override devicetree
......................................................................
config: provide a way to specify a user override devicetree
Change-Id: Ie4652cbf59ba6ba03f97a75ca4644349ffa04915
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M Makefile.inc
M src/Kconfig
2 files changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/35455/1
diff --git a/Makefile.inc b/Makefile.inc
index 3c3088d..7b7954d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -26,6 +26,7 @@
CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE))
CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE))
CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE))
+CONFIG_USER_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_USER_OVERRIDE_DEVICETREE))
#######################################################################
# misleadingly named, this is the coreboot version
@@ -590,12 +591,23 @@
endif
+ifneq ($(CONFIG_USER_OVERRIDE_DEVICETREE),)
+
+USER_OVERRIDE_DEVICETREE_FILE := $(CONFIG_USER_OVERRIDE_DEVICETREE)
+
+# check/convert absolute/relative path
+ifeq ($(call substr,$(USER_OVERRIDE_DEVICETREE_FILE),1,1),/)
+USER_OVERRIDE_DEVICETREE_FILE := $(src)/$(USER_OVERRIDE_DEVICETREE_FILE)
+endif
+
+endif
+
DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c
-$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
+$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(USER_OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
@printf " SCONFIG $(subst $(src)/,,$(<))\n"
mkdir -p $(dir $(DEVICETREE_STATIC_C))
- $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE)
+ $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE) $(USER_OVERRIDE_DEVICETREE_FILE)
ramstage-y+=$(DEVICETREE_STATIC_C)
romstage-y+=$(DEVICETREE_STATIC_C)
diff --git a/src/Kconfig b/src/Kconfig
index a1c016e..427e009 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -346,6 +346,17 @@
Examples: "devicetree.variant-override.cb"
"variant/devicetree-override.cb"
+config USER_OVERRIDE_DEVICETREE
+ string
+ default ""
+ help
+ This symbol allows to provide an additional override devicetree file to
+ override the registers and/or add new devices on top of the ones
+ provided by the devicetree using DEVICETREE and/or OVERRIDE_DEVICETREE.
+
+ Examples: "relative/path/to/devicetree-override.cb"
+ "/abolute/path/to/devicetree-override.cb"
+
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
# Default value set at the end of the file
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie4652cbf59ba6ba03f97a75ca4644349ffa04915
Gerrit-Change-Number: 35455
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner
Gerrit-MessageType: newchange