coreboot-gerrit September 2019

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Change in coreboot[master]: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage
by Arthur Heymans (Code Review) 09 Oct '19

09 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34978 ) Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ...................................................................... sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage This is now done during the romstage. Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34978/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bd3c993..0036bb1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -458,18 +458,6 @@ RCBA32_OR(LCTL, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; @@ -681,7 +669,6 @@ static void pch_lpc_enable_resources(struct device *dev) { - pch_decode_init(dev); return pci_dev_enable_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: acpi_table_header: Replace hard-code length via sizeof(acpi_fadt_t)
by Name of user not set (Code Review) 09 Oct '19

09 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35540 ) Change subject: acpi_table_header: Replace hard-code length via sizeof(acpi_fadt_t) ...................................................................... acpi_table_header: Replace hard-code length via sizeof(acpi_fadt_t) Minimize use of hard code value for acpi_table_header->length to soft code. Replace length of acpi_header_t with sizeof(acpi_fadt_t). Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/mainboard/amd/serengeti_cheetah_fam10/fadt.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/intel/i82371eb/fadt.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35540/1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 845af71..9f6d48c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -35,7 +35,7 @@ /* Prepare the header */ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index 4a5746c..c81e644 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -36,7 +36,7 @@ /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c index 71bdf23..acda6db 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -36,7 +36,7 @@ /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 26a1570..9e43e62 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -38,7 +38,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/35540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38 Gerrit-Change-Number: 35540 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp
by Bora Guvendik (Code Review) 09 Oct '19

09 Oct '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33746 Change subject: [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp ...................................................................... [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33746/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..8e362c1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -62,6 +62,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP + select FSP_USES_CB_STACK select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -120,6 +121,7 @@ config DCACHE_BSP_STACK_SIZE hex + default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and -- To view, visit https://review.coreboot.org/c/coreboot/+/33746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6 Gerrit-Change-Number: 33746 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: WIP: Change to use the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 09 Oct '19

09 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35646 ) Change subject: WIP: Change to use the shared 'dramc_param' module ...................................................................... WIP: Change to use the shared 'dramc_param' module A demonstration for how to use the dramc_param module shared with mtk-dramk blob. Change-Id: I611490f00a5507caded7321dfc0359fcdf10e4e0 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/emi.h 5 files changed, 151 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35646/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index cc1def7..f2dd4e4 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -18,22 +18,22 @@ #include <cbfs.h> #include <console/console.h> #include <fmap.h> +#include <soc/dramc_param.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <string.h> #include "early_init.h" -struct params_data calibration_results; - #define CALIBRATION_REGION "RW_DDR_TRAINING" + static bool read_calibration_data_from_flash(void *data, size_t length) { size_t ret = fmap_read_area(CALIBRATION_REGION, data, length); - printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", - __func__, ret, length); + printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); return ret == length; } @@ -47,25 +47,16 @@ return ret == length; } +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dparam; + void clean_calibration_data(void) { - size_t ret; - struct params_data *params_result = &calibration_results; - size_t length = sizeof(calibration_results); - - if (read_calibration_data_from_flash(params_result, length) && - have_calibration_params(params_result->freq_params)) { - /* reset all params to 0 */ - memset(params_result, 0x0, length); - - ret = fmap_overwrite_area(CALIBRATION_REGION, - params_result, length); - printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", - __func__, ret, length); - } + dparam.header.status = DRAMC_ERR_RECALIBRATE; + fmap_overwrite_area(CALIBRATION_REGION, &dparam, sizeof(dparam)); } -static int dram_run_full_calibration(struct params_data *params_result) +static int dram_run_full_calibration(struct dramc_param *param) { /* Load and run the provided blob for full-calibration if available */ struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); @@ -76,10 +67,9 @@ if (cbfs_prog_stage_load(&dram)) return -2; - prog_set_entry(&dram, prog_entry(&dram), params_result); + prog_set_entry(&dram, prog_entry(&dram), param); prog_run(&dram); - - return 0; + return param->header.status == DRAMC_SUCCESS; } static void init_sdram_params(struct sdram_params *dst, @@ -92,30 +82,28 @@ static void dram_initialize(void) { - u16 is_emcp = 0; - struct params_data *params_result = &calibration_results; - size_t length = sizeof(calibration_results); - struct sdram_params *freq_params = params_result->freq_params; + struct sdram_params *freq_params = &dparam.freq_params[0]; - if (!read_calibration_data_from_flash(params_result, length) && - (params_result->param_header.pl_version != PARAM_PL_VERSION)) { + u32 flags = 0; + if (CONFIG(MT8183_DRAM_EMCP)) + flags |= DRAMC_FLAG_HAS_EMCP; - /* EMCP devices should run 3600Mbps for high frequency calibartion */ - is_emcp = CONFIG(MT8183_DRAM_EMCP) ? PARAM_EMCP_MAGIC : 0; - params_result->param_header.is_emcp = is_emcp; - printk(BIOS_INFO, "is_emcp current DDR type is %s\n", - (is_emcp == PARAM_EMCP_MAGIC) ? "EMCP" : "Discrete"); - /* try to re-run DRAM full calibration if avalible */ - int err = dram_run_full_calibration(params_result); + if (!read_calibration_data_from_flash(&dparam, sizeof(dparam)) || + !is_valid_dramc_param(&dparam) || + dparam.header.flags != flags) { + + initialize_dramc_param(&dparam, flags); + /* try to re-run DRAM full calibration if available */ + int err = dram_run_full_calibration(&dparam); if (err == 0) { printk(BIOS_INFO, "successfully load dram_blob and " "run DRAM calibration\n"); - printk(BIOS_INFO, "save params to flash. pl_version: 0x%x, body_size: 0x%x\n", - params_result->param_header.pl_version, - params_result->param_header.body_size); + printk(BIOS_INFO, "save params to flash. pl_version: %#x, body_size: %#x\n", + dparam.header.version, + dparam.header.size); - write_calibration_data_to_flash(freq_params, length); + write_calibration_data_to_flash(&dparam, sizeof(dparam)); return; } @@ -124,11 +112,8 @@ /* init params setting from sdram configs if no have dram calibraion result */ init_sdram_params(freq_params, get_sdram_config()); - mt_mem_init(freq_params); - } else { - printk(BIOS_INFO, "have dram calibraion params\n"); - mt_mem_init(freq_params); } + mt_mem_init(freq_params); } void platform_romstage_main(void) diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b6c3a33..27591df 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_init_setting.c +romstage-y += dramc_param.c romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c new file mode 100644 index 0000000..31d71c7 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include "soc/dramc_param.h" + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = &param->header; + + if (hdr->magic != DRAMC_PARAM_HEADER_MAGIC) + return DRAMC_ERR_INVALID_MAGIC; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + /* TODO(hungte) Verify and check hdr->checksum. */ + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob, u32 flags) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = &param->header; + + memset(blob, 0, sizeof(*param)); + hdr->magic = DRAMC_PARAM_HEADER_MAGIC; + hdr->size = sizeof(*param); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->flags = flags; + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h new file mode 100644 index 0000000..aa8a4e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H +#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H + +#include <stdint.h> +#include <sys/types.h> + +#include "emi.h" + +enum { + DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, + DRAMC_PARAM_HEADER_VERSION = 1, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_MAGIC, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, +}; + +/* Bit flags. */ +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_EMCP = 0x0001, +}; + +struct dramc_param_header { + u32 status; /* DRAMC_PARAM_STATUS_CODES */ + u32 magic; + u32 version; + u32 size; /* size of whole dramc_param */ + u32 flags; /* DRAMC_PARAM_FLAGS */ + u32 checksum; +}; + +struct dramc_param { + struct dramc_param_header header; + struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob, u32 flags); + +#endif /* SOC_MEDIATEK_MT8183_DRAMC_PARAM_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index a4b9150..be10bf5 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -22,14 +22,6 @@ #define PARAM_START_PATTERN 0x5a5a #define PARAM_END_PATTERN 0x3c3c -#define PARAM_PL_VERSION 0x20190927 -#define PARAM_EMCP_MAGIC 0x5acc - -struct sdram_params_header { - u32 pl_version; - u16 is_emcp; - u16 body_size; -}; struct sdram_params { u16 calibration_result_start; @@ -77,11 +69,6 @@ u16 calibration_result_end; }; -struct params_data { - struct sdram_params_header param_header; - struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; -}; - enum { LP4X_DDR1600, LP4X_DDR2400, -- To view, visit https://review.coreboot.org/c/coreboot/+/35646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611490f00a5507caded7321dfc0359fcdf10e4e0 Gerrit-Change-Number: 35646 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/drallion: Update SD Card pci device
by Selma Bensaid (Code Review) 08 Oct '19

08 Oct '19

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35655 to review the following change. Change subject: mb/google/drallion: Update SD Card pci device ...................................................................... mb/google/drallion: Update SD Card pci device Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Icb96fe433014c905ebf896bdcb7d43cb57563313 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/35655/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d824a55..42310f5 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -399,9 +399,7 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 on end # PCI Express Port 12 -- To view, visit https://review.coreboot.org/c/coreboot/+/35655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb96fe433014c905ebf896bdcb7d43cb57563313 Gerrit-Change-Number: 35655 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: device/root_device: Consolidate common _scan_bus() functions
by Nico Huber (Code Review) 08 Oct '19

08 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31901 Change subject: device/root_device: Consolidate common _scan_bus() functions ...................................................................... device/root_device: Consolidate common _scan_bus() functions scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/root_device.c M src/drivers/usb/acpi/usb_acpi.c M src/include/device/device.h M src/soc/amd/stoneyridge/usb.c M src/soc/intel/common/block/xhci/xhci.c 5 files changed, 6 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31901/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index 8f2d446..2fae5c3 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -72,21 +72,6 @@ printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } -void scan_usb_bus(struct device *bus) -{ - struct bus *link; - - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - - enable_static_devices(bus); - - /* Scan bridges in case this device is a hub */ - for (link = bus->link_list; link; link = link->next) - scan_bridges(link); - - printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); -} - void scan_generic_bus(struct device *bus) { struct device *child; @@ -123,14 +108,7 @@ scan_generic_bus(bus); } -/** - * Scan root bus for generic systems. - * - * This function is the default scan_bus() method of the root device. - * - * @param root The root device structure. - */ -static void root_dev_scan_bus(struct device *bus) +void scan_static_bus(struct device *bus) { struct bus *link; @@ -169,7 +147,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = root_dev_scan_bus, + .scan_bus = scan_static_bus, .reset_bus = root_dev_reset, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = root_dev_acpi_name, diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8c63d2a..e026eeb 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -86,7 +86,7 @@ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_fill_ssdt_generator = usb_acpi_fill_ssdt_generator, }; diff --git a/src/include/device/device.h b/src/include/device/device.h index cbee197..02fb072 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -282,7 +282,7 @@ void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_lpc_bus(struct device *bus); -void scan_usb_bus(struct device *bus); +void scan_static_bus(struct device *bus); #endif /* !defined(__ROMCC__) */ diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index f2fa3ba..2eedd97 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -63,7 +63,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, .ops_pci = &lops_pci, }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index c429e7d..95315b2 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -28,7 +28,7 @@ .enable_resources = pci_dev_enable_resources, .init = soc_xhci_init, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Gerrit-Change-Number: 31901 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: src/device/dram/ddr4: Fix "Dead assignment"
by HAOUAS Elyes (Code Review) 08 Oct '19

08 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35558 ) Change subject: src/device/dram/ddr4: Fix "Dead assignment" ...................................................................... src/device/dram/ddr4: Fix "Dead assignment" The value stored to 'spd_bytes_total' is never read, so let use it to check if 'SPD Bytes Total' and/or 'SPD Bytes Used' are reserved. Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr4.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35558/1 diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 4f99ecc..472a771 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -120,6 +120,13 @@ } spd_bytes_total = 256 << (spd_bytes_total - 1); + + if (spd_bytes_total > 512) + printk(BIOS_WARNING, "SPD Bytes Total value is reserved\n"); + + if (spd_bytes_used > 4) + printk(BIOS_WARNING, "SPD Bytes Used value is reserved\n"); + spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; /* Verify CRC of blocks that have them, do not step over 'used' length */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Gerrit-Change-Number: 35558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: mb/lenovo/{t60,z61t}: Convert to variant board
by Peter Lemenkov (Code Review) 08 Oct '19

08 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34123 ) Change subject: mb/lenovo/{t60,z61t}: Convert to variant board ...................................................................... mb/lenovo/{t60,z61t}: Convert to variant board Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/t60/Kconfig.name M src/mainboard/lenovo/t60/board_info.txt A src/mainboard/lenovo/t60/variants/t60/board_info.txt R src/mainboard/lenovo/t60/variants/t60/data.vbt R src/mainboard/lenovo/t60/variants/t60/devicetree.cb R src/mainboard/lenovo/t60/variants/z61t/board_info.txt R src/mainboard/lenovo/t60/variants/z61t/data.vbt R src/mainboard/lenovo/t60/variants/z61t/devicetree.cb D src/mainboard/lenovo/z61t/Kconfig D src/mainboard/lenovo/z61t/Kconfig.name D src/mainboard/lenovo/z61t/Makefile.inc D src/mainboard/lenovo/z61t/acpi/dock.asl D src/mainboard/lenovo/z61t/acpi/ec.asl D src/mainboard/lenovo/z61t/acpi/gpe.asl D src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl D src/mainboard/lenovo/z61t/acpi/mainboard.asl D src/mainboard/lenovo/z61t/acpi/platform.asl D src/mainboard/lenovo/z61t/acpi/superio.asl D src/mainboard/lenovo/z61t/acpi/video.asl D src/mainboard/lenovo/z61t/acpi_tables.c D src/mainboard/lenovo/z61t/cmos.default D src/mainboard/lenovo/z61t/cmos.layout D src/mainboard/lenovo/z61t/dock.c D src/mainboard/lenovo/z61t/dock.h D src/mainboard/lenovo/z61t/dsdt.asl D src/mainboard/lenovo/z61t/gpio.c D src/mainboard/lenovo/z61t/hda_verb.c D src/mainboard/lenovo/z61t/mainboard.c D src/mainboard/lenovo/z61t/mptable.c D src/mainboard/lenovo/z61t/romstage.c D src/mainboard/lenovo/z61t/smi.h D src/mainboard/lenovo/z61t/smihandler.c D src/mainboard/lenovo/z61t/thermal.h 34 files changed, 32 insertions(+), 1,632 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34123/1 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index e4e87c9..02012f9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -1,7 +1,5 @@ -if BOARD_LENOVO_T60 - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_LENOVO_BASEBOARD_T60 + def_bool n select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 @@ -24,13 +22,25 @@ select I945_LVDS select INTEL_GMA_HAVE_VBT +if BOARD_LENOVO_BASEBOARD_T60 + config MAINBOARD_DIR string default lenovo/t60 +config VARIANT_DIR + string + default "t60" if BOARD_LENOVO_T60 + default "z61t" if BOARD_LENOVO_Z61T + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T60" + default "ThinkPad T60" if BOARD_LENOVO_T60 + default "ThinkPad Z61t" if BOARD_LENOVO_Z61T config MAX_CPUS int diff --git a/src/mainboard/lenovo/t60/Kconfig.name b/src/mainboard/lenovo/t60/Kconfig.name index f02fc3d..e38ed43 100644 --- a/src/mainboard/lenovo/t60/Kconfig.name +++ b/src/mainboard/lenovo/t60/Kconfig.name @@ -1,2 +1,7 @@ config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" + select BOARD_LENOVO_BASEBOARD_T60 + +config BOARD_LENOVO_Z61T + bool "ThinkPad Z61t" + select BOARD_LENOVO_BASEBOARD_T60 diff --git a/src/mainboard/lenovo/t60/board_info.txt b/src/mainboard/lenovo/t60/board_info.txt index 59ec88c..a636aa2 100644 --- a/src/mainboard/lenovo/t60/board_info.txt +++ b/src/mainboard/lenovo/t60/board_info.txt @@ -1,4 +1,5 @@ -Board name: T60/T60p +Vendor name: Lenovo +Board name: ThinkPad T60 baseboard Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t60/variants/t60/board_info.txt b/src/mainboard/lenovo/t60/variants/t60/board_info.txt new file mode 100644 index 0000000..9ba2f57 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Lenovo +Board name: ThinkPad T60/T60p +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/data.vbt b/src/mainboard/lenovo/t60/variants/t60/data.vbt similarity index 100% rename from src/mainboard/lenovo/t60/data.vbt rename to src/mainboard/lenovo/t60/variants/t60/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/variants/t60/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/t60/devicetree.cb rename to src/mainboard/lenovo/t60/variants/t60/devicetree.cb diff --git a/src/mainboard/lenovo/z61t/board_info.txt b/src/mainboard/lenovo/t60/variants/z61t/board_info.txt similarity index 70% rename from src/mainboard/lenovo/z61t/board_info.txt rename to src/mainboard/lenovo/t60/variants/z61t/board_info.txt index 310e100..c7c5643 100644 --- a/src/mainboard/lenovo/z61t/board_info.txt +++ b/src/mainboard/lenovo/t60/variants/z61t/board_info.txt @@ -1,4 +1,5 @@ -Board name: Z61t +Vendor name: Lenovo +Board name: ThinkPad Z61t Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/z61t/data.vbt b/src/mainboard/lenovo/t60/variants/z61t/data.vbt similarity index 100% rename from src/mainboard/lenovo/z61t/data.vbt rename to src/mainboard/lenovo/t60/variants/z61t/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/z61t/devicetree.cb rename to src/mainboard/lenovo/t60/variants/z61t/devicetree.cb diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig deleted file mode 100644 index de48d95..0000000 --- a/src/mainboard/lenovo/z61t/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -if BOARD_LENOVO_Z61T - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_M - select NORTHBRIDGE_INTEL_I945 - select NORTHBRIDGE_INTEL_SUBTYPE_I945GM - select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_NSC_PC87382 - select SUPERIO_NSC_PC87384 - select SOUTHBRIDGE_TI_PCI1X2X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select DRIVERS_I2C_CK505 - select HAVE_OPTION_TABLE - select INTEL_INT15 - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - select HAVE_ACPI_TABLES - select HAVE_ACPI_RESUME - select H8_DOCK_EARLY_INIT - select HAVE_CMOS_DEFAULT - select I945_LVDS - select INTEL_GMA_HAVE_VBT - -config MAINBOARD_DIR - string - default lenovo/z61t - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad Z61t" - -config MAX_CPUS - int - default 2 - -endif diff --git a/src/mainboard/lenovo/z61t/Kconfig.name b/src/mainboard/lenovo/z61t/Kconfig.name deleted file mode 100644 index a232857..0000000 --- a/src/mainboard/lenovo/z61t/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_Z61T - bool "ThinkPad Z61t" diff --git a/src/mainboard/lenovo/z61t/Makefile.inc b/src/mainboard/lenovo/z61t/Makefile.inc deleted file mode 100644 index 8473a13..0000000 --- a/src/mainboard/lenovo/z61t/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c -romstage-y += dock.c -romstage-y += gpio.c diff --git a/src/mainboard/lenovo/z61t/acpi/dock.asl b/src/mainboard/lenovo/z61t/acpi/dock.asl deleted file mode 100644 index 5085b29..0000000 --- a/src/mainboard/lenovo/z61t/acpi/dock.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "smi.h" - -Scope (\_SB) -{ - OperationRegion (DLPC, SystemIO, 0x164c, 1) - Field(DLPC, ByteAcc, NoLock, Preserve) - { - , 3, - DSTA, 1, - } - - Device(DOCK) - { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_DCK, 1, NotSerialized) - { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) - } - - Xor(Arg0, DSTA, Local0) - Return (Local0) - } - - Method(_STA, 0, NotSerialized) - { - Return (DSTA) - } - } -} - -Scope(\_SB.PCI0.LPCB.EC) -{ - OperationRegion(PMH7, SystemIO, 0x15e0, 0x10) - Field(PMH7, ByteAcc, NoLock, Preserve) - { - Offset(0x0c), - PIDX, 8, - Offset(0x0e), - PDAT, 8, - } - - IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) - { - Offset (0x61), - DPWR, 1, - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q37, 0, NotSerialized) - { - if (DPWR) { - Notify(\_SB.DOCK, 0) - } else { - Notify(\_SB.DOCK, 3) - } - } - - Method(_Q50, 0, NotSerialized) - { - if (\_SB.DOCK._STA()) { - Notify(\_SB.DOCK, 1) - } - } -} diff --git a/src/mainboard/lenovo/z61t/acpi/ec.asl b/src/mainboard/lenovo/z61t/acpi/ec.asl deleted file mode 100644 index fe7115a..0000000 --- a/src/mainboard/lenovo/z61t/acpi/ec.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/z61t/acpi/gpe.asl b/src/mainboard/lenovo/z61t/acpi/gpe.asl deleted file mode 100644 index 3cc25b2..0000000 --- a/src/mainboard/lenovo/z61t/acpi/gpe.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "smi.h" -Scope (\_GPE) -{ - Method(_L18, 0, NotSerialized) - { - /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) - } -} diff --git a/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl deleted file mode 100644 index 4c7c3a3..0000000 --- a/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * 0:1e.0 PCI bridge of the ICH7 - */ - -If (PICM) { - Return (Package() { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } - }) - } Else { - Return (Package() { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } - }) -} diff --git a/src/mainboard/lenovo/z61t/acpi/mainboard.asl b/src/mainboard/lenovo/z61t/acpi/mainboard.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/lenovo/z61t/acpi/mainboard.asl +++ /dev/null diff --git a/src/mainboard/lenovo/z61t/acpi/platform.asl b/src/mainboard/lenovo/z61t/acpi/platform.asl deleted file mode 100644 index f9e991b..0000000 --- a/src/mainboard/lenovo/z61t/acpi/platform.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - // CPU specific part - - // Notify PCI Express slots in case a card - // was inserted while a sleep state was active. - - // Are we going to S3? - If (LEqual(Arg0, 3)) { - // .. - } - - // Are we going to S4? - If (LEqual(Arg0, 4)) { - // .. - } - - // TODO: Windows XP SP2 P-State restore - - Return(Package(){0,0}) -} - -/* System Bus */ - -Scope(\_SB) -{ - /* This method is placed on the top level, so we can make sure it's the - * first executed _INI method. - */ - Method(_INI, 0) - { - /* The DTS data in NVS is probably not up to date. - * Update temperature values and make sure AP thermal - * interrupts can happen - */ - - // TRAP(71) // TODO - - \GOS() - - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - - /* SMM power state and C4-on-C3 settings need to be updated */ - // TRAP(43) // TODO - } -} diff --git a/src/mainboard/lenovo/z61t/acpi/superio.asl b/src/mainboard/lenovo/z61t/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/lenovo/z61t/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/lenovo/z61t/acpi/video.asl b/src/mainboard/lenovo/z61t/acpi/video.asl deleted file mode 100644 index 6db3a44..0000000 --- a/src/mainboard/lenovo/z61t/acpi/video.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "smi.h" - -Scope (\) -{ - Method(BRTD, 0, NotSerialized) - { - Trap(SMI_BRIGHTNESS_DOWN) - \_SB.PCI0.GFX0.DECB() - } - - Method(BRTU, 0, NotSerialized) - { - Trap(SMI_BRIGHTNESS_UP) - \_SB.PCI0.GFX0.INCB() - } -} diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c deleted file mode 100644 index bd10a0e..0000000 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <southbridge/intel/i82801gx/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/lenovo/z61t/cmos.default b/src/mainboard/lenovo/z61t/cmos.default deleted file mode 100644 index af865f1..0000000 --- a/src/mainboard/lenovo/z61t/cmos.default +++ /dev/null @@ -1,18 +0,0 @@ -boot_option=Fallback -debug_level=Debug -nmi=Enable -boot_devices='' -boot_default=0x41 -cmos_defaults_loaded=Yes -lpt=Enable -touchpad=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wlan=Enable -wwan=Enable -trackpoint=Enable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable -gfx_uma_size=8M diff --git a/src/mainboard/lenovo/z61t/cmos.layout b/src/mainboard/lenovo/z61t/cmos.layout deleted file mode 100644 index 75ad427..0000000 --- a/src/mainboard/lenovo/z61t/cmos.layout +++ /dev/null @@ -1,135 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007-2008 coresystems GmbH -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail - -# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - -# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 7 r 0 unused - -# coreboot config options: cpu -#945 3 r 0 unused - -# coreboot config options: ec -948 1 e 1 touchpad -949 1 e 1 bluetooth -950 1 e 1 wwan -951 1 e 1 wlan -952 8 h 0 volume -960 1 e 9 first_battery -961 1 e 1 trackpoint -#962 1 r 0 unused -963 1 e 1 sticky_fn -964 1 e 1 power_management_beeps -965 1 e 1 low_battery_beep - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M - -# ----------------------------------------------------------------- -checksums - -checksum 392 983 984 diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c deleted file mode 100644 index 05dd65e..0000000 --- a/src/mainboard/lenovo/z61t/dock.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <arch/io.h> -#include <delay.h> -#include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> -#include "ec/acpi/ec.h" -#include "ec/lenovo/pmh7/pmh7.h" -#include <southbridge/intel/i82801gx/i82801gx.h> - -#define DLPC_CONTROL 0x164c - -static void dlpc_write_register(int reg, int value) -{ - outb(reg, 0x164e); - outb(value, 0x164f); -} - -static u8 dlpc_read_register(int reg) -{ - outb(reg, 0x164e); - return inb(0x164f); -} - -static void dock_write_register(int reg, int value) -{ - outb(reg, 0x2e); - outb(value, 0x2f); -} - -static u8 dock_read_register(int reg) -{ - outb(reg, 0x2e); - return inb(0x2f); -} - -static void dlpc_gpio_set_mode(int port, int mode) -{ - dlpc_write_register(0xf0, port); - dlpc_write_register(0xf1, mode); -} - -static void dock_gpio_set_mode(int port, int mode, int irq) -{ - dock_write_register(0xf0, port); - dock_write_register(0xf1, mode); - dock_write_register(0xf2, irq); -} - -static void dlpc_gpio_init(void) -{ - /* Select GPIO module */ - dlpc_write_register(0x07, 0x07); - /* GPIO Base Address 0x1680 */ - dlpc_write_register(0x60, 0x16); - dlpc_write_register(0x61, 0x80); - - /* Activate GPIO */ - dlpc_write_register(0x30, 0x01); - - dlpc_gpio_set_mode(0x00, 3); - dlpc_gpio_set_mode(0x01, 3); - dlpc_gpio_set_mode(0x02, 0); - dlpc_gpio_set_mode(0x03, 3); - dlpc_gpio_set_mode(0x04, 4); - dlpc_gpio_set_mode(0x20, 4); - dlpc_gpio_set_mode(0x21, 4); - dlpc_gpio_set_mode(0x23, 4); -} - -int dlpc_init(void) -{ - int timeout = 1000; - - /* Enable 14.318MHz CLK on CLKIN */ - dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) - udelay(1000); - - if (!timeout) - return 1; - - /* Select DLPC module */ - dlpc_write_register(0x07, 0x19); - /* DLPC Base Address */ - dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); - dlpc_write_register(0x61, DLPC_CONTROL & 0xff); - /* Activate DLPC */ - dlpc_write_register(0x30, 0x01); - - /* Reset docking state */ - outb(0x00, DLPC_CONTROL); - - dlpc_gpio_init(); - return 0; -} - -static int dock_superio_init(void) -{ - int timeout = 1000; - /* startup 14.318MHz Clock */ - dock_write_register(0x29, 0xa0); - /* wait until clock is settled */ - while(!(dock_read_register(0x29) & 0x10) && timeout--) - udelay(1000); - - if (!timeout) - return 1; - - /* set GPIO pins to Serial/Parallel Port - * functions - */ - dock_write_register(0x22, 0xa9); - - /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); - dock_write_register(0x30, 0x01); - - dock_write_register(0x07, PC87384_GPIO); - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x20); - /* enable GPIO */ - dock_write_register(0x30, 0x01); - - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); - - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); - - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - - /* no GPIO events enabled for PORT0 */ - outb(0x00, 0x1622); - /* clear GPIO events on PORT0 */ - outb(0xff, 0x1623); - outb(0xff, 0x1624); - /* no GPIO events enabled for PORT1 */ - outb(0x00, 0x1626); - - /* clear GPIO events on PORT1*/ - outb(0xff, 0x1627); - outb(0x1F, 0x1628); - outb(0xfd, 0x1620); - return 0; -} - -int dock_connect(void) -{ - int timeout = 1000; - - outb(0x07, DLPC_CONTROL); - - timeout = 1000; - - while(!(inb(DLPC_CONTROL) & 8) && timeout--) - udelay(1000); - - if (!timeout) { - /* docking failed, disable DLPC switch */ - outb(0x00, DLPC_CONTROL); - dlpc_write_register(0x30, 0x00); - return 1; - } - - /* Assert D_PLTRST# */ - outb(0xfe, 0x1680); - udelay(1000); - /* Deassert D_PLTRST# */ - outb(0xff, 0x1680); - udelay(10000); - - return dock_superio_init(); -} - -void dock_disconnect(void) -{ - /* disconnect LPC bus */ - outb(0x00, DLPC_CONTROL); - /* Assert PLTRST and DLPCPD */ - outb(0xfc, 0x1680); -} - -int dock_present(void) -{ - return pmh7_register_read(0x61) & 1; -} - -int legacy_io_present(void) -{ - return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); -} - -void legacy_io_init(void) -{ - /* Enable Power for Ultrabay slot */ - pmh7_ultrabay_power_enable(1); - udelay(100000); - dock_superio_init(); -} diff --git a/src/mainboard/lenovo/z61t/dock.h b/src/mainboard/lenovo/z61t/dock.h deleted file mode 100644 index 6a9efc2..0000000 --- a/src/mainboard/lenovo/z61t/dock.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THINKPAD_X60_DOCK_H -#define THINKPAD_X60_DOCK_H - -int dock_connect(void); -void dock_disconnect(void); -int dock_present(void); -int dlpc_init(void); - -int legacy_io_present(void); -void legacy_io_init(void); -#endif diff --git a/src/mainboard/lenovo/z61t/dsdt.asl b/src/mainboard/lenovo/z61t/dsdt.asl deleted file mode 100644 index 8f8c47d..0000000 --- a/src/mainboard/lenovo/z61t/dsdt.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \BRTU -#define BRIGHTNESS_DOWN \BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20090419 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> - #include <southbridge/intel/common/acpi/platform.asl> - - // General Purpose Events - #include "acpi/gpe.asl" - - // mainboard specific devices - #include "acpi/mainboard.asl" - - Scope (\) - { - // backlight control, display switching, lid - #include "acpi/video.asl" - } - - #include <cpu/intel/speedstep/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/i945/acpi/i945.asl> - #include <southbridge/intel/i82801gx/acpi/ich7.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> - - // Dock support code - #include "acpi/dock.asl" -} diff --git a/src/mainboard/lenovo/z61t/gpio.c b/src/mainboard/lenovo/z61t/gpio.c deleted file mode 100644 index f220b2b..0000000 --- a/src/mainboard/lenovo/z61t/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/common/gpio.h> - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio1 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ - .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ - .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ - .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ - .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ - .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ - .gpio19 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ - .gpio26 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ - .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio1 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_OUTPUT, - .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio19 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_HIGH, - .gpio28 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ - .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ - .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ - .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ - .gpio48 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio48 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, -}; diff --git a/src/mainboard/lenovo/z61t/hda_verb.c b/src/mainboard/lenovo/z61t/hda_verb.c deleted file mode 100644 index 73eecf6..0000000 --- a/src/mainboard/lenovo/z61t/hda_verb.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ - 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(0x0, 0x17aa2025), - - AZALIA_PIN_CFG(0, 0x05, 0xc3014110), - AZALIA_PIN_CFG(0, 0x06, 0x4221401f), - AZALIA_PIN_CFG(0, 0x07, 0x591311f0), - AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), - AZALIA_PIN_CFG(0, 0x09, 0x41813021), - AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), - AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), - AZALIA_PIN_CFG(0, 0x17, 0x59931122), - AZALIA_PIN_CFG(0, 0x18, 0x41a19023), - AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -}; -const u32 pc_beep_verbs[0] = {}; -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c deleted file mode 100644 index 5f59946..0000000 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/device.h> -#include <ec/lenovo/pmh7/pmh7.h> -#include <ec/lenovo/h8/h8.h> -#include <ec/acpi/ec.h> -#include <northbridge/intel/i945/i945.h> -#include <southbridge/intel/i82801gx/chip.h> -#include <drivers/intel/gma/int15.h> -#include <arch/acpigen.h> - -#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT - -static acpi_cstate_t cst_entries[] = { - { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, - { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, - { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - -static void mainboard_init(struct device *dev) -{ - struct southbridge_intel_i82801gx_config *config; - struct device *idedev; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - PANEL, 3); - - /* If we're resuming from suspend, blink suspend LED */ - if (acpi_is_wakeup_s3()) - ec_write(0x0c, 0xc7); - - idedev = pcidev_on_root(0x1f, 1); - - if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { - /* legacy I/O connected */ - pmh7_ultrabay_power_enable(1); - ec_write(0x0c, 0x84); - } else if (idedev && idedev->chip_info && - h8_ultrabay_device_present()) { - config = idedev->chip_info; - config->ide_enable_primary = 1; - pmh7_ultrabay_power_enable(1); - ec_write(0x0c, 0x84); - } else { - pmh7_ultrabay_power_enable(0); - ec_write(0x0c, 0x04); - } - - /* set dock status led */ - ec_write(0x0c, 0x08); - ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/z61t/mptable.c b/src/mainboard/lenovo/z61t/mptable.c deleted file mode 100644 index 165b725..0000000 --- a/src/mainboard/lenovo/z61t/mptable.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ - - mptable_lintsrc(mc, isa_bus); - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c deleted file mode 100644 index 820cd52..0000000 --- a/src/mainboard/lenovo/z61t/romstage.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - -#include <stdint.h> -#include <cf9_reset.h> -#include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <northbridge/intel/i945/i945.h> -#include <northbridge/intel/i945/raminit.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <southbridge/intel/common/pmclib.h> -#include "dock.h" - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN - | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN); - - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); - - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); - - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); -} - -static void rcba_config(void) -{ - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00001230; - RCBA32(D29IP) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(D28IP) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(D27IP) = 0x00000002; - - /* dev irq route register */ - RCBA16(D31IR) = 0x1007; - RCBA16(D30IR) = 0x0076; - RCBA16(D29IR) = 0x3210; - RCBA16(D28IR) = 0x7654; - RCBA16(D27IR) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA64(IOTR0) = 0x000200010000fe01ULL; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA64(IOTR3) = 0x000200f0000c0801ULL; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - -void mainboard_romstage_entry(unsigned long bist) -{ - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); - setup_pch_gpios(&mainboard_gpio_map); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/lenovo/z61t/smi.h b/src/mainboard/lenovo/z61t/smi.h deleted file mode 100644 index f20314f..0000000 --- a/src/mainboard/lenovo/z61t/smi.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_LENOVO_X60_SMI_H -#define MAINBOARD_LENOVO_X60_SMI_H - -#define SMI_DOCK_CONNECT 0x01 -#define SMI_DOCK_DISCONNECT 0x02 -#define SMI_BRIGHTNESS_UP 0x03 -#define SMI_BRIGHTNESS_DOWN 0x04 - -#endif diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c deleted file mode 100644 index 51ced89..0000000 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/i82801gx/nvs.h> -#include <southbridge/intel/common/pmutil.h> -#include <ec/acpi/ec.h> -#include "dock.h" -#include "smi.h" - -#define GPE_EC_SCI 12 - -#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ - -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; - if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) - *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; - } -} - -static void mainboard_smi_brightness_up(void) -{ - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; - if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) - *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; - } -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - case SMI_DOCK_CONNECT: - /* If there's an legacy I/O module present, we're not - * allowed to connect the Docking LPC Bus, as both Super I/O - * chips are using 0x2e as base address. - */ - if (legacy_io_present()) - break; - - if (!dock_connect()) { - /* set dock LED to indicate status */ - ec_write(0x0c, 0x08); - ec_write(0x0c, 0x89); - } else { - /* blink dock LED to indicate failure */ - ec_write(0x0c, 0xc8); - ec_write(0x0c, 0x09); - } - break; - - case SMI_DOCK_DISCONNECT: - dock_disconnect(); - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x08); - break; - - case SMI_BRIGHTNESS_UP: - mainboard_smi_brightness_up(); - break; - - case SMI_BRIGHTNESS_DOWN: - mainboard_smi_brightness_down(); - break; - - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - /* brightness up */ - case 0x14: - mainboard_smi_brightness_up(); - break; - /* brightness down */ - case 0x15: - mainboard_smi_brightness_down(); - break; - /* Fn-F9 Key */ - case 0x18: - /* power loss */ - case 0x27: - /* undock event */ - case 0x50: - mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); - break; - /* dock event */ - case 0x37: - mainboard_io_trap_handler(SMI_DOCK_CONNECT); - break; - default: - break; - } -} - -void mainboard_smi_gpi(u32 gpi) -{ - if (gpi & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - break; - default: - break; - } - return 0; -} diff --git a/src/mainboard/lenovo/z61t/thermal.h b/src/mainboard/lenovo/z61t/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/z61t/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Gerrit-Change-Number: 34123 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/drallion: Remove touch screen detect.
by JoeJ Chang (Code Review) 08 Oct '19

08 Oct '19

JoeJ Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35644 ) Change subject: mb/google/drallion: Remove touch screen detect. ...................................................................... mb/google/drallion: Remove touch screen detect. GPP_B4 is always high due to the cable issue, remove the HW strap detect temporarily. BUG=b:141722840 Signed-off-by: JoeJ Chang <joej_chang(a)compal.corp-partner.google.com> Change-Id: I8781f36d87ece1980137cddde9fe2b6e3f3d5636 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35644/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d824a55..89e2df8 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -344,8 +344,6 @@ register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - register "generic.device_present_gpio" = "GPP_B4" - register "generic.device_present_gpio_invert" = "1" device i2c 10 on end end chip drivers/i2c/generic @@ -358,8 +356,6 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" - register "device_present_gpio" = "GPP_B4" - register "device_present_gpio_invert" = "1" device i2c 34 on end end end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8781f36d87ece1980137cddde9fe2b6e3f3d5636 Gerrit-Change-Number: 35644 Gerrit-PatchSet: 1 Gerrit-Owner: JoeJ Chang <joej_chang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

8 13

Change in coreboot[master]: src: Capitalize Super I/O
by HAOUAS Elyes (Code Review) 07 Oct '19

07 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35541 ) Change subject: src: Capitalize Super I/O ...................................................................... src: Capitalize Super I/O Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/p8h61-m_lx.md M Documentation/mainboard/asus/p8h61-m_pro.md M Documentation/mainboard/supermicro/x10slm-f.md M src/device/pnp_device.c M src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl M src/superio/acpi/pnp_generic.asl M src/superio/acpi/pnp_kbc.asl M src/superio/acpi/pnp_uart.asl 9 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35541/1 diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index df00abd..6a0da5b 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -70,7 +70,7 @@ - The VGA port doesn't work until the OS reinitialises the display. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, but the required driver doesn't exist in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index 5eb7193..212ed97 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -49,7 +49,7 @@ suspend. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md index 169678e..713c794 100644 --- a/Documentation/mainboard/asus/p8h61-m_pro.md +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -46,7 +46,7 @@ ## Known issues - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 7fae61f..acb2c84 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -168,7 +168,7 @@ - VGA graphics - disabling VGA graphics using the jumper - hiding the AST2400 using the CMOS setting -- super I/O hardware monitor (see [Known issues](#known-issues)) +- Super I/O hardware monitor (see [Known issues](#known-issues)) - initialisation with Haswell MRC version 1.6.1 build 2 - flashrom under coreboot - Wake-on-LAN diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 164fc19..28a45d0 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -109,7 +109,7 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - /* The PNP_MSC super IO registers have the IRQ flag set. If no + /* The PNP_MSC Super IO registers have the IRQ flag set. If no value is assigned in the devicetree, the corresponding PNP_MSC register doesn't get written, which should be printed as warning and not as error. */ diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl index d1b2193..9de6da0 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl +++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl @@ -1 +1 @@ -/* no super i/o */ +/* no Super I/O */ diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 980404e..dbae2ac 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -20,9 +20,9 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) * SUPERIO_PNP_HID The EisaId string that identifies this device (optional) - * SUPERIO_PNP_LDN The logical device number on the super i/o + * SUPERIO_PNP_LDN The logical device number on the Super I/O * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device * name (DDN) of this device (e.g. "COM1", optional) diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index cbcfd55..541dce3 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -22,8 +22,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_KBC_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_KBC_LDN The logical device number on the Super I/O * chip for this keyboard controller (required) * SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in * the KBC_LDN. Mouse irq is set at IRQ1 of the diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index f42cc42..3cbe65a 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -21,8 +21,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_UART_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_UART_LDN The logical device number on the Super I/O * chip for this UART (required) * SUPERIO_UART_DDN A string literal that identifies the dos device * name (DDN) of this uart (e.g. "COM1", optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/35541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Gerrit-Change-Number: 35541 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019