Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35620 )
Change subject: soc/intel/{skl,icl,cnl}/chip: Unhide P2SB device
......................................................................
soc/intel/{skl,icl,cnl}/chip: Unhide P2SB device
APL unhides the P2SB device in coreboot already. Do it the same on
other SoCs.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.
Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35620/1
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 4e0dba5..e3962c0 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -21,6 +21,7 @@
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@@ -187,6 +188,13 @@
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
+ /*
+ * Keep the P2SB device visible so it and the other devices are
+ * visible in coreboot for driver support and PCI resource allocation.
+ * There is no UPD setting for this.
+ */
+ p2sb_unhide();
+
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index c4abb0c..abaae9f 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -21,6 +21,7 @@
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
@@ -128,6 +129,13 @@
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
+ /*
+ * Keep the P2SB device visible so it and the other devices are
+ * visible in coreboot for driver support and PCI resource allocation.
+ * There is no UPD setting for this.
+ */
+ p2sb_unhide();
+
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index d1d7d6f..7fe1601 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -28,6 +28,7 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
@@ -175,6 +176,13 @@
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
+ /*
+ * Keep the P2SB device visible so it and the other devices are
+ * visible in coreboot for driver support and PCI resource allocation.
+ * There is no UPD setting for this.
+ */
+ p2sb_unhide();
+
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Gerrit-Change-Number: 35620
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35312 )
Change subject: soc/intel/skylake: Fix crash in MP init
......................................................................
soc/intel/skylake: Fix crash in MP init
If CPU supports SGX and Hyper-Threading the later needs to be disabled.
This fixes random crashes in MP-Init.
I could not find any relation between those two in any datasheet.
To fully migitate L1TF or E2E attacks, hyperthreading should be disabled
anyway if SGX is enabled.
Tested on X11SSH-TF.
Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
M src/soc/intel/skylake/Kconfig
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35312/1
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
index ce6bfa5..acfac29 100644
--- a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
+++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
@@ -31,7 +31,7 @@
register "SaGv" = "SaGv_Disabled"
# Disable SGX
- register "sgx_enable" = "0" # SGX is broken in coreboot
+ register "sgx_enable" = "1" # SGX is broken once Hyper-Threading is enabled
register "PrmrrSize" = "128 * MiB"
register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 901e5f9..2059618 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -81,6 +81,7 @@
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
depends on MAINBOARD_USES_FSP2_0
+ depends on !SOC_INTEL_COMMON_BLOCK_SGX
default y
config CPU_INTEL_NUM_FIT_ENTRIES
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Gerrit-Change-Number: 35312
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969
Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
......................................................................
soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
This moves some boilerplate like setting up timestamps and entering
postcar to a common location.
Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/baytrail/romstage/Makefile.inc
M src/soc/intel/baytrail/romstage/romstage.c
2 files changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index f1a3463..8f009bd 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,5 +1,6 @@
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
cpu_incs-y += $(obj)/fmap_config.h
+romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += raminit.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index cc3bcd9..2a530b4 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -21,6 +21,7 @@
#include <bootblock_common.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
@@ -49,8 +50,6 @@
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
-static void platform_enter_postcar(void);
-
static void program_base_addresses(void)
{
uint32_t reg;
@@ -166,18 +165,12 @@
}
/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc, uint32_t bist)
+void mainboard_romstage_entry(unsigned long bist)
{
struct mrc_params mrc_params;
struct chipset_power_state *ps;
int prev_sleep_state;
- /* Save initial timestamp from bootblock. */
- timestamp_init(tsc);
-
- /* Save romstage begin */
- timestamp_add_now(TS_START_ROMSTAGE);
-
program_base_addresses();
tco_disable();
@@ -215,25 +208,13 @@
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
- platform_enter_postcar();
-
- /* We don't return here */
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
- romstage_main(base_timestamp, bist);
}
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
-static void platform_enter_postcar(void)
+void platform_enter_postcar(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
--
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Gerrit-Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556
Gerrit-Change-Number: 32969
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange