coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in ...coreboot[master]: soc/intel/baytrail: Get rid of struct romstage_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32966 Change subject: soc/intel/baytrail: Get rid of struct romstage_params ...................................................................... soc/intel/baytrail: Get rid of struct romstage_params struct romstage_params holds the BIST and a struct mrc_params pointer. The BIST information is unused. It is easier to just use a mrc_params struct variable. Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 13 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32966/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267..eba8beb 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,20 +55,16 @@ return &spd_file_content[SPD_SIZE * ram_id]; } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_romstage_entry(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; + mrc_params->mainboard.dram_type = DRAM_DDR3L; + mrc_params->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mrc_params->mainboard.weaker_odt_settings = 1; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); @@ -77,10 +73,9 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); - mp.mainboard.dram_data[0] = spd_content; + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; + mrc_params->mainboard.dram_data[1] = spd_content; - rp->mrc_params = &mp; - romstage_common(rp); + romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a2..4fceefb 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,13 +24,8 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; - -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_romstage_entry(struct mrc_params *mrc_params); +void romstage_common(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd1..73991df 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -99,10 +99,7 @@ /* Entry from cache-as-ram.inc. */ static void romstage_main(uint64_t tsc, uint32_t bist) { - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; + struct mrc_params mrc_params; /* Save initial timestamp from bootblock. */ timestamp_init(tsc); @@ -127,7 +124,7 @@ gfx_init(); /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + mainboard_romstage_entry(&mrc_params); platform_enter_postcar(); @@ -212,7 +209,7 @@ } /* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +void romstage_common(struct mrc_params *mrc_params) { struct chipset_power_state *ps; int prev_sleep_state; @@ -231,7 +228,7 @@ /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); + raminit(mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/32966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Gerrit-Change-Number: 32966 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31600 Change subject: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info ...................................................................... [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info Fixes microcode not being updated. Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31600/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index acd56c8..1a6110b 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -49,6 +49,13 @@ smm_initialize(); } +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + #define SMRR_SUPPORTED (1 << 11) static void per_cpu_smm_trigger(void) @@ -98,6 +105,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = pre_mp_smm_init, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, -- To view, visit https://review.coreboot.org/c/coreboot/+/31600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Gerrit-Change-Number: 31600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 13

Change in ...coreboot[master]: cpu/intel/common: Compute the TSC tick freq based on FSB
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31203 Change subject: cpu/intel/common: Compute the TSC tick freq based on FSB ...................................................................... cpu/intel/common: Compute the TSC tick freq based on FSB This allows the cbmem utility to compute timestamps based on coreboot tables without relying on other userspace components. Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/common/fsb.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31203/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 1f7c391..cf258bd 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,7 +11,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> @@ -83,3 +85,27 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr; + unsigned long multiplier; + struct cpuinfo_x86 c; + + get_fms(&c, cpuid_eax(1)); + + msr = rdmsr(IA32_PLATFORM_ID); + multiplier = (msr.lo & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + if ((c.x86 == 6 && c.x86_model == 0xe) || (c.x86 == 0xf)) { + /* Looks like Yonah CPUs don't have the frequency ratio in + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading + should be reliable as those CPUs don't have turbo mode. */ + msr = rdmsr(IA32_PERF_STATUS); + multiplier = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + } + + printk(BIOS_DEBUG, "CPU freq %ld\n", multiplier * get_ia32_fsb()); + return multiplier * get_ia32_fsb(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Gerrit-Change-Number: 31203 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31202 Change subject: arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE ...................................................................... arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE timestamp_tick_freq_mhz() is used to populate the coreboot tables which cbmem can use to determine timestamps without needing userspace tools to get the TSC frequency rate. CONFIG_TSC_CONSTANT_RATE depends on CONFIG_UDELAY_TSC which is not the case on all targets that could still make use of this functionality. Change-Id: I8c34eb811e27d2a91ccf1ca6f48a638da5f6cfd9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/timestamp.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31202/1 diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index b5257c4..f7b5541 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -21,14 +21,20 @@ return rdtscll(); } +/* We want build to fail on targets with CONFIG_TSC_CONSTANT_RATE + if an implementation is lacking since it used to compute udelays. + FIXME: provide an implementation on every target to get rid of this.*/ +#if !IS_ENABLED(CONFIG_TSC_CONSTANT_RATE) +unsigned long __weak tsc_freq_mhz(void) +{ + /* Default to not knowing TSC frequency. cbmem will have to fallback + * on trying to determine it in userspace. */ + return 0; +} +#endif + int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) - return tsc_freq_mhz(); - - /* Filling tick_freq_mhz = 0 in timestamps-table will trigger - * userspace utility to try deduce it from the running system. - */ - return 0; + return tsc_freq_mhz(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c34eb811e27d2a91ccf1ca6f48a638da5f6cfd9 Gerrit-Change-Number: 31202 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: sb/intel/i82801gx: Add a mb hook to override the SPI opmenu
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30888 Change subject: sb/intel/i82801gx: Add a mb hook to override the SPI opmenu ...................................................................... sb/intel/i82801gx: Add a mb hook to override the SPI opmenu By default the SPI configuration gets locked down, but the default opmenu setting could not work with some SPI flashes. This fixes unmodified flashrom not being able to flash the Thinkpad X60 with CONFIG_INTEL_CHIPSET_LOCKDOWN set. Change-Id: I43e6abcc5c761720b31bc023016cb71b860e76ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x60/mainboard.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 3 files changed, 126 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30888/1 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 5cf0d26..f770cf9 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,10 +22,12 @@ #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> +#include <spi_flash.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -68,6 +70,60 @@ return ARRAY_SIZE(cst_entries); } +/* + * SPI lockdown configuration for SST25VF016B. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xad /* Auto Address Increment Word Program */ +#define SPI_OPTYPE_6 0x01 /* Write, address required */ + +#define SPI_OPMENU_7 0x04 /* Write Disable */ +#define SPI_OPTYPE_7 0x01 /* Write, no address */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config_sst = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +}; + + +void mainboard_override_spi_config(struct spi_config *cfg) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + + if (strcmp(flash->name, "SST25VF016B") == 0) { + memcpy(cfg, &spi_config_sst, sizeof(*cfg)); + } +} + static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 9fd9fd6..0a32201 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -364,51 +364,16 @@ #define C3_RES 0x54 #define TCO1_CNT 0x68 -/* SPIBAR - * - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. +/* + * SPI lockdown configuration. */ +struct spi_config { + uint16_t preop; + uint16_t optype; + uint32_t opmenu[2]; +}; -#define PREOP 0x54 -#define OPTYPE 0x56 -#define OPMENU 0x58 - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +void mainboard_override_spi_config(struct spi_config *cfg); #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index e8cfc74..175b33a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -645,21 +645,79 @@ } } +/* SPIBAR + * + * SPI Opcode Menu setup for SPIBAR lockdown + * should support most common flash chips. + */ + +#define PREOP 0x54 +#define OPTYPE 0x56 +#define OPMENU 0x58 + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + #define SPIBAR16(x) RCBA16(0x3020 + x) #define SPIBAR32(x) RCBA32(0x3020 + x) +void __weak mainboard_override_spi_config(struct spi_config *cfg) +{ +} + static void lpc_final(struct device *dev) { u16 tco1_cnt; + struct spi_config spi_cfg; if (!IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; + spi_cfg.preop = SPI_OPPREFIX; + spi_cfg.optype = SPI_OPTYPE; + spi_cfg.opmenu[0] = SPI_OPMENU_LOWER; + spi_cfg.opmenu[1] = SPI_OPMENU_UPPER; + + mainboard_override_spi_config(&spi_cfg); + + SPIBAR16(PREOP) = spi_cfg.preop; /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + SPIBAR16(OPTYPE) = spi_cfg.optype; + SPIBAR32(OPMENU) = spi_cfg.opmenu[0]; + SPIBAR32(OPMENU + 4) = spi_cfg.opmenu[1]; /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); -- To view, visit https://review.coreboot.org/c/coreboot/+/30888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43e6abcc5c761720b31bc023016cb71b860e76ed Gerrit-Change-Number: 30888 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: device/pci_device.c: Use verified boot to check oprom
by Frans Hendriks (Code Review) 12 Oct '19

12 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30810 Change subject: device/pci_device.c: Use verified boot to check oprom ...................................................................... device/pci_device.c: Use verified boot to check oprom Before oprom is executed, no check is performed if rom passes verification. Add call to verified_boot_should_run_oprom() to verify the oprom. BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/device/pci_device.c M src/include/device/pci_rom.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30810/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82033a6..40012f9 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -16,6 +16,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -802,6 +803,10 @@ if (!should_run_oprom(dev)) return; + if (IS_ENABLED(CONFIG_VERIFIED_BOOT)) + if (!verified_boot_should_run_oprom(rom)) + return; + run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n"); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index a4aa52a..865fea3 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef PCI_ROM_H #define PCI_ROM_H #include <endian.h> @@ -47,4 +63,5 @@ u32 map_oprom_vendev(u32 vendev); +int verified_boot_should_run_oprom(struct rom_header *rom_header); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Gerrit-Change-Number: 30810 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

8 12

Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH family SKUs
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35030 ) Change subject: soc/intel/skylake: Add Lewisburg PCH family SKUs ...................................................................... soc/intel/skylake: Add Lewisburg PCH family SKUs Adds the Lewisburg PCH family product and super SKUs These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35030/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3ac6560..8de8241 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2713,6 +2713,19 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_SPT_H_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_LWB_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LWB_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LWB_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LWB_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LWB_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LWB_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LWB_C628 0xa1c7 +#define PCI_DEVICE_ID_INTEL_LWB_C629 0xa1ca +#define PCI_DEVICE_ID_INTEL_LWB_C624_SUPER 0xa242 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1 0xa243 +#define PCI_DEVICE_ID_INTEL_LWB_C621_SUPER 0xa244 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2 0xa245 +#define PCI_DEVICE_ID_INTEL_LWB_C628_SUPER 0xa246 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d7917d6..178b895 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -138,6 +138,7 @@ PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, PCI_DEVICE_ID_INTEL_SPT_H_CM238, + PCI_DEVICE_ID_INTEL_SPT_H_CM238, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index a643bbe..d4d26c1 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -87,6 +87,19 @@ { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM175, "Skylake PCH-H QM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_CM238, "Skylake PCH-H CM238" }, + { PCI_DEVICE_ID_INTEL_LWB_C621, "Lewisburg PCH C621" }, + { PCI_DEVICE_ID_INTEL_LWB_C622, "Lewisburg PCH C622" }, + { PCI_DEVICE_ID_INTEL_LWB_C624, "Lewisburg PCH C624" }, + { PCI_DEVICE_ID_INTEL_LWB_C625, "Lewisburg PCH C625" }, + { PCI_DEVICE_ID_INTEL_LWB_C626, "Lewisburg PCH C626" }, + { PCI_DEVICE_ID_INTEL_LWB_C627, "Lewisburg PCH C627" }, + { PCI_DEVICE_ID_INTEL_LWB_C628, "Lewisburg PCH C628" }, + { PCI_DEVICE_ID_INTEL_LWB_C629, "Lewisburg PCH C629" }, + { PCI_DEVICE_ID_INTEL_LWB_C624_SUPER, "Lewisburg PCH C624 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1, "Lewisburg PCH C627 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C621_SUPER, "Lewisburg PCH C621 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2, "Lewisburg PCH C627 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C628_SUPER, "Lewisburg PCH C628 Super Sku" }, { PCI_DEVICE_ID_INTEL_KBP_H_Q270, "Kabylake-H Q270" }, { PCI_DEVICE_ID_INTEL_KBP_H_H270, "Kabylake-H H270" }, { PCI_DEVICE_ID_INTEL_KBP_H_Z270, "Kabylake-H Z270" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Gerrit-Change-Number: 35030 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: mb/supermicro: Add Supermicro X9SCL+-F
by Christoph Pomaska (Code Review) 10 Oct '19

10 Oct '19

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34873 ) Change subject: mb/supermicro: Add Supermicro X9SCL+-F ...................................................................... mb/supermicro: Add Supermicro X9SCL+-F This port is not working correctly at the moment as coreboot gets stuck in or before postCAR. What works: - RAMinit - Serial (RS232) What does not work: - basically everything else Further notes: - To prevent problems its recommended to always flash after powering the power supply, disable and reenable power supply before flashing. Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A src/mainboard/supermicro/x9scl-f/Kconfig A src/mainboard/supermicro/x9scl-f/Kconfig.name A src/mainboard/supermicro/x9scl-f/Makefile.inc A src/mainboard/supermicro/x9scl-f/acpi/ec.asl A src/mainboard/supermicro/x9scl-f/acpi/platform.asl A src/mainboard/supermicro/x9scl-f/acpi/superio.asl A src/mainboard/supermicro/x9scl-f/acpi_tables.c A src/mainboard/supermicro/x9scl-f/board_info.txt A src/mainboard/supermicro/x9scl-f/devicetree.cb A src/mainboard/supermicro/x9scl-f/dsdt.asl A src/mainboard/supermicro/x9scl-f/gpio.c A src/mainboard/supermicro/x9scl-f/hda_verb.c A src/mainboard/supermicro/x9scl-f/mainboard.c A src/mainboard/supermicro/x9scl-f/romstage.c 14 files changed, 618 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34873/1 diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig b/src/mainboard/supermicro/x9scl-f/Kconfig new file mode 100644 index 0000000..f4bead2 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Kconfig @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Hosting.de GmbH +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## + +if BOARD_SUPERMICRO_X9SCL_PLUS_F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + select NO_STAGE_CACHE + +config MAINBOARD_DIR + string + default "supermicro/x9scl-f" + +config MAINBOARD_PART_NUMBER + string + default "X9SCL+-F" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "10sb,0532" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig.name b/src/mainboard/supermicro/x9scl-f/Kconfig.name new file mode 100644 index 0000000..fd73657 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL_PLUS_F + bool "X9SCL+-F" diff --git a/src/mainboard/supermicro/x9scl-f/Makefile.inc b/src/mainboard/supermicro/x9scl-f/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl-f/acpi/ec.asl b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9scl-f/acpi/platform.asl b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl new file mode 100644 index 0000000..b269aa7 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/supermicro/x9scl-f/acpi/superio.asl b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl diff --git a/src/mainboard/supermicro/x9scl-f/acpi_tables.c b/src/mainboard/supermicro/x9scl-f/acpi_tables.c new file mode 100644 index 0000000..315379d --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi_tables.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl-f/board_info.txt b/src/mainboard/supermicro/x9scl-f/board_info.txt new file mode 100644 index 0000000..a14680e --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl-f/devicetree.cb b/src/mainboard/supermicro/x9scl-f/devicetree.cb new file mode 100644 index 0000000..d12f2e6f88 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/devicetree.cb @@ -0,0 +1,107 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc1641" + register "gen3_dec" = "0x00040ca1" + register "gen4_dec" = "0x001c03e1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x15d9 0x0624 + end + device pci 1b.0 off # High Definition Audio + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x15d9 0x0624 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x15d9 0x0624 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x15d9 0x0624 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x15d9 0x0624 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x15d9 0x0624 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x15d9 0x0624 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x15d9 0x0624 + end + device pci 1f.3 on # SMBus + subsystemid 0x15d9 0x0624 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x15d9 0x0624 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 off # Internal graphics + end + end +end diff --git a/src/mainboard/supermicro/x9scl-f/dsdt.asl b/src/mainboard/supermicro/x9scl-f/dsdt.asl new file mode 100644 index 0000000..1f86a1d --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/supermicro/x9scl-f/gpio.c b/src/mainboard/supermicro/x9scl-f/gpio.c new file mode 100644 index 0000000..8567313 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/gpio.c @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl-f/hda_verb.c b/src/mainboard/supermicro/x9scl-f/hda_verb.c new file mode 100644 index 0000000..a5b6e19 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/hda_verb.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl-f/mainboard.c b/src/mainboard/supermicro/x9scl-f/mainboard.c new file mode 100644 index 0000000..7992796 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/supermicro/x9scl-f/romstage.c b/src/mainboard/supermicro/x9scl-f/romstage.c new file mode 100644 index 0000000..426d1c9 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x370f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a Gerrit-Change-Number: 34873 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: google/kukui: force run dram full-k blob
by huayang duan (Code Review) 09 Oct '19

09 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35110 ) Change subject: google/kukui: force run dram full-k blob ...................................................................... google/kukui: force run dram full-k blob Force load dram.bin and run it for full dram calibration. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c 1 file changed, 53 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35110/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 131d167..f3774a1 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/stages.h> +#include <assert.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> @@ -33,7 +34,7 @@ int (*dram_init)(void *param); size_t blob_size, region_size; - region_size = _edram_init_code - _dram_init_code; + region_size = REGION_SIZE(dram_init_code); blob_size = cbfs_boot_load_file("dram.bin", _dram_init_code, region_size, CBFS_TYPE_RAW); if (blob_size == 0) { @@ -42,18 +43,43 @@ } dram_init = (int (*)(void *))_dram_init_code; + printk(BIOS_ERR, "dram.bin after _dram_init_code\n"); return dram_init(NULL); } +static const struct sdram_params *get_full_k_param(void) +{ + const struct sdram_params *params = NULL; + + //load params from flash(the params generated by full-k blob) + //TODO + //params = read_params_from_flash() + params = get_sdram_config(); + + return params; +} + +static bool force_full_k_dram = true; static void dram_initialize(void) { - int err = dram_blob_load_and_run(); - if (err == 0) - return; + const struct sdram_params *params = NULL; - printk(BIOS_ERR, "dram_blob error:%d\n", err); - mt_mem_init(get_sdram_config()); + params = get_full_k_param(); + + //if (!params->have_full_k_params) { + if (force_full_k_dram) { + int err = dram_blob_load_and_run(); + if (err == 0) { + printk(BIOS_INFO, "dram_blob load success\n"); + return; + } + printk(BIOS_ERR, "dram_blob error:%d\n", err); + } + + //load params from sdram-ddr-config + params = get_sdram_config(); + mt_mem_init(params); } void platform_romstage_main(void) @@ -69,5 +95,26 @@ pmic_init_scp_voltage(); rtc_boot(); dram_initialize(); + + printk(BIOS_DEBUG, "before do first complex_mem_test \n"); + for (u8 *addr = (u8*)0x40000000; addr < (u8*)0x100000000; addr+=0x40000000) { + int i = complex_mem_test(addr, 0x50000); + + printk(BIOS_DEBUG, "[MEM]addr:0x%p complex R/W mem test %s : %d\n", addr, + (i == 0) ? "pass" : "fail", i); + + ASSERT(i == 0); + } + mtk_mmu_after_dram(); + + printk(BIOS_DEBUG, "before do second complex_mem_test \n"); + for (u8 *addr = (u8*)0x40000000; addr < (u8*)0x100000000; addr+=0x40000000) { + int i = complex_mem_test(addr, 0x50000); + + printk(BIOS_DEBUG, "[MEM]addr:0x%p complex R/W mem test %s : %d\n", addr, + (i == 0) ? "pass" : "fail", i); + + ASSERT(i == 0); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Gerrit-Change-Number: 35110 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

8 62

Change in coreboot[master]: mediatek/mt8183: Use calibration result do fast calibration
by huayang duan (Code Review) 09 Oct '19

09 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35164 ) Change subject: mediatek/mt8183: Use calibration result do fast calibration ...................................................................... mediatek/mt8183: Use calibration result do fast calibration Load calibration result from flash, if result was correct, use this calibration result do fast calibration to reduce the bootup time. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/memory.c 5 files changed, 366 insertions(+), 254 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35164/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9103c2d..232b4cf 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -601,45 +601,54 @@ static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group) { - s8 clkDelay[CHANNEL_MAX] = {0x0}; - s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; + if (params->have_full_k_params) { + dramc_dbg("bypass duty calibration\n"); - switch (freq_group) { - case LP4X_DDR1600: - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - break; - case LP4X_DDR2400: - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 0; - dqsDelay[CHANNEL_B][1] = -2; - break; - case LP4X_DDR3200: - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 1; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 1; - dqsDelay[CHANNEL_B][1] = -2; - break; - case LP4X_DDR3600: - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - break; - } + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay(chn, params->duty_dqs_delay[chn]); + } + } else { + s8 clkDelay[CHANNEL_MAX] = {0x0}; + s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - dramc_duty_set_clk_delay(chn, clkDelay[chn]); - dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + switch (freq_group) { + case LP4X_DDR1600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + case LP4X_DDR2400: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 0; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3200: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 1; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 1; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, clkDelay[chn]); + dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + } } } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 39ea0b3..220a319 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -244,17 +244,25 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { - u32 cbt_cs, mr12_value; + u32 final_vref, clk_dly, cmd_dly, cs_dly; - cbt_cs = params->cbt_cs[chn][rank]; - mr12_value = params->cbt_mr12[chn][rank]; + clk_dly = params->cbt_clk_dly[chn][rank]; + cmd_dly = params->cbt_cmd_dly[chn][rank]; + cs_dly = params->cbt_cs_dly[chn][rank]; + final_vref = params->cbt_final_vref[chn][rank]; - /* CBT adjust cs */ - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + if (params->have_full_k_params) { + /* Set CLK and CA delay */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + (0x3f << 8) | (0x3f << 24), (cmd_dly << 8) | (clk_dly << 24)); + udelay(1); + } + + /* Set CLK and CS delay */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], 0x3f, cs_dly << 0); /* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); + dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } static void dramc_read_dbi_onoff(bool on) @@ -885,112 +893,124 @@ coarse_end = coarse_start + 12; dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { - u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; - u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; - u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; - u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; - u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; - u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + if (params->have_full_k_params) { + dramc_dbg("[bypass Gating]\n"); + } else { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { + u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; + u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - if (value >= 11) { - value -= 11; - dly_coarse_large_rodt = value >> 3; + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; + u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; + u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + + if (value >= 11) { + value -= 11; + dly_coarse_large_rodt = value >> 3; dly_coarse_0p5t_rodt = value - (dly_coarse_large_rodt << 3); - value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; - dly_coarse_large_rodt_p1 = value >> 3; + value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; + dly_coarse_large_rodt_p1 = value >> 3; dly_coarse_0p5t_rodt_p1 = value - (dly_coarse_large_rodt_p1 << 3); - } + } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - 0x77777777, - (dly_coarse_large << 0) | (dly_coarse_large << 8) | - (dly_coarse_large << 16) | (dly_coarse_large << 24) | - (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | - (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - 0x77777777, - (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | - (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | - (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | - (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - 0x77777777, - (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | - (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | - (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | - (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - 0x77777777, - (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | - (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | - (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | - (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (dly_coarse_large << 0) | (dly_coarse_large << 8) | + (dly_coarse_large << 16) | (dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | + (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); - for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { - dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - dly_fine_xt | (dly_fine_xt << 8)); + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { + dramc_set_gating_mode(chn, 0); + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + dly_fine_xt | (dly_fine_xt << 8)); - dram_phy_reset(chn); + dram_phy_reset(chn); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); udelay(1); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & - MISC_STBERR_RK_R_STBERR_RK_R_MASK; - u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & - MISC_STBERR_RK_F_STBERR_RK_F_MASK; - debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); - debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; - debug_cnt[0] &= 0xffff; + u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & + MISC_STBERR_RK_R_STBERR_RK_R_MASK; + u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & + MISC_STBERR_RK_F_STBERR_RK_F_MASK; + debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); + debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; + debug_cnt[0] &= 0xffff; - dramc_set_gating_mode(chn, 1); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_set_gating_mode(chn, 1); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - dramc_find_dly_tune(chn, dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt, dqs_high, - dly_coarse_large_cnt, dly_coarse_0p5t_cnt, - dly_fine_tune_cnt, dqs_transition, dqs_done); + dramc_find_dly_tune(chn, dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt, dqs_high, + dly_coarse_large_cnt, dly_coarse_0p5t_cnt, + dly_fine_tune_cnt, dqs_transition, dqs_done); - dramc_dbg("%d %d %d |", dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_dbg("%X ", debug_cnt[dqs]); + dramc_dbg("%d %d %d |", dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_dbg("%X ", debug_cnt[dqs]); - dramc_dbg(" |"); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - dramc_dbg("(%X %X)", - (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, - (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + dramc_dbg(" |"); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("(%X %X)", + (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, + (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + } + + dramc_dbg("\n"); + if (dramc_find_gating_window(result_r, result_f, debug_cnt, + dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, + pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + coarse_tune = coarse_end; } - - dramc_dbg("\n"); - if (dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, - pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) - coarse_tune = coarse_end; } + + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - pass_count[dqs] = dqs_transition[dqs]; - min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; - min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; - min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; - + if (params->have_full_k_params) { + dramc_dbg("[bypass Gating params] dqs:%d\n", dqs); + pass_count[dqs] = params->gating_pass_count[chn][rank][dqs]; + min_fine_tune[dqs] = params->gating_fine_tune[chn][rank][dqs]; + min_coarse_tune0p5t[dqs] = params->gating05T[chn][rank][dqs]; + min_coarse_tune2t[dqs] = params->gating2T[chn][rank][dqs]; + } else { + pass_count[dqs] = dqs_transition[dqs]; + min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; + min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; + min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; + } u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2; u8 tmp_value = min_fine_tune[dqs] + tmp_offset; best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP; @@ -1551,20 +1571,34 @@ else use_delay_cell = 0; - for (u8 byte = 0; byte < DQS_NUMBER; byte++) { - center_dly[byte].min_center = 0xffff; - center_dly[byte].max_center = 0; - - for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { - index = bit + 8 * byte; - if (vref_dly[index].win_center < center_dly[byte].min_center) - center_dly[byte].min_center = vref_dly[index].win_center; - if (vref_dly[index].win_center > center_dly[byte].max_center) - center_dly[byte].max_center = vref_dly[index].win_center; + if (params->have_full_k_params && (bypass_tx)) { + dramc_dbg("bypass TX\n"); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; + center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + vref_dly[index].win_center = params->tx_win_center[chn][rank][index]; + vref_dly[index].best_first = params->tx_first_pass[chn][rank][index]; + vref_dly[index].best_last = params->tx_last_pass[chn][rank][index]; + } } - dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", - chn, rank, byte, center_dly[byte].min_center, - center_dly[byte].max_center); + } else { + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = 0xffff; + center_dly[byte].max_center = 0; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < center_dly[byte].min_center) + center_dly[byte].min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > center_dly[byte].max_center) + center_dly[byte].max_center = vref_dly[index].win_center; + } + dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", + chn, rank, byte, center_dly[byte].min_center, + center_dly[byte].max_center); + } } for (u8 byte = 0; byte < DQS_NUMBER; byte++) { @@ -1681,12 +1715,26 @@ u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; + bool bypass_tx = !fsp; dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, &dly_begin, &dly_end, params); + if (params->have_full_k_params) { + if (type == RX_WIN_TEST_ENG && vref_scan_enable == 1) { + vref_begin = params->rx_vref[chn]; + vref_end = vref_begin + 1; + dramc_dbg("bypass RX vref:%d\n", vref_begin); + } else if (type == TX_WIN_DQ_ONLY) { + vref_begin = params->tx_vref[chn][rank]; + vref_end = vref_begin + 1; + dramc_dbg("bypass TX vref:%d\n", vref_begin); + } + vref_dly.best_vref = vref_begin; + } + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) dly_step = 2; @@ -1705,98 +1753,112 @@ vref_step = 2; } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_init(chn, rank); - } else { - if (type == RX_WIN_TEST_ENG) - dramc_rx_vref_pre_setting(chn); - dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - } - - vref_dly.max_win_sum = 0; - for (vref = vref_begin; vref < vref_end; vref += vref_step) { - small_reg_value = 0xff; - finish_bit = 0; - if (type == TX_WIN_DQ_ONLY) - vref_use = vref | (vref_range << 6); - else - vref_use = vref; - - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_perbit[bit].first_pass = PASS_RANGE_NA; - win_perbit[bit].last_pass = PASS_RANGE_NA; - win_perbit[bit].best_first = PASS_RANGE_NA; - win_perbit[bit].best_last = PASS_RANGE_NA; + if (params->have_full_k_params && bypass_tx && + (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM)) { + dramc_set_tx_best_dly(chn, rank, bypass_tx,vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); + } else { + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_init(chn, rank); + } else { + if (type == RX_WIN_TEST_ENG) + dramc_rx_vref_pre_setting(chn); + dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); } - if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_use); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { - dramc_set_rx_dly_factor(chn, rank, - RX_DQM, FIRST_DQ_DELAY); - dramc_set_rx_dly_factor(chn, rank, - RX_DQ, FIRST_DQ_DELAY); - } - - for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); - - err_value = dram_k_perbit(chn, type); - if (!vref_scan_enable) - dramc_dbg("%d ", dly); + vref_dly.max_win_sum = 0; + for (vref = vref_begin; vref < vref_end; vref += vref_step) { + small_reg_value = 0xff; + finish_bit = 0; + if (type == TX_WIN_DQ_ONLY) + vref_use = vref | (vref_range << 6); + else + vref_use = vref; for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; - - /* pass window bigger than 7, consider as real pass window */ - if (dramc_check_dqdqs_win(&(win_perbit[bit]), - dly, dly_end, bit_fail) > 7) - finish_bit |= (1 << bit); - - if (vref_scan_enable) - continue; - dramc_dbg("%s", bit_fail ? "x" : "o"); - if (bit % DQS_BIT_NUMBER == 7) - dramc_dbg(" "); + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + win_perbit[bit].best_first = PASS_RANGE_NA; + win_perbit[bit].best_last = PASS_RANGE_NA; } - if (!vref_scan_enable) - dramc_dbg(" [MSB]\n"); + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_use); - if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { - dramc_dbg("all bits window found, early break! delay=0x%x\n", - dly); - break; + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { + dramc_set_rx_dly_factor(chn, rank, + RX_DQM, FIRST_DQ_DELAY); + dramc_set_rx_dly_factor(chn, rank, + RX_DQ, FIRST_DQ_DELAY); + } + + if (params->have_full_k_params && (type == RX_WIN_RD_DQC ||type == RX_WIN_TEST_ENG)) { + dramc_dbg("bypass RX params\n"); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].best_first = params->rx_firspass[chn][rank][bit]; + win_perbit[bit].best_last = params->rx_lastpass[chn][rank][bit]; + } + } else { + for (dly = dly_begin; dly < dly_end; dly += dly_step) { + dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); + + err_value = dram_k_perbit(chn, type); + if (!vref_scan_enable) + dramc_dbg("%d ", dly); + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + + /* pass window bigger than 7, consider as real pass window */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) + finish_bit |= (1 << bit); + + if (vref_scan_enable) + continue; + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); + } + + if (!vref_scan_enable) + dramc_dbg(" [MSB]\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, early break! delay=0x%x\n", + dly); + break; + } } } - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, - win_perbit[bit].best_first, win_perbit[bit].best_last, - win_perbit[bit].best_last - win_perbit[bit].best_first); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) + dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, + win_perbit[bit].best_first, win_perbit[bit].best_last, + win_perbit[bit].best_last - win_perbit[bit].best_first); - if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) - break; + if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) + break; + } + + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_end(chn); + } else { + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); + } + + if (vref_scan_enable && type == RX_WIN_TEST_ENG) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) + dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); + else + dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_end(chn); - } else { - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); - } - - if (vref_scan_enable && type == RX_WIN_TEST_ENG) - dramc_set_vref(chn, rank, type, vref_dly.best_vref); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) - dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); - else - dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, - freq_group, dq_precal_result, dly_cell_unit, params); - if (vref_scan_enable && type == TX_WIN_DQ_ONLY) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1843,40 +1905,45 @@ u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat, freq_group); + if (params->have_full_k_params) { + best_step = params->rx_datlat[chn][rank]; + dramc_dbg("bypass DATLAT, best_step:%d\n", best_step); + } else { + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group); - u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - if (err == 0) { - if (begin == 0) { - first = datlat; - begin = 1; + u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + if (err == 0) { + if (begin == 0) { + first = datlat; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; } - if (begin == 1) { - sum++; - if (sum > 4) - break; - } - } else { - if (begin == 1) - begin = 0xff; + + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } - dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + + assert(sum != 0); + + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - - assert(sum != 0); - - if (sum <= 3) - best_step = first + (sum >> 1); - else - best_step = first + 2; - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - begin, sum, best_step); - dramc_dle_factor_handler(chn, best_step, freq_group); clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 818458c..f51428b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -383,17 +383,19 @@ pmic_set_vdram2_vol(vddq); } -void mt_set_emi(const struct sdram_params *params) +void mt_set_emi(const struct sdram_params *freq_params) { - u32 current_freq = LP4X_HIGH_FREQ; + u8 current_freq = LP4X_HIGH_FREQ; + const struct sdram_params *params = NULL; #if DUAL_FREQ_K - u32 low_freq, middle_freq, high_freq; + u8 low_freq, middle_freq, high_freq; low_freq = LP4X_LOW_FREQ; middle_freq = LP4X_MIDDLE_FREQ; high_freq = LP4X_HIGH_FREQ; current_freq = low_freq; + params = &freq_params[current_freq]; #endif set_dram_voltage_by_freq(current_freq); @@ -402,11 +404,13 @@ #if DUAL_FREQ_K current_freq = middle_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); current_freq = high_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d918..07c4827 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -21,10 +21,42 @@ #include <soc/dramc_common_mt8183.h> struct sdram_params { - u32 impedance[2][4]; + bool have_full_k_params; + u16 frequency; u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; - u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + + /* DUTY */ + s8 duty_clk_delay[CHANNEL_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + + /* Gating */ + u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + + /* TX perbit */ + u8 tx_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + + /* datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_vref[CHANNEL_MAX]; + s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; @@ -47,7 +79,7 @@ size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); void enable_emi_dcm(void); -void mt_set_emi(const struct sdram_params *params); -void mt_mem_init(const struct sdram_params *params); +void mt_set_emi(const struct sdram_params *freq_params); +void mt_mem_init(const struct sdram_params *freq_params); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b2c7441..67f6c65 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -19,12 +19,12 @@ #include <soc/emi.h> #include <symbols.h> -void mt_mem_init(const struct sdram_params *params) +void mt_mem_init(const struct sdram_params *freq_params) { u64 rank_size[RANK_MAX]; /* memory calibration */ - mt_set_emi(params); + mt_set_emi(freq_params); if (CONFIG(MEMORY_TEST)) { size_t r; -- To view, visit https://review.coreboot.org/c/coreboot/+/35164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Gerrit-Change-Number: 35164 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 69

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019