coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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1442 discussions

Change in coreboot[master]: mb/google/drallion: Disable GBE in firmware for drallion variants
by Thejaswani Putta (Code Review) 02 Oct '19

02 Oct '19

Hello Thejaswani Putta, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35509 to review the following change. Change subject: mb/google/drallion: Disable GBE in firmware for drallion variants ...................................................................... mb/google/drallion: Disable GBE in firmware for drallion variants BUG: None TEST: Build and boot, check if 1f.6 is off on drallion variants Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db --- M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35509/1 diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index f2367ff..8cb1aa3 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -417,6 +417,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Gerrit-Change-Number: 35509 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: intel/baytrail: Replace config_of(dev) with config_of_soc()
by Kyösti Mälkki (Code Review) 02 Oct '19

02 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35670 ) Change subject: intel/baytrail: Replace config_of(dev) with config_of_soc() ...................................................................... intel/baytrail: Replace config_of(dev) with config_of_soc() The function does not otherwise need dev. Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/romstage/pmc.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35670/1 diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 882edf0..2eb3846 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -41,13 +41,11 @@ { uint32_t reg; uint8_t rid; - const struct device *dev; const struct soc_intel_baytrail_config *cfg = NULL; rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = pcidev_on_root(SOC_DEV, SOC_FUNC); - cfg = config_of(dev); + cfg = config_of_soc(); reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Gerrit-Change-Number: 35670 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: coreinfo/coreinfo.c: Support both lower and upper case alphabets
by Name of user not set (Code Review) 02 Oct '19

02 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35538 ) Change subject: coreinfo/coreinfo.c: Support both lower and upper case alphabets ...................................................................... coreinfo/coreinfo.c: Support both lower and upper case alphabets Modify handle_category_key to handle both upper and lower case alphabets in the coreinfo payload. Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M payloads/coreinfo/coreinfo.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35538/1 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index b731abf..e6b7f2e 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -198,7 +198,9 @@ static void handle_category_key(struct coreinfo_cat *cat, int key) { - if (key >= 'a' && key <= 'z') { + if ((key >= 'a' && key <= 'z') || (key >= 'A' && key <= 'Z')) { + if (key >= 'A' && key <= 'Z') + key = key + 32; int index = key - 'a'; if (index < cat->count) { cat->cur = index; -- To view, visit https://review.coreboot.org/c/coreboot/+/35538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Gerrit-Change-Number: 35538 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/google/drallion: dynamic disable memory channel
by EricR Lai (Code Review) 02 Oct '19

02 Oct '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35241 ) Change subject: mb/google/drallion: dynamic disable memory channel ...................................................................... mb/google/drallion: dynamic disable memory channel Disable memory channel by HW strap pin. Using for factory debug. Keep this until the real board come out. BUG=b:139773082 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e --- M src/mainboard/google/drallion/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35241/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..6e62a1e 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -16,6 +16,8 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <gpio.h> +#include <variant/gpio.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -59,5 +61,9 @@ { wilco_ec_romstage_init(); + /* Disable memory channel by HW strap pin */ + memupd->FspmConfig.DisableDimmChannel0 = gpio_get(GPP_F1)? 0 : 3; + memupd->FspmConfig.DisableDimmChannel1 = gpio_get(GPP_F2)? 0 : 3; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Gerrit-Change-Number: 35241 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Create the build directory before bootblock.bin
by Martin Roth (Code Review) 01 Oct '19

01 Oct '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35531 ) Change subject: Makefile: Create the build directory before bootblock.bin ...................................................................... Makefile: Create the build directory before bootblock.bin This was causing a failure when building platforms with no bootblock when building with make -jXX Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35531/1 diff --git a/Makefile.inc b/Makefile.inc index 3c3088d..cf8e470 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -504,7 +504,7 @@ @printf " GEN build.h\n" mv $< $@ -build-dirs: +build-dirs $(objcbfs) $(objgenerated): mkdir -p $(objcbfs) $(objgenerated) ####################################################################### @@ -706,7 +706,7 @@ $(OBJCOPY_bootblock) -O binary $< $@ ifneq ($(CONFIG_HAVE_BOOTBLOCK),y) -$(objcbfs)/bootblock.bin: +$(objcbfs)/bootblock.bin: $(objcbfs) dd if=/dev/zero of=$@ bs=64 count=1 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Gerrit-Change-Number: 35531 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard/amd: Add padmelon doucumentation and images
by Richard Spiegel (Code Review) 01 Oct '19

01 Oct '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34493 ) Change subject: Documentation/mainboard/amd: Add padmelon doucumentation and images ...................................................................... Documentation/mainboard/amd: Add padmelon doucumentation and images Extract publicly available information and pictures from padmelon manual, and make them available to coreboot community. Add information on programming SPI. BUG=none. TEST=none. Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/mainboard/amd/Padmelon.md A Documentation/mainboard/amd/padmelon/padmelon.jpg A Documentation/mainboard/amd/padmelon/padmelon_components.jpg A Documentation/mainboard/amd/padmelon/padmelon_io.jpg A Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg M Documentation/soc/amd/index.md A Documentation/soc/amd/merlinfalcon.md 7 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34493/1 diff --git a/Documentation/mainboard/amd/Padmelon.md b/Documentation/mainboard/amd/Padmelon.md new file mode 100644 index 0000000..2868b05 --- /dev/null +++ b/Documentation/mainboard/amd/Padmelon.md @@ -0,0 +1,66 @@ +# Padmelon board + +## Specs (Merlin Falcon) + +* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs + Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs +* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot code + is specific for Merlin Falcon SOC. Some specs change if not Merlin Falcon. +* One half mini PCI-Express slot on back side of mainboard +* One PCI Express® 3.0 x8 slot +* Two SATA3 ports with 6Gb/s data transfer rate +* Two USB 2.0 ports at rear panel +* Two USB 3.0* ports at rear panel +* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller +* Supports 6-channel High-Definition audio from Realtek ALC662 codec +* One soldered down SPI flash with dediprog header + +## Picture padmelon components mistakes. + +The picture was extracted from manual, however, the numbering on the padmelon board is misplaced. +Of real importance is that (6) is actually the dediprog header to flash the BIOS. +(16) is actually 2 mux chips that acts like a bridge between the SPI and the CPU or the dediprog +header. The bridge will connect the SPI to the header if and only if no power is applied to the CPU, +thugh the board itself can be connected to a power supply that is connected to AC. With or without +AC connected, provided CPU is not powered, SPI can be programmed using dediprog. Once CPU is powered, +dediprog is protected from harm (even if still connected to the header) because the mux will float +the pins. The mux should be the first place to be investigated if you are unable to program the SPI. + +## Flashing coreboot + ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Model | Macronix MX256435E | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| In circuit flashing | no, use dediprog | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +``` + +## Technology + ++---------------+------------------------------+ +| SoC | :doc:`../../soc/amd/index` | ++---------------+------------------------------+ +| CPU | Merlin Falcon SOC | ++---------------+------------------------------+ + +## Pictures + ++----------------------------+----------------------------------------+ +|padmelon.jpg | Motherboard with components identified | ++----------------------------+----------------------------------------+ +|padmelon_components.jpg | Identifying components | ++----------------------------+----------------------------------------+ +|padmelon_io.jpg | Back panel picture | ++----------------------------+----------------------------------------+ +|padmelon_io_description.jpg | Back panel description | ++----------------------------+----------------------------------------+ diff --git a/Documentation/mainboard/amd/padmelon/padmelon.jpg b/Documentation/mainboard/amd/padmelon/padmelon.jpg new file mode 100644 index 0000000..1723f5e --- /dev/null +++ b/Documentation/mainboard/amd/padmelon/padmelon.jpg Binary files differ diff --git a/Documentation/mainboard/amd/padmelon/padmelon_components.jpg b/Documentation/mainboard/amd/padmelon/padmelon_components.jpg new file mode 100644 index 0000000..5574d8a --- /dev/null +++ b/Documentation/mainboard/amd/padmelon/padmelon_components.jpg Binary files differ diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg new file mode 100644 index 0000000..0a515f7 --- /dev/null +++ b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg Binary files differ diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg new file mode 100644 index 0000000..341e610 --- /dev/null +++ b/Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg Binary files differ diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index 7945b48..84d070b 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -4,5 +4,6 @@ ## Technology +- [Merlin Falcon](merlinfalcon.md) - [Family 17h](family17h.md) diff --git a/Documentation/soc/amd/merlinfalcon.md b/Documentation/soc/amd/merlinfalcon.md new file mode 100644 index 0000000..e8a36be --- /dev/null +++ b/Documentation/soc/amd/merlinfalcon.md @@ -0,0 +1,28 @@ +# AMD Merlin Falcon in coreboot + +## Abstract + +Merlin Falcon is a family 15h Models 60-6F SOC, more specifically, 00660F01. + +## Introduction + +Family 15h products are x86-based designs. This documentation assumes +familiarity with x86, its reset state and its early initialization +requirements. + +AMD has historically required an NDA for access to the PSP +specification1. coreboot relies on util/amdfwtool to build +the structures and add various other firmware to the final image. + +Support in coreboot for modern AMD products is based on AMD’s +reference code: AMD Generic Encapsulated Software Architecture +(AGESATM). AGESA contains the technology for enabling DRAM, +configuring proprietary core logic, assistance with generating ACPI +tables, and other features. + +## Additional Definitions + +* PSP, Platform Security Processor: Onboard ARM processor that runs +alongside the main x86 processor; may be viewed as analogous to the +IntelR Management Engine +* FCH, Fusion Control Hub, the logical southbridge within the SOC -- To view, visit https://review.coreboot.org/c/coreboot/+/34493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98 Gerrit-Change-Number: 34493 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/soc/amd: Add family 15h
by Richard Spiegel (Code Review) 01 Oct '19

01 Oct '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34561 ) Change subject: Documentation/soc/amd: Add family 15h ...................................................................... Documentation/soc/amd: Add family 15h Create documentation for AMD family 15h, and in particular to models for which there's coreboot code: Models 60h-6Fh and 70h-7Fh. BUG=none. TEST=none. Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/soc/amd/family15h.md M Documentation/soc/amd/index.md 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34561/1 diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md new file mode 100644 index 0000000..2e583e8 --- /dev/null +++ b/Documentation/soc/amd/family15h.md @@ -0,0 +1,44 @@ +# AMD Family 15h in coreboot + +## Abstract + +Family 15h uses the AMD CPU micro architecture _Excavator_, and is available +in several models with different number of cores and some other small +variations, to attend a broad spectrum of users. Of particular interest for +coreboot are models **60h-6Fh** (_Merlin Falcon_) and **70h-7Fh** (_Stoney Ridge_), +for which there are coreboot implementations. + +## Introduction + +Family 15h products are x86-based designs. This documentation assumes +familiarity with x86, its reset state and its early initialization requirements. + +AMD has historically required an NDA for access to the PSP specification. +coreboot relies on util/amdfwtool to build the structures and add various +other firmware to the final image. + +Support in coreboot for modern AMD products is based on AMD’s +reference code: AMD Generic Encapsulated Software Architecture +(AGESA _**TM**_). AGESA contains the technology for enabling DRAM, +configuring proprietary core logic, assistance with generating ACPI +tables, and other features. + +Some functionality, such as GPIO setting and D0/D3 of some devices such as +I2C and UART were removed from AGESA (though still available on most AGESA +images) and converted to coreboot code for granularity, speed and easy of +use reasons. +>In particular, GPIO achieved a greater control over what is being +>programmed through the use of a table that is easily created using +>macros. + +## Additional Definitions + +* PSP, Platform Security Processor: Onboard ARM processor that runs +alongside the main x86 processor; may be viewed as analogous to the +IntelR Management Engine +* FCH, Fusion Control Hub, the logical southbridge within the SOC + +## References + +1. [Merlin Falcon BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BK… +2. [Stoney Ridge BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models… diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index 7945b48..d6f31c8 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -4,5 +4,6 @@ ## Technology +- [Family 15h](family15h.md) - [Family 17h](family17h.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/34561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Gerrit-Change-Number: 34561 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: allow modifying vcore voltage
by hsin-hsiung wang (Code Review) 01 Oct '19

01 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33391 Change subject: mediatek/mt8183: allow modifying vcore voltage ...................................................................... mediatek/mt8183: allow modifying vcore voltage Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33391/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index c90e6e4..f213c35 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -25,6 +25,9 @@ PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, + PMIC_VCORE_OP_EN = 0x1490, + PMIC_VCORE_DBG0 = 0x149e, + PMIC_VCORE_VOSEL = 0x14aa, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, PMIC_VDRAM1_OP_EN = 0x1610, PMIC_VDRAM1_DBG0 = 0x161e, @@ -43,5 +46,7 @@ void pmic_set_power_hold(bool enable); unsigned int pmic_get_vdram1_vol(void); void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vcore_vol(void); +void pmic_set_vcore_vol(unsigned int vcore_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 409369f..eff0543 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -756,6 +756,29 @@ pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); } +unsigned int pmic_get_vcore_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +void pmic_set_vcore_vol(unsigned int vcore_uv) +{ + unsigned int vol_reg; + + if (vcore_uv < 500000) + vol_reg = 0; + else if (vcore_uv > 1100000) + vol_reg = 0x60; + else + vol_reg = (vcore_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Gerrit-Change-Number: 33391 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: Move intel_ht_sibling() to common folder
by Patrick Rudolph (Code Review) 01 Oct '19

01 Oct '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35619 ) Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ...................................................................... cpu/intel/common: Move intel_ht_sibling() to common folder Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent raceconditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 10 files changed, 60 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/1 diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4074d8c..4fa3aff 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,4 +22,7 @@ config CPU_INTEL_COMMON_TIMEBASE bool +config CPU_INTEL_COMMON_HYPERTHREADING + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index c38e81c..0a84deb 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index b9ac056..480dfe6 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -27,4 +27,9 @@ struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); +/* + * Returns true if it's not threat 0 on a hyperthreading enabled core. + */ +bool intel_ht_sibling(void); + #endif diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c new file mode 100644 index 0000000..a1ac457 --- /dev/null +++ b/src/cpu/intel/common/hyperthreading.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/lapic.h> +#include <cpu/intel/common/common.h> +#include <arch/cpu.h> + +/* Return true if running thread does not have the smallest lapic ID + * within a CPU core. + */ +bool intel_ht_sibling(void) +{ + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + result = cpuid(1); + /* Is hyperthreading supported */ + if (!(result.edx & (1 << 28))) + return 0; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids < 1) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + return !!(lapicid() & (threads-1)); +} diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 3c3e53a..f5bcc87 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -25,30 +25,6 @@ static int first_time = 1; static int disable_siblings = !CONFIG(LOGICAL_CPUS); -/* Return true if running thread does not have the smallest lapic ID - * within a CPU core. - */ -int intel_ht_sibling(void) -{ - unsigned int core_ids, apic_ids, threads; - - apic_ids = 1; - if (cpuid_eax(0) >= 1) - apic_ids = (cpuid_ebx(1) >> 16) & 0xff; - if (apic_ids < 1) - apic_ids = 1; - - core_ids = 1; - if (cpuid_eax(0) >= 4) { - struct cpuid_result result; - result = cpuid_ext(4, 0); - core_ids += (result.eax >> 26) & 0x3f; - } - - threads = (apic_ids / core_ids); - return !!(lapicid() & (threads-1)); -} - void intel_sibling_init(struct device *cpu) { unsigned int i, siblings; diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 9e70775..dcf9441 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -7,3 +7,5 @@ select SMP select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index e759a43..04710a9 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h> static void model_f2x_init(struct device *cpu) diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820..9a5e2a1 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d348df6..48e3872 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h> static void model_f3x_init(struct device *cpu) diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h index c84a6a7..0a1461c 100644 --- a/src/include/cpu/intel/hyperthreading.h +++ b/src/include/cpu/intel/hyperthreading.h @@ -3,6 +3,5 @@ struct device; void intel_sibling_init(struct device *cpu); -int intel_ht_sibling(void); #endif /* CPU_INTEL_HYPERTHREADING_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Gerrit-Change-Number: 35619 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add gameport base for gameport to fix enumeration
by Petr Cvek (Code Review) 01 Oct '19

01 Oct '19

Petr Cvek has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35671 ) Change subject: mb/kontron: Add gameport base for gameport to fix enumeration ...................................................................... mb/kontron: Add gameport base for gameport to fix enumeration A missing definition of PNP io 0x60 base will cause an automatic address assignment during PCI/PNP enumeration, which won't obey already set limit 0x7ff. This will cause the enumeration to fail as other devices already have the values enabled. The symptoms are: not working USB, PS/2, garbled UART console, PCIe GPUs and crashes. Probably because of wrongly assigned IO ports. Example of log (shortened): Done reading resources. Setting resources... !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.0 1c * [0x0 - 0xfff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io !! Resource didn't fit !! aligned base 400 size 10 limit 2e7 40f needs to be <= 2e7 (limit) PCI: 00:1f.2 20 * [0x3080 - 0x308f] io !! Resource didn't fit !! ... ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned ... ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned ... PCI: 00:1b.0 subsystem <- 8086/27d8 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/27d0 PCI: 00:1c.0 cmd <- 107 PCI: 00:1c.1 brids70c01mcu0PeC: 0 dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished (ports probably started to collide after 00:1c.0). A debug run with compiled SPEW shows the problem with enumeration: PCI: 00:1f.1 18 * [0x50b8 - 0x50bf] io PCI: 00:1f.2 10 * [0x50c0 - 0x50c7] io PCI: 00:1f.2 18 * [0x50c8 - 0x50cf] io PCI: 00:1f.1 14 * [0x50d0 - 0x50d3] io PCI: 00:1f.1 1c * [0x50d4 - 0x50d7] io PCI: 00:1f.2 14 * [0x50d8 - 0x50db] io PCI: 00:1f.2 1c * [0x50dc - 0x50df] io PNP: 002e.7 60 * [0x50e0 - 0x50e0] io <- gameport base DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done Notice a weird base for DOMAIN, along with the limit. Adding a definition of gameport (0x220) fixes the problems. The gameport should be still disabled thanks to disable bits (but W83627THF datasheet is somewhat chaotic). I didn't find any info if the gameport is available on some pads. Signed-off-by: Petr Cvek <petrcvekcz(a)gmail.com> Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408 --- M src/mainboard/kontron/986lcd-m/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35671/1 diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 5db7551..08b0703 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -79,6 +79,7 @@ irq 0xf0 = 0x82 # HW accel A20. end device pnp 2e.7 on # GPIO1, GAME, MIDI + io 0x60 = 0x220 io 0x62 = 0x330 irq 0x70 = 9 end -- To view, visit https://review.coreboot.org/c/coreboot/+/35671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408 Gerrit-Change-Number: 35671 Gerrit-PatchSet: 1 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019